CN105097750A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN105097750A
CN105097750A CN201410219030.1A CN201410219030A CN105097750A CN 105097750 A CN105097750 A CN 105097750A CN 201410219030 A CN201410219030 A CN 201410219030A CN 105097750 A CN105097750 A CN 105097750A
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China
Prior art keywords
wire
coating layer
making
base material
electrically connected
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CN201410219030.1A
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English (en)
Inventor
赖杰隆
陈贤文
张宏达
叶懋华
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN105097750A publication Critical patent/CN105097750A/zh
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    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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Abstract

一种封装结构及其制法，该封装结构包括：具有多个电性连接部的基材、设于该基材上的电子组件、立设于各该电性连接部上的多个导线、设于该基材上并包覆该电子组件且外露该些导线的包覆层、以及设于该包覆层上并电性连接该些导线的线路层，所以藉由该些导线作为内联机路，因其线宽小而使各该导线之间的距离能极小化，以缩减该基材的尺寸，而达到微小化的需求。

Description

封装结构及其制法
技术领域
本发明涉及一种封装制程，特别是关于一种应用打线技术的封装结构及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductordevice)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂堆加多个封装结构以形成封装外堆栈结构(PackageonPackage,POP)或封装内堆栈结构(Packageinpackage,PiP)，此种封装方式能发挥***封装(SiP)异质整合特性，可将不同功用的电子组件，例如：内存、中央处理器、绘图处理器、影像应用处理器等，藉由堆栈设计达到***的整合，适合应用于轻薄型各种电子产品。请参阅图3，其为现有封装外堆栈结构(PackageonPackage,POP)的剖面示意图。
如图3所示，现有封装外堆栈结构3是将第二封装件3b叠设于第一封装件3a上。
该第一封装件3a包含具有相对的第一及第二表面31a,31b的第一基板31、及设于该第一表面31a上且电性连接该第一基板31的第一电子组件30。该第二封装件3b包含具有相对的第三及第四表面32a,32b的第二基板32、设于该第三表面32a上且电性连接该第二基板32的第二电子组件35、及包覆该第二电子组件35的封装胶体36。此外，通过于该第一基板31的第一表面31a上形成焊锡球310，以令该第二基板32的第四表面32b藉由该焊锡球310叠设且电性连接于该第一基板31上。又，该第一基板31的第二表面31b上具有植球垫312以供结合焊球34，且该第一及第二电子组件30,35为主动组件及/或被动组件，并以覆晶方式电性连接基板，且藉由底胶33充填于第一及第二电子组件30,35与第一基板31与第二基板32间，以形成覆晶接合。
然而，现有封装外堆栈结构3的体积过大，无法满足微小化的需求，例如，为了避免桥接发生，各该焊锡球310之间需保有一定距离，所以难以缩小第一基板31的尺寸。
另一方面，目前还发展出将芯片立体堆栈化整合为三维集成电路(3DIC)芯片堆栈的技术，例如，于封装基板与半导体芯片之间增设一具有导电硅穿孔(Through-siliconvia,TSV)的硅中介板(ThroughSiliconinterposer,TSI)。由于该硅中介板可采用半导体制程做出3/3μm以下的线宽/线距，所以当该半导体芯片具高I/O数时，该硅中介板的长宽方向的面积足以连接高I/O数的半导体芯片，所以不需增加该封装基板的面积，以满足微小化需求。
然而，于制作现有硅中介板时，该导电硅穿孔的制程需于该硅板上挖孔(即经由曝光显影蚀刻等图案化制程而形成该些穿孔)及金属填孔，致使该导电硅穿孔的整体制程占整个该硅中介板的制作成本达约40～50％(以12寸晶圆为例，不含人工成本)，且制作时间耗时(因前述步骤流程冗长，特别是蚀刻该硅板以形成该些穿孔)，以致最终产品的成本及价格难以降低。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的目的为提供一种封装结构及其制法，以缩减基材的尺寸，而达到微小化的需求。
本发明的封装结构，包括：基材，其具有多个电性连接部；至少一电子组件，其设于该基材上；多个导线，其立设于各该电性连接部上，且各该导线具有相对的第一端及第二端，并以其第一端结合至各该电性连接部；包覆层，其形成于该基材上并包覆该些导线与该电子组件，该包覆层具有相对的第一表面及第二表面，使该包覆层的第一表面结合至该基材与该些电性连接部上，且至少部分该导线的第二端外露于该包覆层的第二表面；以及线路层，其设于该包覆层的第二表面上并电性连接各该导线的第二端。
本发明还提供一种封装结构的制法，其包括：提供一具有多个电性连接部的基材，且该基材上设有至少一电子组件；立设多个具有相对的第一端及第二端的导线于该电性连接部上，且各该导线以其第一端结合至各该电性连接部；形成具有相对的第一表面及第二表面的包覆层于该基材上，以令该包覆层包覆该些导线与该电子组件，且该包覆层的第一表面结合至该基材与该些电性连接部上，而至少部分该导线的第二端外露于该包覆层的第二表面；以及形成线路层于该包覆层的第二表面上，且该线路层电性连接各该导线的第二端。
前述的制法中，该导线以打线接合法形成者。
前述的封装结构及其制法中，该基材还具有线路构造，该线路构造具有相对的第一侧及第二侧，且该电性连接部设于该第一侧上。此外，该线路构造的第二侧形成有多个导电组件，且各该导电组件电性连接该线路构造。又，该基材也可具有载板，且该载板设于该线路构造的第二侧上并电性连接该线路构造，例如，该载板为半导体材、介电材、陶瓷材或金属材，且该载板具有多个导电穿孔，以令该线路构造电性连接该些导电穿孔；或者，于形成该线路层之后，移除该载板。
前述的封装结构及其制法中，该电子组件电性连接该基材。
前述的封装结构及其制法中，该电子组件外露于该包覆层的第二表面。
前述的封装结构及其制法中，该导线的线径为0.01至0.15毫米。
前述的封装结构及其制法中，至少两相邻的该导线之间的距离为0.03至0.3毫米。
前述的封装结构及其制法中，还包括堆栈至少一电子装置于该包覆层的第二表面上，使该电子装置电性连接该线路层。例如，该电子装置以多个导电组件叠设于该线路层上。
另外，该包覆层还具有与该第一及第二表面相邻的侧面，且部分该导线的第二端外露于该侧面。
由上可知，本发明封装结构及其制法中，藉由藉由该导线作为导电路径，其线径可小于0.15㎜，因而使各该导线之间的距离能小于0.3㎜，所以相较于现有技术受限于焊锡球的规格，本发明的封装结构能使各该电性连接部的间距或各该线路层的间距缩小，以增加接点密度，因而能缩小该封装结构的体积，且能增加该电子组件的电性I/O密度。
此外，该导线以简易的现有打线接合方式制作，所以相较于现有硅中介板的制程，本发明的制法能大幅降低成本。
图式简单说明
图1A至图1G为本发明封装结构的制法的第一实施例的剖视示意图；其中，图1D’为图1D的另一实施例，图1F’及图1F”为图1F的其它实施例；
图2A至图2C为本发明封装结构的制法的第二实施例的剖视示意图；
图2D至图2F为本发明封装结构的制法的第三实施例的剖视示意图；其中，图2F’为图2F的另一实施例；以及
图3为现有封装外堆栈结构的剖视示意图。
符号说明
1,1’,2,2’,4,4’,4”封装结构
10,10’,20基材
101,201载板
102离形层
11线路构造
11a第一侧
11b第二侧
12电性连接部
13焊垫
14,24导线
14a,24a第一端
14b,24b第二端
15,15’,15”电子组件
16包覆层
16a,31a第一表面
16b,31b第二表面
16c侧面
160开口
17,17’线路层
18,190,28,290导电组件
19,19’电子装置
190’铜凸块
191,291芯片
200导电穿孔
202电性接触垫
203绝缘材
240RDL
27外接垫
3封装外堆栈结构
3a第一封装件
3b第二封装件
30第一电子组件
31第一基板
310焊锡球
312植球垫
32第二基板
32a第三表面
32b第四表面
33底胶
34焊球
35第二电子组件
36封装胶体
5封装模块
A非布线区
d间距
w线径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、”第三”、”第四”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图1A至图1G为本发明封装结构的制法的第一实施例的剖视示意图。
如图1A所示，提供一具有多个电性连接部12及多个焊垫13的基材10，且该焊垫13上覆晶设有多个电子组件15，使该电子组件15电性连接该基材10。
于本实施例中，该电性连接部12为垫状，且该基材10包含一载板101、一离形层102及线路构造11。具体地，该载板101为半导体材、介电材、陶瓷材、玻璃或金属材，但不限于此，且以涂布或贴合方式形成具粘性的离形层102于该载板101上，并制作一层或多层线路重布层(redistributionlayer,RDL)的线路构造11于该离形层102上。
此外，该线路构造11具有相对的第一侧11a及第二侧11b，且该些电性连接部12与焊垫13设于该线路构造11的第一侧11a上并电性连接该线路构造11，而该焊垫13上形成有凸块底下金属层(UnderBumpMetallurgy,UBM)(图略)以覆晶结合该电子组件15。
又，该载板101利用该离形层102设于该线路构造11的第二侧11b上。
另外，各该电子组件15为平面相邻排设，且该电子组件15为主动组件(如半导体芯片)或被动组件(如电容)；于其它实施例中，该电子组件15也可利用芯片接合膜(dieattachfilm,DAF)或导电胶的方式固设于该基材10上；或者，该电子组件15亦可利用打线方式电性连接该基材10。
如图1B所示，立设多个具有相对的第一端14a及第二端14b的导线14于各该电性连接部12上，且该导线14以其第一端14a结合至该电性连接部12。
于本实施例中，单一该电性连接部12仅结合一条导线14。再者，该导线14以打线接合(WireBonding,WB)方式形成多个直立线状，以作为内联机路结构。
又，各该导线14的线径w可小于0.15毫米(㎜)，且两相邻的该导线14之间的距离d可小于0.3毫米。
如图1C所示，形成具有相对的第一表面16a及第二表面16b的包覆层16于该基材10上，以令该包覆层16包覆各该导线14与该电子组件15，且该包覆层16的第一表面16a结合至该基材10与该电性连接部12上，而全部该导线14的第二端14b外露于该包覆层16的第二表面16b。
于本实施例中，该包覆层16的制程可选择液态封胶(liquidcompound)、喷涂(injection)或模压(compressionmolding)，且于模具内贴有离型膜，以确保移除模具后，该导线14的第二端14b能外露于该包覆层16的第二表面16b。此外，该电子组件15的上表面埋设于该包覆层16中。
如图1D所示，形成一线路层17于该包覆层16的第二表面16b上，且该线路层17的线路部分或接触垫部分电性连接各该导线14的第二端14b，使该线路层17经由该导线14电性连接该电性连接部12。
于本实施例中，该线路层17为一层线路重布层(redistributionlayer,RDL)；于其它实施例中，可依实际需求选择制作多层线路重布层(RDL)于该包覆层16的第二表面16b上。
或者，涂布一有机保焊膜(organicsolderabilitypreservatives,OSP，图略)于该线路层17上，以防止该线路层17的金属表面发生氧化反应而影响讯号传递。
另外，该电子组件15上方的该包覆层16的第二表面16b处可设计为非布线区A，即该非布线区A上不会形成线路(如该线路层17)。因此，可依需求形成多个开口160于该非布线区A上，如图1D’所示，以令各该电子组件15的上表面外露于该包覆层16的第二表面16b，以供散热或外接组件之用。
如图1E所示，移除该离形层102及该载板101，以形成新的基材10’。
如图1F所示，进行切单制程，且形成多个如焊球的导电组件18于该线路构造11的第二侧11b，且该导电组件18电性连接该线路构造11，以藉由该些导电组件18接置如电路板的电子装置(图略)。
本发明的制法中，藉由该导线14作为导电路径，其线宽小于0.15㎜，因而使各该导线14之间的距离d能小于0.3㎜，所以相较于现有技术受限于焊锡球的规格，本发明的封装结构1能符合微小化的需求。
此外，利用该导线14取代现有焊锡球，可使接点(如各该电性连接部12或各该线路层17)的间距密度增加，所以不仅能缩小该封装结构1的体积，且能增加电性I/O的密度。
又，该导线14以简易的现有打线接合方式制作，所以相较于现有硅中介板，本发明的制法能大幅降低成本。
另外，如图1F’所示，该电子组件15’的上表面可齐平该包覆层16的第二表面16b，使该电子组件15’的上表面外露于该包覆层16的第二表面16b；或者，如图1F”所示，各该电子组件15”可相互堆栈于该线路构造11的第一侧11a上，且位于上方的电子组件15”的上表面亦可选择性外露于该包覆层16的第二表面16b。
如图1G所示，接续图1F的制程，堆栈一电子装置19于该包覆层16的第二表面16b上，使该电子装置19电性连接该线路层17，以成为堆栈式封装结构1’。
于本实施例中，该电子装置19为封装件、芯片或基板等，并无特别限制。
此外，该电子装置19以如焊锡凸块、铜凸块的导电组件190电性连接该线路层17。于其它实施例中，该导电组件也可设于该电子组件15的上方。
又，由于能缩小该封装结构1的体积，所以该堆栈式封装结构1’能随的符合微小化的需求。
另外，该电子装置19具有打线式芯片191；于其它实施例中，该电子装置也可具有覆晶式芯片，但芯片的设置方式不限于上述。
图2A至图2C为本发明的封装结构的制法的第二实施例的剖视示意图。本实施例与第一实施例的差异在于载板的设计，其它相同的组件援用相同图号，且相同组件的制程亦不另覆述。
如图2A所示，提供一基材20，该基材包含一载板201及该线路构造11。
于本实施例中，该载板201为半导体材、介电材、陶瓷材或金属材，且该载板201具有多个导电穿孔200。例如，该载板201为半导体材，如硅，以成为具有导电硅穿孔(Through-siliconvia,TSV)的硅中介板(ThroughSiliconinterposer,TSI)，且该线路构造11电性连接该些导电穿孔200，而该导电穿孔200的侧壁周围可选择性形成绝缘材203。
此外，该载板201的下侧具有多个电性连接该导电穿孔200的电性接触垫202。
另外，有关该载板201的种类繁多，且可依需求设计，并不限于此。
如图2B所示，进行如图1B至图1D所述的制程，再形成多个导电组件18于该载板201的电性接触垫202上，以形成封装结构2，使该导电组件18电性连接该些导电穿孔200。
如图2C所示，进行如图1G所述的制程，以形成堆栈式封装结构2’。
于本实施例中，该电子装置19’具有覆晶式芯片291，且该导电组件290还设于该电子组件15的上方，以强化支撑该电子装置19’。具体地，该电子组件15上方的该包覆层16的第二表面16b处可设计至少一外接垫27，以结合该导电组件290，且该外接垫27可电性连接或不电性连接该线路层17。
图2D至图2F为本发明的封装结构的制法的第三实施例的剖视示意图。本实施例与上述实施例的差异在于导线的设计，其它相同的组件援用相同图号，且相同组件的制程亦不另覆述。
如图2D所示，以改良第二实施例的制程为例，立设多个具有相对的第一端14a,24a及第二端14b,24b的导线14,24于各该电性连接部12上，且各该导线14,24以其第一端14a,24a结合至该电性连接部12。
于本实施例中，部分该导线14为直立线状，而另一部分该导线24为弧形线状。
如图2E所示，进行如图1C至图1F所述的制程，以形成封装结构4，且该包覆层16还具有与该第一及第二表面16a,16b相邻的侧面16c，使弧形线状的导线24的第二端24b外露于该侧面16c，以作为电性接点，以供后续制程电性连接电子器材。
于本实施例中，可形成至少一层RDL240于该包覆层16的侧面16c与该导线24的第二端24b上；也可形成UBM(图略)于该导线24的第二端24b上；或者形成异方性导电胶(AnisotropicConductiveFilm,ACF，图略)于该导线24的第二端24b上，以作为电性连接垫。
此外，该电子组件15’的上表面可齐平该包覆层16的第二表面16b，使该电子组件15’的上表面外露于该包覆层16的第二表面16b。
又，该线路层17’也可选择性地形成于该电子组件15’的上表面，且该线路层17’可选择性电性连接该电子组件15’。
如图2F所示，进行如图1G所述的制程，以形成堆栈式封装结构4’。因此，藉由该导线24的第二端24b的设计，该测测装置可将线路牵引至该封装结构4’的侧面，以进行该电子组件15的测试，所以能提升测试的便利性。
于本实施例中，该导电组件290还接触地设于该电子组件15’上的线路层17’，以供该电子组件15’散热或电性连接至该电子装置19。当然地，该导电组件290也可直接地接触该电子组件15’的上表面上。
于其它实施例中，如图2F’所示，于该包覆层16的侧面16c制作RDL(图略)、UBM(图略)、ACF(图略)或OSP(图略)后，可形成用于电性连接该导线24的第二端24b的多个如焊锡材的导电组件28，以利用该些导电组件28并排连接多个封装结构4”，而形成具有水平与垂直电性连接路径的封装模块5。之后，再利用表面贴装技术(SurfaceMountTechnology,SMT)将该封装模块5设于电路板(图略)上。
于本实施例中，焊锡材的导电组件190内部包覆有铜凸块190’，以减少焊锡材的使用量，所以可避免各该导电组件190之间发生桥接现象，而提升产品的良率，且能满足细间距(finepitch)的需求。
本发明提供一种封装结构1,1’,2,2’,4,4’,4”，包括：一基材10’,20、设于该基材上10’,20的至少一电子组件15,15’,15”、多个导线14,24、一包覆层16、以及一线路层17。
所述的基材10’,20具有多个电性连接部12与一线路构造11，该线路构造11具有相对的第一侧11a及第二侧11b，且该电性连接部12设于该第一侧11a上。
所述的电子组件15,15’,15”电性连接该基材10’,20。
所述的导线14,24立设于各该电性连接部12上，且该导线14,24具有相对的第一端14a,24a及第二端14b,24b，并以其第一端14a,24a结合至该电性连接部12。具体地，该导线14,24的线径w为0.01至0.15毫米，且两相邻的导线14,24之间的距离d为0.03至0.3毫米。
所述的包覆层16设于该基材10’,20上并包覆该些导线14,24与该电子组件15,15’,15”，该包覆层16具有相对的第一表面16a及第二表面16b，使该包覆层16的第一表面16a结合至该基材10’,20与该电性连接部12上，且至少部分该导线14的第二端14b外露于该包覆层16的第二表面16b。
所述的线路层17设于该包覆层16的第二表面16b上并电性连接该导线14的第二端14b。
于一实施例中，该线路构造11的第二侧11b形成有多个导电组件18，且各该导电组件18电性连接该线路构造11。
于一实施例中，该基材20更具有一载板201，且该载板201设于该线路构造11的第二侧11b上并电性连接该线路构造11。例如，该载板201为半导体材、介电材、陶瓷材或金属材，且该载板201具有多个导电穿孔200，以令该线路构造11电性连接该些导电穿孔200。
于一实施例中，该电子组件15’外露于该包覆层16的第二表面16b。
于一实施例中，该封装结构1’,2’还包括至少一电子装置19,19’，其堆栈于该包覆层16的第二表面16b上并电性连接该线路层17，其中，该电子装置19,19’以多个导电组件190叠设于该线路层17上。
于一实施例中，该包覆层16还具有与该第一及第二表面16a,16b相邻的侧面16c，且部分该导线24的第二端24b外露于该侧面16c。
综上所述，本发明封装结构及其制法，主要藉由该导线作为导电路径，因其线宽小而使各该导线之间的距离能极小化，所以不仅能符合微小化的需求，且能大幅降低成本。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (28)

1.一种封装结构，包括：
基材，其具有多个电性连接部；
至少一电子组件，其设于该基材上；
多个导线，其立设于各该电性连接部上，且各该导线具有相对的第一端及第二端，并以其第一端结合至各该电性连接部；
包覆层，其形成于该基材上并包覆该些导线与该电子组件，该包覆层具有相对的第一表面及第二表面，使该包覆层的第一表面结合至该基材与该些电性连接部上，且至少部分该导线的第二端外露于该包覆层的第二表面；以及
线路层，其设于该包覆层的第二表面上并电性连接各该导线的第二端。
2.如权利要求1所述的封装结构，其特征在于，该基材还具有线路构造，该线路构造具有相对的第一侧及第二侧，且该电性连接部设于该第一侧上。
3.如权利要求2所述的封装结构，其特征在于，该线路构造的第二侧形成有多个导电组件，且各该导电组件电性连接该线路构造。
4.如权利要求2所述的封装结构，其特征在于，该基材更具有载板，且该载板设于该线路构造的第二侧上并电性连接该线路构造。
5.如权利要求4所述的封装结构，其特征在于，该载板具有多个导电穿孔，以令该线路构造电性连接该些导电穿孔。
6.如权利要求4所述的封装结构，其特征在于，该载板为半导体材、介电材、陶瓷材或金属材。
7.如权利要求1所述的封装结构，其特征在于，该电子组件电性连接该基材。
8.如权利要求1所述的封装结构，其特征在于，该电子组件外露于该包覆层的第二表面。
9.如权利要求1所述的封装结构，其特征在于，该导线的线径为0.01至0.15毫米。
10.如权利要求1所述的封装结构，其特征在于，至少两相邻的该导线之间的距离为0.03至0.3毫米。
11.如权利要求1所述的封装结构，其特征在于，该封装结构还包括至少一电子装置，其堆栈于该包覆层的第二表面上并电性连接该线路层。
12.如权利要求11所述的封装结构，其特征在于，该电子装置以多个导电组件叠设于该线路层上。
13.如权利要求1所述的封装结构，其特征在于，该包覆层还具有与该第一及第二表面相邻的侧面，且部分该导线的第二端外露于该侧面。
14.一种封装结构的制法，包括：
提供一具有多个电性连接部的基材，且该基材上设有至少一电子组件；
立设多个具有相对的第一端及第二端的导线于该电性连接部上，且各该导线以其第一端结合至各该电性连接部；
形成具有相对的第一表面及第二表面的包覆层于该基材上，以令该包覆层包覆该些导线与该电子组件，且该包覆层的第一表面结合至该基材与该些电性连接部上，而至少部分该导线的第二端外露于该包覆层的第二表面；以及
形成线路层于该包覆层的第二表面上，且该线路层电性连接各该导线的第二端。
15.如权利要求14所述的封装结构的制法，其特征在于，该基材还具有线路构造，该线路构造具有相对的第一侧及第二侧，且该电性连接部设于该第一侧上。
16.如权利要求15所述的封装结构的制法，其特征在于，该线路构造的第二侧形成有多个导电组件，且各该导电组件电性连接该线路构造。
17.如权利要求15所述的封装结构的制法，其特征在于，该基材更具有载板，且该载板设于该线路构造的第二侧上并电性连接该线路构造。
18.如权利要求17所述的封装结构的制法，其特征在于，该制法还包括于形成该线路层之后，移除该载板。
19.如权利要求17所述的封装结构的制法，其特征在于，该载板具有多个导电穿孔，以令该线路构造电性连接该些导电穿孔。
20.如权利要求17所述的封装结构的制法，其特征在于，该载板为半导体材、介电材、陶瓷材或金属材。
21.如权利要求14所述的封装结构的制法，其特征在于，该电子组件电性连接该基材。
22.如权利要求14所述的封装结构的制法，其特征在于，该电子组件外露于该包覆层的第二表面。
23.如权利要求14所述的封装结构的制法，其特征在于，该导线以打线接合法形成者。
24.如权利要求14所述的封装结构的制法，其特征在于，该导线的线径为0.01至0.15毫米。
25.如权利要求14所述的封装结构的制法，其特征在于，至少两相邻的该导线之间的距离为0.03至0.3毫米。
26.如权利要求14所述的封装结构的制法，其特征在于，该制法还包括堆栈至少一电子装置于该包覆层的第二表面上，使该电子装置电性连接该线路层。
27.如权利要求26所述的封装结构的制法，其特征在于，该电子装置以多个导电组件叠设于该线路层上。
28.如权利要求14所述的封装结构的制法，其特征在于，该包覆层还具有与该第一及第二表面相邻的侧面，且部分该导线的第二端外露于该侧面。
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