CN104882417A - 集成无源倒装芯片封装 - Google Patents

集成无源倒装芯片封装 Download PDF

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Publication number
CN104882417A
CN104882417A CN201510088584.7A CN201510088584A CN104882417A CN 104882417 A CN104882417 A CN 104882417A CN 201510088584 A CN201510088584 A CN 201510088584A CN 104882417 A CN104882417 A CN 104882417A
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integrated circuit
tsv
coupled
circuit die
metal layer
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CN201510088584.7A
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CN104882417B (zh
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侯有才
李秀奇
戴慧洋
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申請案涉及集成无源倒装芯片封装。一种用于封装集成电路裸片使得每一封装包含裸片的方法，其中集成无源组件安装到所述裸片的背面、有源表面或所述背面及有源表面两者上。

Description

集成无源倒装芯片封装
技术领域
本发明大体上涉及集成电路(IC)的封装。更特定来说，描述了用于生产包含集成无源组件的IC封装的方法及***。
背景技术
存在许多用于封装集成电路(IC)裸片的常规工艺。举例来说，许多IC封装利用已由金属薄片印刻或蚀刻而成的金属引线框来提供与外部装置的电互连件。裸片可借助接合线、焊料凸块或其它合适电连接来电连接到引线框。一股来说，裸片及引线框的部分以模制材料囊封以保护裸片的有源侧上的精细电组件，同时使引线框的所选择部分暴露以促进与外部装置的电连接。
所得的IC封装通常安装到印刷电路板(PCB)上。PCB用于机械支撑包含IC封装的电子组件且使用导电通路或迹线电连接包含IC封装的电子组件，所述导电通路或迹线通常由层压到非导电衬底上的铜薄片蚀刻而成。在许多应用中，希望沿着迹线中的一些定位多种非有源(或无源)组件来中断裸片与外部装置或电力供应器之间的某些信号传输路径。举例来说，电阻器、电容器和/或电感器中的一或多者通常安装到PCB上。举例来说，旁路电容器通常用来使电路的一部分与另一部分解耦。更具体来说，旁路电容器可用来绕过电力供应器或电路的其它高阻抗组件。
在晶片制造期间构建集成电路的无源组件由于需要较高电感、电容或电阻而对性能具有限制。
常规导线接合封装的引线上的无源组件的直接接触提供与集成无源组件类似的功能；然而，此方式存在缺点。这些缺点包括(但不限于)：封装装置的较大占用面积(以便包括引线上的无源组件)、较高封装成本(其归因于无源附接(通常使用焊料回流工艺)及额外导线接合两者的要求)及(最后)集成电路裸片及无源组件之间的较长电信号路径(其影响能源损耗)。
随着移动装置的大小演变得越来越小，需要封装装置的较小占用面积。
因而，需要一种集成电路及无源组件的组合的经改进封装。
发明内容
下文呈现经简化总结以便提供本发明的一个或多个方面的基本理解。此总结并不是本发明的广泛概述，且既不希望识别本发明的关键或重要元素，也不希望划定本发明的范围。实情是，本总结的主要目的是以简化形式呈现本发明的一些概念作为稍后呈现的更详细描述的序言。
根据本申请案的实施例，提供一种封装集成电路装置。所述封装集成电路装置包括：引线框，其具有多根引线；集成电路裸片，其具有有源表面及背面；所述集成电路裸片的有源表面包含第一组接合垫、多个金属化层(其覆在形成在裸片的半导体衬底内的有源电路上)、中间电介质层(其插置在金属化层之间以使金属化层物理分离且电分离)、导电通孔(其在适当位置处形成在电介质层中以在所要位置中电连接金属化层的特定部分)；至少一对穿硅通孔(TSV)，TSV具有第一端及第二端，其中每一TSV的第一端耦合到集成电路裸片的有源表面的金属互连图案，且TSV的第二端与集成电路裸片的背面共面。每一TSV在TSV的每一端上具有可焊接的凸块底部金属化物UBM；至少一个表面安装无源装置；其中至少一个表面安装无源装置安装在集成电路裸片的顶部或底部上且耦合到至少一对TSV；多个接合垫中的第一组接合垫通过焊料球耦合到引线框的引线；及模制化合物，其囊封组合件，其中模制化合物保护所述组合件免受外部环境影响，同时使引线框的引线暴露于外界以用于耦合到更复杂的电***中。
根据本申请案的另一实施例，提供一种封装集成电路装置的方法。封装集成电路装置的方法包括：提供引线框，其具有多根引线；提供集成电路晶片，所述晶片包含大量集成电路裸片，每一裸片具有源表面及背面，每一裸片的有源表面包括第一组接合垫及第二组接合垫，所述裸片的背面组合以形成品片的背面；形成多个金属化层，其覆在形成在裸片的半导体衬底内的有源电路上；形成中间电介质层，其插置在金属化层之间以使金属化层物理分离且电分离；在适当位置处在电介质层中形成导电通孔以在所要位置中电连接金属化层的特定部分；形成至少一对穿硅通孔(TSV)，TSV具有第一端及第二端，其中每一TSV的第一端耦合到集成电路裸片的有源表面上的金属互连图案，且TSV的第二端与集成电路裸片的背面共面；在TSV的每一端上形成可焊接的凸块底部金属化物UBM；提供至少一个表面安装无源装置；在集成电路裸片的顶部或底部上安装至少一个表面安装无源装置且将其耦合到至少一对TSV；使用焊料球将第一组接合垫耦合到引线框的多根引线中的每一根；及使用模制化合物囊封组合件，其中模制化合物保护所述组合件免受外部环境影响，同时使引线框的引线暴露于外界以用于耦合到更复杂的电***中。
附图说明
结合附图将更容易地理解以下详细的描述，其中：
图1是根据本发明的一个实施例的示范性晶片的俯视图，其详细示出了行、列、切割线及集成电路裸片。
图2是根据本发明的一个实施例的沿图1的截面A：A’截取的示范性集成电路裸片的横截面图，其详细示出了集成表面安装。
图3是根据本发明的一个实施例的示范性封装的横截面图，其详细示出了倒装芯片安装的集成电路，其中表面安装无源装置安装到集成电路裸片的顶部及底部两者。
图4是根据本发明的一个实施例的示范性封装的横截面图，其详细示出了倒装芯片安装的集成电路，其中表面安装无源装置安装到集成电路裸片的底部。
图5是根据本发明的一个实施例的示范性封装的横截面图，其详细示出了倒装芯片安装的集成电路，其中无源表面安装装置安装到集成电路裸片的顶部(有源侧)。
在图式中，相同参考数字有时用来标示相同结构元件。还应理解，图中的描绘是示意性的且不按比例。
具体实施方式
参考附图描述本发明。所述图不按比例绘制且仅提供所述图来说明本发明。下文参考用于说明的实例应用描述本发明的若干方面。应理解，陈述许多具体细节、关系及方法以提供对本发明的理解。然而，相关领域的技术人员将容易地认识到，本发明可在没有所述具体细节中的一或多者的情况下实践或用其它方法实践。在其它情况中，为避免使本发明变得模糊，未详细展示众所周知的结构或操作。本发明不受所描述的动作或事件的顺序的限制，这是因为一些动作可按不同顺序发生和/或与其它动作或事件同时发生。此外，并非需要所有所说明的动作或事件来实施根据本发明的方法。
本发明大体上涉及集成电路(IC)的封装。更特定来说，描述用于生产包含集成无源组件的IC封装的方法及***。
图1展示包含大量裸片51的半导体晶片50的实例。如此项技术中众所周知，大多数晶片及裸片由硅(Si)形成，但也可使用任何其它合适的半导体材料。熟悉此项技术的人员将了解，现有技术水平的晶片通常将具有形成在其中的数百到数千个裸片，且期望在未来晶片中可达到甚至更高的装置密度。裸片大体上形成为行52及列53的二维阵列，其中每一行/列通过切割线54(又被称为锯道)与紧邻行/列分离。每一裸片在从晶片单件化之后都将变成IC组件。每一裸片具有包括金属互连图案及多个接合垫的有源表面及背面。
图2是实例倒装芯片集成电路100的实施例的横截面图。集成电路100包含至少一对穿硅通孔(TSV)103，TSV各自具有第一端及第二端，其中每一TSV的第一端耦合到裸片的有源表面的金属互连图案，且TSV的第二端与裸片的背面共面。每一TSV在TSV的每一端上具有可焊接的金属化物UBM 108。集成电路100的有源表面通常具有多个金属化层，其覆在形成在裸片的半导体衬底内的有源电路上。中间电介质层106通常插置在金属化层之间以使金属化层物理分离且电分离。导电通孔在适当位置处形成在电介质层中以在所要位置中电连接金属化层的特定部分。
多种金属化层可用作接地/电源平面及/或用作IC裸片内的信号路由互连件。多种材料可用来形成电介质层及金属化层。举例来说，铝(AL)及铜(Cu)通常是用于金属化层的材料，且(在基于Si的装置中)二氧化硅、氮化硅及/或其它氧化物及氮化物通常用来形成电介质层。通过每一裸片上的有源表面上的最外层的电介质层或钝化层中的多种开口来使最顶层的金属化层的所选择部分暴露以形成用作裸片的电接触件的多个接合垫107(也称为“I/O垫”)，其中凸块底部金属化物(UBM)107覆盖经暴露的多个接合垫，从而提供可焊接的表面。
图3是耦合到引线框104的实例倒装芯片集成电路100的实施例的横截面图，其中无源表面安装装置105在封装200内安装到集成电路的两侧，封装200包括具有至少一对穿硅通孔(TSV)103的集成电路，TSV具有第一端、第二端及侧壁，其中每一TSV的第一端耦合到集成电路裸片的有源表面的金属互连图案，且TSV的第二端与集成电路裸片的背面共面。每一TSV在TSV的每一端上具有可焊接的金属化物UBM 108。表面安装无源装置105安装在集成电路裸片的底部上且耦合到至少一对TSV 103，且另一表面安装无源装置105安装在集成电路的顶部上且也耦合到至少一对TSV 103。
通过穿过裸片蚀刻通孔、在所述通孔的壁上沉积绝缘层102(例如，二氧化硅、氮化硅、氧化物-氮化物-氧化物、氧化铪或氧化铝)而形成TSV 103。接着，将粘合层101沉积在绝缘层102(例如，钽-氮化钽或钛-氮化钛)上。随后，使用导电材料(例如，钨或铜)填充通孔腔。且最后在通孔的顶部端及底部端上提供可焊接的金属化物108UBM。
接着，通过将无源组件焊接到集成电路且以倒装芯片方式将集成电路焊接到引线框104来组装集成电路及其无源组件。接着，将组合件囊封在模制化合物109中以保护所述组合件免受外部环境影响，同时使引线框的引线暴露于外界以用于耦合到更复杂的电***中。
在图3的所说明的实施例中，每一裸片包含至少一对穿硅通孔(TSV)103，其中TSV103中的每一者具有耦合到每一端的可焊接金属化物UBM 108。多个接合垫107中的每一者通过焊料球耦合到引线框的引线。
图4是耦合到引线框104的实例倒装芯片集成电路100的另一个实施例的横截面图，其中无源表面安装装置105在封装300中安装到集成电路的底部，封装300包含具有至少一对穿硅通孔(TSV)103的集成电路，表面安装无源装置105安装在集成电路的底部上且耦合到至少一对TSV 103。
接着，通过将无源组件焊接到集成电路且以倒装芯片方式将集成电路焊接到引线框104来组装集成电路及其无源组件。接着，将组合件囊封在模制化合物109中以保护组合件免受外部环境影响，同时使引线框的引线暴露于外界以用于耦合到更复杂的电***中。
图5是耦合到引线框104的实例倒装芯片集成电路100的另一个实施例的横截面图，其中无源表面安装装置105在封装400中安装到集成电路的顶部，封装400中包含具有至少一对穿硅通孔(TSV)103的集成电路，表面安装无源装置105耦合到至少一对TSV103且安装在集成电路的顶部(有源侧)。
接着，通过将无源组件焊接到集成电路且以倒装芯片方式将集成电路焊接到引线框104来组装集成电路及其无源组件。接着，将组合件囊封在模制化合物109中以保护组合件免受外部环境影响，同时使引线框的引线暴露于外界以用于耦合到更复杂的***中。
以上描述出于解释目的而使用特定术语来提供对本发明的透彻理解。然而，所属领域的技术人员将明白，不需要具体细节来实践本发明。因此，出于说明及描述的目的呈现本发明的特定实施例的以上描述。以上描述不希望是详尽的或将本发明限于所揭示的精确形式。所属领域的一股技术人员将明白，鉴于以上教示，存在许多修改及变型。举例来说，无源组件可在晶片单件化之前或之后安装到裸片的有源表面上。
虽然已在上文描述本发明的多种实施例，但应理解，仅作为实例而非作为限制呈现所述实施例。可根据本发明对所揭示的实施例做出各种改变而不背离本发明的精神或范围。因此，本发明的广度及范围不应受由上文所述的实施例中的任何者限制。实情是，应根据所附权利要求书及其等效物界定本发明的范围。

Claims (16)

1.一种封装集成电路装置，其包括：
引线框，其具有多根引线；
集成电路裸片，其具有有源表面及背面；
所述集成电路裸片的所述有源表面包含：第一组接合垫、覆在形成在所述裸片的半导体衬底内的有源电路上的多个金属化层、插置在所述金属化层之间以使所述金属化层物理分离且电分离的中间电介质层、在适当位置处形成在所述电介质层中以在所要位置中电连接所述金属化层的特定部分的导电通孔；
至少一对穿硅通孔TSV，所述TSV具有第一端及第二端，其中所述每一TSV的所述第一端耦合到所述集成电路裸片的所述有源表面的金属互连图案，且所述TSV的所述第二端与所述集成电路裸片的所述背面共面，每一TSV在所述TSV的每一端上具有可焊接的凸块底部金属化物UBM；
至少一个表面安装无源装置；
其中所述至少一个表面安装无源装置安装在所述集成电路裸片的顶部或底部上且耦合到所述至少一对TSV；
多个接合垫中的所述第一组接合垫通过焊料球耦合到所述引线框的引线；以及
模制化合物，其囊封组合件，其中所述模制化合物保护所述组合件免受外部环境影响，同时使所述引线框的所述引线暴露于外界以耦合到更复杂的电***中。
2.根据权利要求1所述的封装集成电路装置，其中TSV包括：
第一端、第二端及侧壁，其从所述裸片延伸，在所述通孔的所述侧壁上包含选自由以下组成的群组的绝缘层：所述通孔的所述壁上的二氧化硅、氮化硅、氧化物-氮化物-氧化物、氧化铪或氧化铝；
粘合层，其覆盖所述绝缘层，所述粘合层选自由钽-氮化钽或钛-氮化钛组成的群组；且最终使用选自由钨或铜组成的群组的导电材料填充通孔腔。
3.根据权利要求1所述的封装集成电路装置，其中所述表面安装无源装置选自由电阻器、电容器或电感器组成的群组。
4.根据权利要求1所述的封装集成电路装置，其中所述集成电路裸片上的所述金属化层是铝或铜。
5.根据权利要求1所述的封装集成电路装置，其中在所述集成电路裸片上的所述金属化层之间的所述电介质层是二氧化硅或氮化硅。
6.根据权利要求1所述的封装集成电路装置，其中所述至少一个表面安装无源装置安装在所述集成电路裸片的所述顶部上且耦合到所述至少一对TSV。
7.根据权利要求1所述的封装集成电路装置，其中所述至少一个表面安装无源装置安装在所述集成电路裸片的所述底部上且耦合到所述至少一对TSV。
8.根据权利要求1所述的封装集成电路装置，其中存在至少两个表面安装无源装置，至少一个安装在所述集成电路裸片的所述底部上且耦合到所述至少一对TSV，且至少一个安装在所述集成电路裸片的所述顶部上且耦合到所述至少一对TSV。
9.一种封装集成电路装置的方法，其包括：
提供引线框，所述引线框具有多根引线；
提供集成电路晶片，所述晶片包括大量集成电路裸片，每一裸片具有有源表面及背面，每一裸片的所述有源表面包含第一组接合垫及第二组接合垫，所述裸片的所述背面组合以形成所述晶片的背面；
形成多个金属化层，所述多个金属化层覆在形成在所述裸片的半导体衬底内的有源电路上；
形成中间电介质层，所述中间电介质层插置在所述金属化层之间以使所述金属化层物理分离且电分离；
在适当位置处在所述电介质层中形成导电通孔，以便在所要位置中电连接所述金属化层的特定部分；
形成至少一对穿硅通孔TSV，所述TSV具有第一端及第二端，其中所述每一TSV的所述第一端耦合到所述集成电路裸片的所述有源表面的金属互连图案，且所述TSV的所述第二端与所述集成电路裸片的所述背面共面；
在所述TSV的每一端上形成可焊接的凸块底部金属化物UBM；
提供至少一个表面安装无源装置；
在所述集成电路裸片的顶部或底部上安装所述至少一个表面安装无源装置并将其耦合到所述至少一对TSV；
使用焊料球将所述第一组接合垫耦合到所述引线框的所述多根引线中的每一者；及
使用模制化合物囊封组合件，其中所述模制化合物保护所述组合件免受外部环境影响，同时使所述引线框的所述引线暴露于外界以用于耦合到更复杂的电***中。
10.根据权利要求9所述的封装集成电路装置的方法，其中TSV包括：
提供第一端、第二端及延伸通过所述裸片的侧壁，包含沉积在所述通孔的所述侧壁上的选自由以下组成的群组的绝缘层：二氧化硅、氮化硅、氧化物-氮化物-氧化物、二氧化铪或氧化铝；
沉积覆盖所述绝缘层的选自由钽-氮化钽或钛-氮化钛组成的群组的粘合层；及最终使用选自由钨或铜中组成的群组的导电材料填充通孔腔。
11.根据权利要求9所述的封装集成电路装置的方法，其中所述表面安装无源装置选自由电阻器、电容器或电感器组成的群组。
12.根据权利要求9所述的封装集成电路装置的方法，其中形成在所述集成电路裸片上的所述金属化层是铝或铜。
13.根据权利要求9所述的封装集成电路装置的方法，其中形成在所述集成电路裸片上的所述金属化层之间的所述电介质层是二氧化硅或氮化硅。
14.根据权利要求9所述的封装集成电路装置的方法，其中所述至少一个表面安装无源装置安装在所述集成电路裸片的所述顶部上且耦合到所述至少一对TSV。
15.根据权利要求9所述的封装集成电路装置的方法，其中所述至少一个表面安装无源装置安装在所述集成电路裸片的所述底部上且耦合到所述至少一对TSV。
16.根据权利要求9所述的封装集成电路装置的方法，其中存在至少两个表面安装无源装置，至少一个安装在所述集成电路裸片的所述底部上且耦合到所述至少一对TSV，且至少一个安装在所述集成电路裸片的所述顶部上且耦合到所述至少一对TSV。
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