CN105225925A - 用于互连件覆盖应用的金属互连件中的碳基污染物的清洁 - Google Patents
用于互连件覆盖应用的金属互连件中的碳基污染物的清洁 Download PDFInfo
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- CN105225925A CN105225925A CN201510359303.7A CN201510359303A CN105225925A CN 105225925 A CN105225925 A CN 105225925A CN 201510359303 A CN201510359303 A CN 201510359303A CN 105225925 A CN105225925 A CN 105225925A
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- silane
- based agent
- copper
- substrate
- dielectric
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 80
- 239000002184 metal Substances 0.000 title claims abstract description 80
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 41
- 239000003344 environmental pollutant Substances 0.000 title claims abstract description 33
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- 239000010949 copper Substances 0.000 claims abstract description 101
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 98
- 229910000077 silane Inorganic materials 0.000 claims abstract description 98
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- 230000008676 import Effects 0.000 claims description 4
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- NBBQQQJUOYRZCA-UHFFFAOYSA-N diethoxymethylsilane Chemical compound CCOC([SiH3])OCC NBBQQQJUOYRZCA-UHFFFAOYSA-N 0.000 claims description 3
- NKSJNEHGWDZZQF-UHFFFAOYSA-N ethenyl(trimethoxy)silane Chemical compound CO[Si](OC)(OC)C=C NKSJNEHGWDZZQF-UHFFFAOYSA-N 0.000 claims description 3
- GCSJLQSCSDMKTP-UHFFFAOYSA-N ethenyl(trimethyl)silane Chemical compound C[Si](C)(C)C=C GCSJLQSCSDMKTP-UHFFFAOYSA-N 0.000 claims description 3
- RSIHJDGMBDPTIM-UHFFFAOYSA-N ethoxy(trimethyl)silane Chemical compound CCO[Si](C)(C)C RSIHJDGMBDPTIM-UHFFFAOYSA-N 0.000 claims description 3
- QULMGWCCKILBTO-UHFFFAOYSA-N n-[dimethylamino(dimethyl)silyl]-n-methylmethanamine Chemical compound CN(C)[Si](C)(C)N(C)C QULMGWCCKILBTO-UHFFFAOYSA-N 0.000 claims description 3
- CWMFRHBXRUITQE-UHFFFAOYSA-N trimethylsilylacetylene Chemical compound C[Si](C)(C)C#C CWMFRHBXRUITQE-UHFFFAOYSA-N 0.000 claims description 3
- KAHVZNKZQFSBFW-UHFFFAOYSA-N n-methyl-n-trimethylsilylmethanamine Chemical compound CN(C)[Si](C)(C)C KAHVZNKZQFSBFW-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 125000003545 alkoxy group Chemical group 0.000 description 3
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- 150000002739 metals Chemical class 0.000 description 3
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- ATNSDOISPHKKST-UHFFFAOYSA-N C(=O)=CC(C)(C)C#C.[Co] Chemical compound C(=O)=CC(C)(C)C#C.[Co] ATNSDOISPHKKST-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
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- 125000003368 amide group Chemical group 0.000 description 2
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- XLJKHNWPARRRJB-UHFFFAOYSA-N cobalt(2+) Chemical compound [Co+2] XLJKHNWPARRRJB-UHFFFAOYSA-N 0.000 description 2
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- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- CSJDCSCTVDEHRN-UHFFFAOYSA-N methane;molecular oxygen Chemical compound C.O=O CSJDCSCTVDEHRN-UHFFFAOYSA-N 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
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- 125000001424 substituent group Chemical group 0.000 description 2
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- NWZSZGALRFJKBT-KNIFDHDWSA-N (2s)-2,6-diaminohexanoic acid;(2s)-2-hydroxybutanedioic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O.NCCCC[C@H](N)C(O)=O NWZSZGALRFJKBT-KNIFDHDWSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
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- 241001269238 Data Species 0.000 description 1
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Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
- C23C16/16—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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Abstract
本发明涉及用于互连件覆盖应用的金属互连件中的碳基污染物的清洁。驻留在铜线和电介质扩散阻挡层之间的接口处的保护性覆盖物用于改善互连件的各种操作特性。诸如含钴覆盖物或含锰覆盖物之类的覆盖物使用CVD或者ALD方法在存在暴露的电介质的条件下选择性地沉积到暴露的铜线上。所述覆盖材料的沉积受到铜表面上的含碳污染物的影响,其会导致覆盖层的增长较差或者不均匀。在沉积覆盖物之前从铜表面去除含碳污染物的方法涉及使含有暴露铜表面的衬底与硅烷基化剂在第一温度下接触以在铜表面上形成已反应的硅烷基化剂层,接着在更高的温度下加热衬底以从铜表面释放已反应的硅烷基化剂。
Description
技术领域
本发明涉及在部分制成的集成电路上形成材料层的方法。具体地说,本发明涉及用于互连件覆盖应用的清洁金属互连件中的碳基污染物的方法。
背景技术
镶嵌处理是用于在集成电路上形成金属线的方法。该方法涉及在形成于电介质层(层间电介质)中的沟槽和通孔中形成镶嵌式金属线。镶嵌处理通常是一种优选的方法,因为此方法相比于其他方法需要较少的处理步骤,并提供了较高的产率。该方法也特别适合于不能轻易通过等离子体蚀刻所图案化的金属(诸如铜)。
在典型的镶嵌处理中,金属沉积到图案化的电介质上以填充形成在电介质层中的通孔和沟槽。所得的金属化层通常直接形成在承载有源器件的层上或者形成在下伏的金属化层上。电介质扩散阻挡材料(如碳化硅或氮化硅)薄层沉积在相邻的金属化层之间,以防止金属扩散到电介质的主体层。在一些情况下,碳化硅或氮化硅电介质扩散阻挡层还兼作在层间电介质(ILD)的图案化期间的蚀刻停止层。
在典型的集成电路(IC)中,若干金属化层一层一层地沉积以形成堆叠,其中,金属填充的通孔和沟槽充当集成电路导电路径。一个金属化层的导电路径通过一系列镶嵌互连件被连接到下伏层或上覆层的导电路径。
这些互连件的制造提出了若干挑战,随着IC器件特征的尺寸不断缩小,这些挑战变得越来越显著。例如,铜金属与上覆的电介质扩散阻挡层的粘附通常是较差的,这导致所形成的IC器件的可靠性降低。此外,铜线尺寸的大幅降低导致电迁移增加。在一些情况下,覆盖层沉积在铜的顶部上以解决这些问题并提高互连件的稳定性。
发明内容
在集成电路制造期间所遇到的一个挑战性问题是带有含碳残余物的金属线表面的污染。这种污染的存在会阻碍覆盖物在金属线上的沉积。例如,当含金属的覆盖物(如含钴覆盖物或含锰覆盖物)通过化学气相沉积(CVD)或原子层沉积(ALD)沉积在受碳污染的表面上时,可能导致低的沉积速率、斑块状和不均匀的沉积。此外,当沉积含金属的导电覆盖物层时,这样的覆盖层应当选择性地沉积在金属线表面上而不应当沉积在ILD表面周围。在许多情况下,金属线的表面上的碳基污染物的存在减少了这种沉积的选择性。
含有氧化物物质(如铜氧化物)的污染可通过用还原剂处理衬底(例如,通过等离子体或还原环境下的热处理)被容易除去时,含有含碳物质的污染一般不容易处理。出乎意料的是,发现了用于使用硅烷基化剂从金属表面去除碳基污染物的处理。这种处理可用于去除碳基污染物(例如含有碳-碳和/或碳-氧键的污染物)以清洁诸如铜、钴和镍(包括它们的合金)之类的金属。
在一个方面中,本发明提供了一种用于形成半导体器件结构的方法。该方法涉及:(a)提供包含暴露金属层(如铜,钴,镍)和暴露电介质层的半导体衬底;(b)使所提供的半导体衬底与硅烷基化剂在第一温度下接触,以使所述硅烷基化剂与所述暴露金属层的表面上的含碳污染物反应;以及(c)在接触之后,在更高温度下加热所述半导体衬底以从所述半导体衬底的金属表面去除已反应的硅烷基化剂。接下来,在从所述金属表面去除所述已反应的硅烷基化剂之后,处理继续,选择性地沉积覆盖层在所述金属表面上,而不将相同覆盖层沉积在所述电介质层上。在覆盖层被选择性地形成在金属线上之后,在所述覆盖金属层上和所述暴露电介质上沉积电介质扩散阻挡层(例如,掺杂的或者非掺杂的碳化硅或者氮化硅)。
所提供的方法特别适用于含金属覆盖层的沉积,所述金属覆盖层如钴覆盖层和锰覆盖层。在一些实施方式中,所述覆盖层是通过使经处理的所述衬底与有机金属化合物接触而形成。例如,所述衬底可与包含钴和配体的有机钴合物接触,所述配体选自由烯丙基、脒基(amidinate)、二氮杂二烯基和环戊二烯基所构成的组。用于选择性沉积含钴覆盖层的适当有机钴化合物的实例包括但不限于:羰基叔丁基乙炔钴、苯并钴(cobaltacene)、环戊二烯基二羰基钴(II)、钴脒(cobaltamidinate)、二氮杂二烯钴、以及这些化合物的组合。
在一些实施方式中,所提供的方法还包括在使所述衬底与所述硅烷基化剂接触之前预处理所述衬底以调整所述衬底的表面。能够执行预处理来使电介质表面针对覆盖材料的沉积和/或从金属表面去除金属氧化物(如铜氧化物)更加惰性。预处理能够通过直接等离子体处理、远程等离子体处理、UV处理和在包含Ar、He、N2、NH3和H2中的至少一种气体内的热处理中的一种或者多种处理来执行。为了防止衬底的再次污染,使衬底在预处理之后并且在与硅烷基化剂接触之前不暴露于大气。
使用所述硅烷基化剂的处理优选地在介于约100和约300℃之间的温度下并且在约0.5至20托之间的压强下执行。诸如氩和/或氦之类的惰性气体能够与硅烷基化剂流一起供给。在一些实施方式中,所述惰性气体的流率比所述硅烷基化剂的流率大至少约10倍。合适的硅烷基化剂的实例包括三甲氧基硅烷、二乙氧基甲基硅烷、二甲基氨基三甲基硅烷、乙氧基三甲基硅烷、双-二甲基氨基二甲基硅烷、乙烯基三甲基硅烷、乙烯基三甲氧基硅烷、三甲基硅烷基乙炔、(3-巯基丙基)三甲氧基硅烷、苯基三甲氧基硅烷以及它们的组合。
在用硅烷基化剂处理结束并且硅烷基化剂的流动停止之后,加热衬底以从金属表面驱离已反应的硅烷基化剂。在一些实施方式中,所述加热是在介于约120和约450℃之间的温度下在气体内执行,所述气体选自由Ar、He、N2、NH3、H2和它们的混合物所构成的组。
在一些实施方式中,所述电介质层还能在用硅烷基化剂处理期间与硅烷基化剂反应。在一些实施方式中,所述电介质在与所述硅烷基化剂反应时针对覆盖层的沉积而变得钝化,由此增加了覆盖沉积处理的选择性。
在一些实施方式中,所提供的方法被集成到处理方案内,该处理方案包括光刻图案化并且还包括:施加光致抗蚀剂到所述衬底;将所述光致抗蚀剂暴露于光;将所述光致抗蚀剂图案化并且将图案转印到所述衬底;以及从所述衬底选择性地去除所述光致抗蚀剂。
在另一方面中,本发明还提供了一种用于在晶片衬底上形成半导体器件结构的装置。该装置包括:处理腔,其具有用于导入气相的或者挥发性的反应物的进口;晶片衬底支撑件,其用于在所述处理腔内处理所述晶片衬底的期间将所述晶片衬底保持在适当位置;以及控制器,其包含用于执行本发明所提供的方法的程序指令。例如所述控制器可以包含程序指令,所述程序指令用于:(i)使具有暴露电介质层和暴露金属层的所述晶片衬底在第一温度下与硅烷基化剂接触,以使所述硅烷基化剂与所述暴露金属层的表面上的含碳污染物反应,其中所述金属选自由铜、钴和镍所构成的组;(ii)在接触之后,在更高的温度下加热所述晶片衬底以从所述晶片衬底的所述金属表面去除所述已反应的硅烷基化剂;以及(iii)在从所述金属表面去除所述已反应的硅烷基化剂之后,选择性地沉积覆盖层在所述金属表面上,而不将相同覆盖层沉积在所述电介质层上。
在一些实施方式中,提供了一种***,其中该***包括本文所述的装置和步进曝光机(stepper)。
在另一方面,本发明提供了一种非暂时性计算机可读介质,其中所述介质包括用于沉积装置的程序指令,所述程序指令包含用于执行本文所述方法中的任意操作的代码。
附图说明
图1A-1D示出了根据本文所提供的一些实施方式的选择性覆盖处理期间所生成的器件结构的示意性横截面图。
图2呈现了根据本文所提供的一些实施方式的覆盖处理的处理流程图。
图3呈现了根据本文所提供的实施方式的适用于去除碳基污染物的处理腔的示意图。
图4A是示意了通过化学机械抛光(CMP)平坦化的电沉积铜层的铜表面上存在碳的X射线光电子能谱(XPS)图。
图4B是示意了通过物理气相沉积(PVD)所沉积的铜层的铜表面上存在碳的XPS图。
图5是示意了用硅烷基化剂处理之后的铜表面上的碳和硅的含量。
图6是示意了针对在不同条件下所处理的样品的衬底表面组成的图表。
图7A是示意了经过了不同条件下的处理之后的电介质和铜上的钴沉积物的柱状图。
图7B是示意了经过了不同条件下的处理之后的电介质和铜上的钴沉积物的柱状图。
具体实施方式
提供了用于从在半导体衬底上的金属表面去除含碳污染物的方法和装置。污染物是通过用硅烷化试剂处理金属表面来去除。所提供的方法可以用来清洁铜、钴和镍的表面并且能够用来准备这些表面以用于覆盖层的CVD和ALD沉积。
术语“半导体衬底”和“部分制成的半导体装置”可互换使用,并且包括包含位于衬底中任何位置的半导体材料的衬底。应理解,除了半导体材料,半导体衬底通常还包括金属层和介电材料层。合适的半导体衬底的一个例子是包含由镶嵌处理形成的一个或多个金属化层的硅晶片。本文所提供的方法可以在后端和前端处理都使用。
术语“铜”、“钴”和“镍”既包括纯金属也包括这些金属的合金,其中铜、钴、镍的浓度或者这些金属的组合的浓度为至少约70原子%。如本文所用的铜的实例包括95-99%的纯铜金属以及含有至少70原子%的铜的铜合金,如CuAl合金以及CuMn合金。为清楚起见,这些方法将随后使用铜作为例子进行说明。要理解,钴和镍(包括其合金)的清洁可类似进行。
术语“覆盖层”包括沉积到经清洁的金属层的上部上和/或沉积在该上部内的层。覆盖层的实施例包括在镶嵌处理中沉积到铜线上的钴或锰层。
术语“选择性沉积”(其中覆盖层沉积在金属表面上,而不是沉积在电介质表面上)指的是使金属上的覆盖层的厚度比电介质上的覆盖层的厚度大至少10倍这样的沉积。如本文使用的术语“去除”以及“清洁”既包括部分去除也包括完全去除。
从金属表面去除含碳污染物可以在各种暴露电介质的存在下执行。在一些实施方式中,衬底包含暴露的金属层和暴露的电介质层,其中该电介质是低k电介质(3.2>k>2.7)、超低k(ULK)电介质(2.7>k>2.2)或极低k(ELK)电介质(k<2.2),其中k是介电常数。在前端处理中使用的一些实施方式中,电介质是致密的硅氧化物。合适的电介质的实例包括氧化硅基电介质,诸如碳掺杂的硅氧化物材料、有机电介质、多孔电介质等。所述方法对于在ULK和ELK电介质存在下处理金属层是特别有利的,因为这些方法可以在一些实施方式中在不使用等离子体的温和的条件下执行,例如甚至不破坏机械特性最弱的ULK和ELK电介质。合适的电介质的实例包括聚合的CVD沉积膜,其具有带有CH3终止端的Si-O-Si交联(如)和其它的CVD沉积的电介质(如BlackDiamond)。也可使用由旋涂方法沉积的电介质。
在一些实施方式中,用硅烷基化剂处理金属层的同时使电介质改性并且针对覆盖材料的沉积使其有惰性,从而改善覆盖物沉积的选择性。例如,在一些实施方式中,硅烷基化剂可以将电介质层上的-OH基团硅烷基化,从而使该电介质针对覆盖前体是有惰性的。含有-OH基团的电介质,如Si-O-H基团可以与在覆盖化学物质中使用的有机金属化合物偶然地进行反应,导致Si-O-金属基团的形成,并且导致覆盖处理的更小选择性。在一些实施方式中,硅烷基化剂降低了电介质的表面上的游离Si-O-H基团的浓度,从而改善了覆盖沉积的选择性。
图1A-1D示出了根据本文提供的实施方式的处理过程中得到的部分制成的半导体器件结构。只有顶部金属化层被示出以保持清晰。该处理开始于图1A中所示意的结构(镶嵌结构),该结构包含具有嵌入式铜线105的电介质层101(例如,ULK电介质),其中铜线105通过薄层的扩散阻挡层103(例如,钽、氮化钽或钽/氮化钽双层)与电介质隔开。该结构的表面含有铜层,该铜层受到含碳污染物107污染,该含碳污染物107可包括含有碳-碳和碳-氧键的污染物。图1A中所提供的衬底是在通过化学机械研磨(CMP)工艺从衬底的场区域去除多余的铜和多余的扩散阻挡层材料之后获得的。然而应当指出,具有含碳物质的污染物不仅在CMP之后所分析的铜试样上被发现,甚至在衬底不经受CMP的情况下也可能存在。例如,碳污染物被发现在通过物理气相沉积(PVD)所沉积的铜层上,其中铜没有通过CMP进行平坦化。
接着,可选地预处理衬底,用于例如去除铜表面上的铜氧化物或者用于调节电介质101的表面,然后使用硅烷基化剂对衬底进行处理,从而使硅烷基化剂与含碳污染物反应。接着加热衬底以从铜表面去除已反应的硅烷基化剂,提供如图1B所示的具有清洁的铜表面的结构。
接着,覆盖层(诸如钴覆盖层109)被选择性地沉积在铜层105上而不被沉积到电介质101上。所述沉积可通过使衬底与有机钴前体和还原剂接触来进行。在一些实施方式中,介于约的覆盖材料(例如介于约的覆盖材料)沉积在铜线路上。在其他实施方式中,所沉积的钴被沉积在铜线的顶部内,并且在铜层上不设有任何额外的厚度。在一些实施方式中,钴既沉积在铜层上也沉积在铜层的内部。
接着,诸如掺杂或未掺杂的硅氧化物和/或掺杂或未掺杂的硅碳化物(例如,SiCN)之类的电介质扩散阻挡层或蚀刻停止层被沉积在衬底的整个表面上。所得到的结构1D示出了驻留在电介质层101的顶部和钴层109的顶部上的SiCN扩散阻挡层111。
去除含碳污染物的方法可以在各种处理方案中用作在利用对于污染物的存在敏感的方法(例如利用CVD和ALD)沉积材料之前的金属表面处理步骤。例如,在一些实施方式中,所述清洁方法可以在以下的处理方案中使用。首先提供一种含有第一金属化层和ILD的上覆层的半导体衬底。接着,蚀刻所述ILD以限定凹陷特征并且使第一金属化层的铜线的顶部暴露。接着,暴露的铜线被可选地预处理并且与硅烷基化剂接触以使硅烷基化剂与铜表面上的含碳污染物反应。接着加热衬底以从铜表面去除已反应的硅烷基化剂,然后覆盖物(例如,钴覆盖物)被选择性地沉积在清洁的铜层上。接着,在底部具有受覆盖的铜的凹陷特征可以例如通过电沉积被填充以金属。
图2提供了在利用硅烷基化剂处理清洁的铜层上选择性地沉积覆盖层的方法的过程流程图的一个实施例。在操作201,提供了具有暴露的铜层和暴露的电介质层的部分制成的半导体装置。该装置可类似于图1A中所示的结构。在另一个实施方式中,该装置可以是一种结构,该结构包括在ILD层中所制作的通孔底部处的暴露的铜。接着,在操作203中,可选地预处理衬底。预处理可以加热地执行(不使用等离子体),并且在一些实施方式中可以包括UV照射。在一些实施方式中,使用直接或远程等离子体进行预处理。在预处理中,衬底可以与例如H2或NH3等还原气体接触。在一些实施方式中,在预处理期间,衬底与例如N2、He或Ar等惰性气体接触。前处理通常在介于约100-400℃的温度以及在介于约0.5至10托的压强下执行。当在预处理期间使用等离子体时,可以使用介于约100至6000W之间的功率执行。在这些实施方式中,当使用UV照射时,具有在介于约180和250nm的波长下发射的有效功率的紫外光源是优选的。在一些实施方式中,特别是在那些使用还原气体的实施方式中,预处理用于从铜表面清除铜氧化物。在其他实施方式中,执行预处理以调节电介质的表面并使电介质相对于覆盖层的沉积具有更加惰性。例如,存在NH3的UV照射显示出抑制钴在电介质上的生长。
在预处理完成后,重要的是不暴露衬底到大气环境以避免金属表面的再污染。因此,如果没有空气隔断(airbreak),那么衬底在操作203中与硅烷基化剂接触以使硅烷基化剂与铜表面上的含碳污染物反应。处理是在没有等离子体的条件下并且优选地(但非必需地)在没有UV照射的条件下执行。处理优选在介于约100-300℃之间的温度下和在介于约0.5至20托之间的压强下执行。硅烷基化剂通常以气体形式与例如N2、氩、氦等惰性气体一起供给或者与这些气体中的任意气体的混合物一起供给。在一些实施方式中,惰性气体的流率是硅烷基化剂的流率的至少十倍。在一些实施方式中,衬底暴露于硅烷基化剂持续5-120秒。硅烷基化剂是一种有机硅化合物。不希望受特定操作机制的束缚,相信合适的有机硅化合物含有一个或多个离去基团(如烷氧基,二烷基氨基等),这些离去基团在反应时被取代。优选地,硅烷基化剂不含有卤素取代基,因为这些卤素取代基可能会在离去时导致金属腐蚀。硅烷基化剂可以含有例如氢基、烷基、烷氧基、乙烯基、氨基、巯基、苯基和乙炔这样的取代基。合适的硅烷基化剂包括三甲氧基硅烷,二乙氧基甲基硅烷,二甲基胺基三甲基硅烷,乙氧基三甲基硅烷,双-二甲基氨基二甲基硅烷,乙烯基三甲基硅烷,乙烯基三甲氧基硅烷,三甲基硅烷基乙炔,(3-巯基丙基)三甲氧基硅烷,苯基三甲氧基硅烷。在一些实施方式中,优选的有机硅化合物的化学式是R1R2 3Si,其中R1选自由仲氨基(例如,二甲基氨基)、乙烯基、乙酰基和烷氧基(例如,乙氧基)组成的组,并且其中R2是烷基,例如甲基。处理后,在操作207中加热衬底以从铜表面去除已反应的硅烷基化剂。无需在利用硅烷基化剂处理后将衬底保持在惰性气体环境下。因此,在操作205和207之间可能存在空气隔断。加热能够在有介于约120-450℃之间的温度下执行。在一些实施方式中,加热是在比用硅烷基化剂处理衬底的温度大至少50℃(优选大至少100℃)的温度下执行的。例如,衬底可以在约250℃的温度下用硅烷基化剂进行处理,而加热可以在约400℃下进行。加热可以在惰性气体环境中或在存在还原气体的条件下进行。例如,加热可以在存在N2、氩、氦、NH3和H2中的一种或多种的条件下在介于约0.5-20托之间的压强下进行。在一个示例性的处理中,加热是在400℃的温度下在存在氩气的条件下在约15托的压强下执行持续约5分钟。
接着,在从铜表面上去除了硅烷基化剂之后,在操作209,覆盖层被选择性地沉积在铜表面上。可以实现大于20例如大于40(其中,选择比率指沉积在铜上的覆盖材料厚度与沉积在电介质材料上的覆盖材料厚度的比率)的选择比率。各种瓶盖可以使用CVD和ALD方法沉积到铜层。在一些实施方式中,钴覆盖材料是通过使用有机钴化合物作为前体的CVD进行沉积的。合适的有机钴化合物包括羰基叔丁基乙炔钴、苯并钴、环戊二烯基二羰基钴(II)、钴脒、二氮杂二烯钴、含有配体的变体以及这些化合物的组合。
要注意的是,由于本文所提供的清洁步骤,因此不能选择性沉积在未清洁表面上的一些有机钴前体成为合适的并且选择性沉积的钴。这些前体包括但不限于含有配体的有机金属钴前体,所述配体如烯丙基、脒基、环戊二烯基、二氮杂二烯基和醇氧基。有机金属钴化合物通常在与诸如氩气之类的惰性气体的混合物中以汽化形式提供。衬底与有机金属化合物和还原剂接触。结果发现,应优选使用相对低的温度来抑制有机金属化合物和还原剂之间的气相反应,该气相反应可能导致沉积选择比率降低。例如,可以使用介于约60-200℃(例如介于70-100℃)之间的处理温度以有效地促进在铜表面上的钴的沉积,同时对于待抑制的气相反应又是足够低的。此外,发现,相对低的压强也有利于抑制钴化合物和还原剂之间的气相反应,同时允许表面驱动的在铜上的沉积。在一些实施方式中,钴沉积是在约0.2-200托之间的压强下执行的。例如,在一些实施方式中,沉积是在约1托的压强下进行的。合适的还原剂包括肼、水合肼、烷基肼、1,1-二烷基肼、1,2-二烷基肼、氨、硅烷、二硅烷、三硅烷、锗烷、乙硼烷、甲醛、硼烷胺、二烷基锌、烷基铝化合物、烷基镓化合物、烷基铟化合物以及它们的组合。而在一个优选实施方式中,钴沉积是在没有等离子体的条件下执行,在替代实施方式中,可以使用氢等离子体和/或氨等离子体。在其它实施方式中,锰覆盖材料经由CVD或ALD通过使衬底与有机锰前体接触而进行沉积。合适的前体包括但不限于含有配体的有机金属锰前体,所述配体如烯丙基、脒基、环戊二烯基、二氮杂二烯基和醇氧基。
在覆盖层已沉积之后,扩散阻挡层可选地沉积在衬底上以接触覆盖层和电介质两者。适合的扩散阻挡层包括掺杂和非掺杂的SiC和SiN。这些层可以通过PECVD来沉积。例如,SiCN可以经由在含有前体以及含氮气体(例如,NH3)的气体形成等离子体通过PECVD进行沉积,该前体含有硅和碳(例如,烷基硅烷)。由于铜线上存在覆盖层,因此显著改善了这种扩散阻挡层对于铜的粘附性。
装置
在一般情况下,清洁铜线上的碳基污染物并形成保护覆盖物可以在允许引入挥发性前体且被配置以提供对反应条件的控制的任何类型的装置中执行,所述反应条件如室温度、前体流率、暴露时间等等。为了防止无意中氧化和污染衬底,通常优选以不将衬底暴露于周围环境中的方式执行操作201-211。在一个实施方式中,操作201-211以不破坏真空的方式在一个模块中按序执行。在一些实施方式中,操作201-211在一个模块中执行,所述模块具有位于一个室内的多个站,或具有多个室。可从LamReach公司(Fremont,CA)得到的VECTORTM模块是合适装置的一个实例。在其他实施方式中,预清洁和利用硅烷基化剂进行处理可以在一个装置中执行,并且随后的操作可以在用硅烷基化剂处理之后通过空气隔断而在不同的装置中执行。
示例性装置将包括一个或多个室或“反应器”(有时包括多个站),其容纳一个或多个晶片并且适于晶片处理。每个室可以容纳一个或多个晶片用于处理。所述一个或多个室将晶片保持在限定的一个位置或多个位置(在所述位置有或没有动作,例如旋转、振动或其它搅动)。图3提供了描绘被配置用于根据本文所提供的实施方式实现铜表面的清洁的不同反应器组件的简化框图。如图所示,反应器300包括处理室301,该处理室301包围反应器的其它组件并且用来容纳通过喷头303输送的处理气体。在反应器内,晶片基座307支撑晶片衬底309并且还包括用于加热衬底的加热块305。基座通常包括卡盘、叉或升降销,以将衬底在沉积反应期间和在沉积反应之间保持和传送。卡盘可以是静电卡盘、机械卡盘或作为可用于工业和/或研究用途的各种其他类型的卡盘。
处理气体经由入口311引入并通过气体管道315输送。多个源气体管道317连接到歧管319。气体可以是或者可以不是预先混合的。使用适当的阀和质量流量控制机构来确保在预处理期间和在用硅烷基化剂处理的期间输送适当的气体。在硅烷基化剂以液体形式输送的情况下,采用液体流量控制机构。然后使液体在输送过程中,在被加热到其汽化点之上的歧管内汽化并且与处理气体混合,然后到达沉积室。
处理气体经由出口321排出室300。真空泵323(例如,一个或两个阶段的机械干式泵和/或涡轮分子泵)通常将处理气体吸出并通过诸如节流阀或摆动阀之类的闭环回路受控流量限制装置在反应器内部维持适当的低压。
控制器325与所述装置电连接,并且被配置以用于控制所述预处理和清洁处理。控制器可包括用于提供必需的温度、压强、前体流和所提供方法的其它处理参数的程序指令。
在采用UV照射执行预处理或硅烷基化剂处理的那些实施方式中,装置还包括UV灯(未示出),该UV灯被配置以用UV光照射衬底并且与控制器相连。在用等离子体进行预处理的那些实施方式中,该装置还可以包括与控制器相连的用于高频(HF)和/或低频(LF)等离子体的等离子体发生器。在一些实施方式中,装置被配置成在预处理期间使用远程等离子体,并包括与处理室流体连通的等离子体发生室,其中,所述装置被配置用于在预处理期间从等离子体发生室递送自由基到处理室。
本发明的另一个方面是被配置以实现本文描述的方法的***或模块。合适的***包括用于完成处理操作的硬件和具有用于控制根据本发明的处理操作的指令的***控制器。该***控制器通常会包括一个或多个存储设备和被配置以执行指令的一个或多个处理器,从而使装置将执行根据本发明的方法。包含用于控制根据本发明的处理操作的指令的机器可读介质可耦合到***控制器。例如,控制器可包括用于为衬底预处理、硅烷基化剂处理以及覆盖层沉积提供合适工艺条件的程序指令或内置逻辑。例如,控制器可包括用于在硅烷基化剂处理期间维持适当温度并且升高温度以去除硅烷基化剂的程序指令。控制器还可在预处理期间控制紫外灯,并且可包括用于衬底的紫外线照射的程序指令。在一般情况下,该控制器可以包括用于执行本文所提供的方法的任意步骤的指令。
本文上述的装置/处理可以与光刻图案化工具或处理结合使用,以例如制造或生产半导体器件、显示器、发光二极管、光伏电池板等。典型地但非必需地,这样的工具/处理将在常用制造设施内使用或一起执行。膜的光刻图案化通常包括以下步骤中的一部分或全部,每个步骤能以多个可能工具实现:(1)用旋涂或喷涂式工具在工件即衬底上施加光致抗蚀剂;(2)使用热板或加热炉或UV固化工具固化光致抗蚀剂;(3)使用诸如晶片步进曝光机之类的工具将光致抗蚀剂暴露于可见光或紫外线或X射线光;(4)使所述抗蚀剂显影,以便选择性地除去抗蚀剂并进而使用诸如湿式工作台之类的工具将其图案化;(5)通过使用干式或等离子体辅助式刻蚀工具将抗蚀剂图案转印到下伏膜或工件上;以及(6)使用例如RF或微波等离子体抗蚀剂剥离机等工具去除抗蚀剂。
实验实施例
实施例1:在通过不同的方法所沉积和处理的铜薄膜上得到X射线光电子能谱(XPS)数据。图4A示出了通过电镀沉积和用CMP平坦化的铜薄膜的XPS数据。在这个样品中观察到了分配到含碳污染物的两个峰值:约289eV的峰值被分配到碳-氧(碳酸酯)键,并且约285eV的峰值被分配到C-C或C-H键。图4B示出了通过PVD所沉积的铜薄膜(未进行后续的CMP处理)的XPS数据。在该样品中也观察到了分配到含碳污染物的两个峰值:约289eV的峰值被分配到碳-氧(羰基)键,并且约285eV的峰值被分配到C-C或C-H键。这两个图表均是指C1sXPS数据。这些数据说明,含碳污染物存在于由不同方法所沉积的铜层上,并且不限于由CMP中所使用的化学组合物而获得的污染物。
实施例2:碳和硅含量是在不同条件下用硅烷基化剂所处理的铜层的不同样品中通过XPS(分别使用C1s的积分面积和Si2p峰值)所测定的。图5中所示的曲线示出了硅含量(y轴)相对于总的碳含量(x轴)的依赖关系。得到了两列数据。以菱形示出的数据列是指经电沉积CMP处理的铜的样品。以方块示出的数据列是指经PVD沉积的铜的样品(没有通过CMP平坦化)。由此可以看出,在这两个数据列中,碳和硅含量是正相关关系,这示意了含碳污染物和硅烷基化剂之间的结合。
实施例3:在包含在用硅烷基化剂处理之前和之后的含铜层的样品上得到了碳(C1s)的XPS数据,其中所述处理包括加热以去除已反应的硅烷基化剂。在约285eV和289eV处的峰值强度大大降低。
实施例4:铜表面上的硅、铜、氧、碳和氮含量是在不同的条件下对层进行处理之后在经电沉积CMP处理的铜层上利用XPS测定的。结果示于图6中的表中。表的第一列列出了样品识别号。表的第二列表示特定样品是否进行了预处理。预处理是通过使衬底在15托的压强下在NH3气体中经受UV照射(在90%的紫外线灯强度下)持续30秒执行的。该表的第三列指的是暴露到硅烷基化剂(化学暴露)。将样品暴露于二甲基氨基三甲基硅烷硅烷基化剂持续60秒而不使用等离子体。第四列列出了处理温度(基座温度),在该处理温度下执行用硅烷基化剂的处理。样品A1-A4是在250℃下进行处理的,而样品B1-B4是在400℃进行处理的。第五列列出了在用硅烷基化剂进行处理期间在样品A1、A2、B1、B2、C1和C2上所执行的UV曝光。第六列列出了在样品A2,A4,B2,B4,C2和C4上执行的后处理,所述后处理是通过在压强为15托的氩气环境中在400℃下持续5分钟加热样品而执行的。其余列列出了硅、铜、氧、碳和氮的含量(原子%)。“控制”样品列出了在不存在任何处理的情况下铜表面上的这些元素的含量。可以看出,在样品A2、A4、B2和B4中铜表面上的碳含量降低(与控制相比),所述样品A2、A4、B2和B4是在250℃的温度下用硅烷基化剂进行处理,并且随后在更高的温度下加热以除去已反应的硅烷基化剂。在没有UV照射的情况下所处理的样品A4和B4相比于在存在UV辐射的情况下所处理的样品A2和B2在其表面上显示出较低硅含量。
实施例5:钴是通过MOCVD在铜层上和在ULK电介质(K=2.55)上沉积的。钴含量是在铜和ULK电介质表面上测定,并且沉积选择系数被设定为铜上的钴浓度与电介质上钴浓度的比率。图7A示出了示意针对不同沉积条件在铜样品和ULK电介质样品上的钴含量的柱状图。
对于所有样品,在不存在等离子体的条件下通过将衬底暴露到含氢气的处理气体中的羰基钴前体而沉积钴。样品1和2示出了在没有用硅烷基化剂处理过的衬底上的铜和电介质上的(相应)钴浓度。得到为32的选择系数。样品3和4示出了衬底上的铜和电介质上的(相应)钴浓度,所述衬底在250℃用硅烷基化剂处理,并且然后在400℃下加热以去除已反应的硅烷基化剂。可以看出,选择系数提高到43。样品5和6示出了衬底上的铜和电介质上的(相应)钴浓度,所述衬底在250℃下用硅烷基化剂处理而没有经历随后的加热和除去已反应的硅烷基化剂。可以看出,在这种情况下铜上的钴生长受到抑制。样品7和8示出了衬底上的铜和电介质上的(相应)钴浓度,所述衬底在250℃下用NH3预处理且同时用紫外线照射,然后用硅烷基化剂在250℃下进行处理,并随后进行加热以去除已反应的硅烷基化剂。可以看出,在这种情况下选择系数大大提高,并且在电介质上没有检测到钴的沉积。样品9和10示出了衬底上的铜和电介质上的(相应)钴浓度,所述衬底在250℃下用NH3进行预处理并且同时用紫外线照射,然后在250℃下用硅烷基化剂处理并且没有用于去除已反应的硅烷基化剂的后续加热。可以看出,在这种情况下铜上的钴的增长受到抑制,导致较差沉积选择性。
实施例6:通过MOCVD在不同类型的铜层上和在不同的ULK电介质上沉积钴。钴含量通过XRF测定,并示于图7B中所显示的柱状图中。具体地说,样品11、15、19和23示出了在ULK(k=2.4)上的沉积;样品12、16、20和24示出了在ULK(k=2.55)上的沉积,样品13、17、21和25示出了在经PVD沉积的铜上的沉积,并且样品14、18、22和26示出了在通过CMP平坦化的电沉积铜上的沉积。用与实施例5相同的方法沉积钴。将所有样品用硅烷基化剂处理,并且随后将这些样品在氩气环境下在400℃进行加热,以去除已反应的硅烷基化剂。样品11、12、13、14在没有UV照射的情况下并且未经任何预处理的条件下用硅烷基化剂在250℃下进行处理。样品15、16、17和18是在250℃下用氨进行预处理,同时进行紫外线照射,并然后在250℃下用硅烷基化剂进行处理。样品19、20、21和22是在不存在UV照射并且没有任何预处理的情况下在400℃下用硅烷基化剂进行处理的。样品23、24、25和26是在250℃下用氨进行预处理,同时用UV照射,并随后在400℃下用硅烷基化剂进行处理。可看到,相比于较高的温度(400℃),在用硅烷基化剂进行处理期间优选较低的温度(250℃),并且在所有的实验样品中使用氨的UV预处理减少了电介质上的钴生长。
Claims (20)
1.一种用于形成半导体器件结构的方法,该方法包括:
(a)提供包含暴露金属层和暴露电介质层的半导体衬底,其中所述金属选自由铜、钴和镍所构成的组;
(b)使所提供的所述半导体衬底与硅烷基化剂在第一温度下接触,以使所述硅烷基化剂与所述暴露金属层的表面上的含碳污染物反应;以及
(c)在接触之后,在更高温度下加热所述半导体衬底以从所述半导体衬底的金属表面去除已反应的硅烷基化剂;以及
(d)在从所述金属表面去除所述已反应的硅烷基化剂之后,选择性地沉积覆盖层在所述金属表面上,而不将相同覆盖层沉积在所述电介质层上。
2.根据权利要求1所述的方法,其中所述暴露金属层是暴露铜层。
3.根据权利要求1所述的方法,其中所述覆盖层是含金属覆盖层。
4.根据权利要求1所述的方法,其中所述覆盖层是包含钴和/或锰的含金属覆盖层。
5.根据权利要求1所述的方法,其中(d)包括使所述衬底与有机金属化合物接触。
6.根据权利要求1所述的方法,其中(d)包括使所述衬底与包含钴和配体的有机钴化合物接触,所述配体选自由烯丙基、脒基、二氮杂二烯基和环戊二烯基所构成的组。
7.根据权利要求1所述的方法,其还包括在使所述衬底与所述硅烷基化剂接触之前预处理所述衬底,其中所述预处理选自由直接等离子体处理、远程等离子体处理、UV处理和气体内的热处理构成的组,所述气体包含Ar、He、N2、NH3和H2中的至少一种。
8.根据权利要求7所述的方法,其中在介于预处理和与所述硅烷基化剂接触之间使所述衬底不暴露于大气。
9.根据权利要求1所述的方法,其中所述硅烷基化剂选自由三甲氧基硅烷、二乙氧基甲基硅烷、二甲基氨基三甲基硅烷、乙氧基三甲基硅烷、双-二甲基氨基二甲基硅烷、乙烯基三甲基硅烷、乙烯基三甲氧基硅烷、三甲基硅烷基乙炔、(3-巯基丙基)三甲氧基硅烷、苯基三甲氧基硅烷以及它们的组合所构成的组。
10.根据权利要求1所述的方法,其中所述第一温度介于约100和约300℃之间。
11.根据权利要求1所述的方法,其中所述硅烷基化剂是与惰性气体一起供给,并且其中所述惰性气体的流率比所述硅烷基化剂的流率大至少约10倍。
12.根据权利要求1所述的方法,其中(b)是在介于约0.5至20托之间的压强下执行。
13.根据权利要求1所述的方法,其中(c)是在介于约120和约450℃之间的温度下在气体内执行,所述气体选自由Ar、He、N2、NH3、H2和它们的混合物所构成的组。
14.根据权利要求1所述的方法,其中所述硅烷基化剂还与暴露的电介质反应并且针对所述覆盖层的沉积使所述电介质钝化。
15.根据权利要求1所述的方法,其中所述电介质具有小于约3的电介质常数。
16.根据权利要求1所述的方法,其还包括:
(e)在所述覆盖金属上和所述暴露电介质上沉积电介质层。
17.根据权利要求16所述的方法,其中所述电介质层包括掺杂的或者非掺杂的碳化硅。
18.根据权利要求1所述的方法,其还包括:
施加光致抗蚀剂到所述衬底;
将所述光致抗蚀剂暴露于光;
将所述光致抗蚀剂图案化并且将图案转印到所述衬底;
以及从所述衬底选择性地去除所述光致抗蚀剂。
19.一种用于在晶片衬底上形成半导体器件结构的装置,该装置包括:
(a)处理腔,其具有用于导入气相的或者挥发性的反应物的进口;
(b)晶片衬底支撑件,其用于在所述处理腔内处理所述晶片衬底的期间将所述晶片衬底保持在适当位置;以及
(c)控制器,其包含程序指令,所述程序指令用于:
(i)使具有暴露电介质层和暴露金属层的所述晶片衬底在第一温度下与硅烷基化剂接触,以使所述硅烷基化剂与所述暴露金属层的表面上的含碳污染物反应,其中所述金属选自由铜、钴和镍所构成的组;以及
(ii)在接触之后,在更高的温度下加热所述晶片衬底以从所述晶片衬底的所述金属表面去除所述已反应的硅烷基化剂;以及
(iii)在从所述金属表面去除所述已反应的硅烷基化剂之后,选择性地沉积覆盖层在所述金属表面上,而不将相同覆盖层沉积在所述电介质层上。
20.一种***,其包括步进曝光机和根据权利要求19所述的装置。
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KR20160000863A (ko) | 2016-01-05 |
US20150380296A1 (en) | 2015-12-31 |
TW201612351A (en) | 2016-04-01 |
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