CN102931081B - Manufacturing method for semiconductor device with field barrier layer - Google Patents
Manufacturing method for semiconductor device with field barrier layer Download PDFInfo
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- CN102931081B CN102931081B CN201110230806.6A CN201110230806A CN102931081B CN 102931081 B CN102931081 B CN 102931081B CN 201110230806 A CN201110230806 A CN 201110230806A CN 102931081 B CN102931081 B CN 102931081B
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Abstract
The invention discloses a manufacturing method for a semiconductor device with a field barrier layer. The manufacturing method comprises the following steps of etching a slot or a hole with required depth on the back of a silicon chip; growing highly doped polysilicon in the slot or the hole; diffusing at high temperature for a long time in the slot or the hole; performing the conventional positive process on the semiconductor device; and reducing the thickness of the back of the silicon chip, and leaving the required field barrier layer. According to the manufacturing method for the semiconductor device with the field barrier layer, the step of manufacturing the field barrier layer required to be subjected to high-temperature diffusion is adjusted to the front stage of a processing process of the device, a high-temperature diffusion process is not required in the silicon chip positive process, new field barrier layer structures which can confirm to different demands are easy to obtain, the problem of the limitation of the capability of a machine for processing slices is solved, the machine can finish the positive process under the condition of keeping the thickness of the silicon chip, the field barrier layer can be manufactured at deep places away from the upper surfaces of the large-size wafers, and the cost is lower.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacture method of the semiconductor device with a barrier layer.
Background technology
IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor), FRD (Fast Recovery Diode, fast recovery diode) etc. are the semiconductor device on band barrier layer, field.
IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) be a kind of powerful power electronic device, particularly be greater than the IGBT of more than 1200 volts, needing to increase back surface field barrier layer improves withstand voltage, reduce the emission effciency in hole, reduce the risk of fastening lock effect.In present industry, mainly the wafer of 4 cun or 6 cun is making IGBT, because substrate thickness own is just very thin, does not have large process risk.And for 8 cun of wafers due to process equipment allow into substrate thickness thicker, and the barrier layer, field at the characteristic requirements back side of IGBT with barrier layer, field is dark to 500 microns in distance wafer surface 200 microns.
The manufacture method of the IGBT on barrier layer, existing band field is, after wafer finishes front technique, according to the requirement of the characteristic such as withstand voltage, wafer is ground to required thickness, then the ion (as phosphorus or arsenic etc.) of N-type impurity is injected at the back side, because now device front has the metal materials such as AL, the temperature adopted when adopting common annealing technology generally can not higher than 500 degrees Celsius, the efficiency that the barrier layer ion injected is activated is not high, so need afterwards to be activated by high annealing, adopt laser annealing greatly to raise the efficiency, but cost is very high;
Application number is the Chinese patent application of 201010164106.7, provide a kind of manufacture method with the IGBT of field stop structure, as Fig. 1, shown in Fig. 2, after front technique finished by substrate, carry out substrate back more thinning, then carry out at substrate back ion implantation or method of diffusion, the impurity identical with silicon chip conduction type is imported in substrate, form N+ field cutoff layer (Fig. 1) or P+ field cutoff layer (Fig. 2), then at silicon chip back surface layer, the impurity contrary with silicon chip conduction type is imported in substrate, form P+ collector region (Fig. 1) or N+ collector region (Fig. 2), finally carry out annealing or advancing high-temperature heat treatment.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method of the semiconductor device with a barrier layer, solve the restriction of board process thin slice ability, make board can finish front technique when keeping the thickness of silicon chip, barrier layer, field can be accomplished that cost is low from large-sized wafer upper surface comparatively depths.
For solving the problems of the technologies described above, the manufacture method of the semiconductor device on barrier layer, band field of the present invention, comprises the following steps:
One. groove or the hole of desired depth is etched at silicon chip back side;
Two. highly doped polysilicon of growing up from the groove or hole of described silicon chip back side;
Three. from the groove or hole of described silicon chip back side, carry out high temperature push away trap for a long time, form back surface field barrier layer;
Four. silicon chip is inverted, carry out the conventional face technique of semiconductor device;
Five. after front side of silicon wafer technique is finished, silicon chip back side is thinning, leave required barrier layer, field, then carry out polishing;
Six. on barrier layer, silicon chip back side field, do silicon chip back side collector electrode carrier injection and annealing;
Seven. make the smithcraft of silicon chip back side, form collector contact metal.
Described silicon wafer thickness can be more than or equal to 500 microns.
The degree of depth in described groove or hole can be more than or equal to 20 microns.
The highly doped polysilicon concentration of growing up in the groove of described silicon chip back side or hole can be greater than a 19 powers charge carrier of every cubic centimetre 10.
In step one, can to grow up silicon oxide film at silicon chip back side, then front side of silicon wafer be protected, carry out the exposure of back surface field barrier layer figure, then silicon chip back side is carried out the etching of silicon oxide film, etch into silicon face; Then utilize silicon oxide film as barrier layer, silicon is etched, etch groove or the hole of desired thickness at silicon chip back side, remove described silicon oxide film.
Can be that, in step 2, the highly doped polysilicon of growing up in the groove of described silicon chip back side or hole is N-type, in step 6, barrier layer, silicon chip back side field is done silicon chip back side P type collector electrode carrier injection.
Can be that, in step 2, the highly doped polysilicon of growing up in the groove of described silicon chip back side or hole is P type, in step 6, barrier layer, silicon chip back side field is done silicon chip back side N-type collector electrode carrier injection.
In step 3, temperature can be carried out higher than 950 degrees Celsius, the time be longer than 1 hour push away trap, formed back surface field barrier layer.
In step 3, temperature can be carried out higher than 1100 degrees Celsius, the time be longer than 5 hours push away trap, formed back surface field barrier layer.
In step 4, silicon chip is inverted, the conventional face technique of vertical double diffused metal-oxide semiconductor field effect transistor can be carried out.
The semiconductor device on barrier layer, described band field can be insulated gate bipolar transistor.
The semiconductor device on barrier layer, described band field can be fast recovery diode.
The manufacture method of the semiconductor device on barrier layer, band field of the present invention, by barrier layer, the field manufacturing step needing high temperature to push away trap being advanceed to the processing technology leading portion of device, after front side of silicon wafer technique, no longer need high temperature to push away trap technique, the formation of the smithcrafts such as front side aluminum can not be affected, be exaggerated flexibility and the adjustability of this barrier layer formation process, be easy to obtain the new field barrier layer structure that can meet different demand, owing to not adopting the contour cost technology of laser annealing, technique can be achieved with good cost performance, also solve the restriction of board process thin slice ability simultaneously, after having carried out back surface field barrier layer, front technique can be finished when keeping the thickness of silicon chip, eliminate the cost of board transformation, can barrier layer, field be accomplished from 8 cun of upper wafer surface 200 microns dark again simultaneously.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is existing a kind of manufacture method flow chart with the IGBT of field stop structure;
Fig. 2 is the manufacture method flow chart that existing another kind has the IGBT of field stop structure;
Fig. 3 is in manufacture method one embodiment of the semiconductor device on barrier layer, band field of the present invention, etches groove or hole schematic diagram at silicon chip back side;
Fig. 4 is in manufacture method one embodiment of the semiconductor device on barrier layer, band field of the present invention, highly doped polysilicon schematic diagram of growing up in the groove of silicon chip back side or hole;
Fig. 5 is in manufacture method one embodiment of the semiconductor device on barrier layer, band field of the present invention, carries out high temperature and push away the schematic diagram after trap for a long time from the groove or hole of silicon chip back side;
Fig. 6 is in manufacture method one embodiment of the semiconductor device on barrier layer, band field of the present invention, carries out the schematic diagram after conventional face technique;
Fig. 7 is in manufacture method one embodiment of the semiconductor device on barrier layer, band field of the present invention, and barrier layer, silicon chip back side field is done the schematic diagram after silicon chip back side P type collector electrode carrier injection and annealing;
Fig. 8 is in manufacture method one embodiment of the semiconductor device on barrier layer, band field of the present invention, makes the smithcraft of silicon chip back side, forms the schematic diagram after collector contact metal.
Embodiment
Manufacture method one execution mode of the semiconductor device on barrier layer, band field of the present invention, comprises the following steps:
One. at silicon chip back side growth silicon oxide film, preferably, silicon wafer thickness is more than or equal to 500 microns, and silicon oxide film thickness is 5000-20000 dust, is then protected by front side of silicon wafer, carries out the exposure of barrier layer, silicon chip back side field figure;
Two. silicon chip back side is carried out the etching of silicon oxide film, etch into silicon face;
Three. photoresist is removed, utilizes silicon oxide film as barrier layer, etch silicon, etch groove or the hole of desired depth, remove described silicon oxide film at silicon chip back side, preferably, the degree of depth in described groove or hole is more than or equal to 20 microns;
Four. the polysilicon (N-type or P type) of growing up highly doped from the groove or hole of silicon chip back side, preferably, the 19 powers charge carrier that described polycrystal concentration is greater than every cubic centimetre 10;
Five. from the groove or hole of silicon chip back side, carry out high temperature push away trap for a long time, formed back surface field barrier layer, preferably, carry out temperature higher than 950 degree, the time be longer than 1 hour push away trap;
Six. silicon chip is inverted, carry out the conventional face technique known.
Seven. after front side of silicon wafer technique is finished, silicon chip back side is thinning, leave required barrier layer, field, then carry out polishing;
Eight. on barrier layer, silicon chip back side field, make silicon chip back side collector electrode charge carrier (P type or N-type, contrary with highly doped polysilicon of growing up in groove or hole) inject and anneal;
Nine. make the smithcraft of silicon chip back side, form collector contact metal, draw collector electrode.
The manufacture method of the semiconductor device on barrier layer, band field of the present invention, be applicable to utilize PIN thin layer to bear the semiconductor device of reverse voltage, the semiconductor device on barrier layer, described band field can be IGBT (insulated gate bipolar transistor), FRD (fast recovery diode) etc.
One embodiment, manufactures the IGBT device on the barrier layer, band field of withstand voltage 1700V, as shown in Fig. 3 to Fig. 8, comprises the following steps:
One. be the silicon oxide film of 8 cun of silicon chip 1 back side growth 5000-20000 dusts of 725 microns at thickness, then by good for silicon chip 1 front protecting, carry out the exposure of silicon chip 1 back surface field barrier layer figure; Silicon chip 1 back surface field barrier layer graphics critical dimension can be greater than 0.5 micron;
Two. silicon chip 1 back side is carried out the etching of silicon oxide film, etch into silicon face
Three. photoresist is removed, utilizes silicon oxide film as barrier layer, silicon is etched, go out at silicon chip 1 back-etching groove or the hole 11 that the degree of depth is 20 microns, remove described silicon oxide film, as shown in Figure 3;
Four. the N-type polycrystalline silicon 12 of 11 growth highly doped (e.g., the 19 powers charge carrier that bulk concentration is greater than every cubic centimetre 10) from the groove or hole at silicon chip 1 back side, as shown in Figure 4;
Five. from the groove or hole of silicon chip back side, carry out temperature higher than 1100 degrees Celsius, the high temperature that the time is longer than 5 hours pushes away trap for a long time, makes the degree of depth of trap be greater than 30 microns, forms back surface field barrier layer 13, as shown in Figure 5;
Six. silicon chip is inverted, utilization is similar to the conventional face technological process known of VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor), completes the front technique that device is formed, comprising: grid oxygen and polysilicon electrode are formed, P trap, N+ source is formed; The inter-level dielectric film of coated described polysilicon electrode, contact hole is formed, P+ contacts implanted layer and is formed, source metal electrode is formed and polycrystalline electrodes is formed, as shown in Figure 6, injection 4, P type tagma 5, groove 7, N-type withstand voltage zone 8 is just being drawn at cut-off ring injection region 1, front side of silicon wafer formation field, P type guard ring injection region 2, source 3, P;
Seven. after front side of silicon wafer technique is finished, silicon chip back side is thinning, leave required barrier layer, field 13, then carry out polishing.
Eight. on barrier layer, silicon chip back side field, do silicon chip back side P type collector electrode carrier injection and annealing, form P type collector layer 9, as shown in Figure 7;
Nine. silicon chip back side carries out evaporation or the physical sputtering of metal, makes the smithcraft of silicon chip back side, forms collector contact metal 10, draws collector electrode, as shown in Figure 8.
The manufacture method of the semiconductor device on barrier layer, band field of the present invention, by barrier layer, the field manufacturing step needing high temperature to push away trap being advanceed to the processing technology leading portion of device, after front side of silicon wafer technique, no longer need high temperature to push away trap technique, the formation of the smithcrafts such as front side aluminum can not be affected, be exaggerated flexibility and the adjustability of this barrier layer formation process, be easy to obtain the new field barrier layer structure that can meet different demand, owing to not adopting the contour cost technology of laser annealing, technique can be achieved with good cost performance, also solve the restriction of board process thin slice ability simultaneously, after having carried out back surface field barrier layer, front technique can be finished when keeping the thickness of silicon chip, eliminate the cost of board transformation, can barrier layer, field be accomplished from 8 cun of upper wafer surface 200 microns dark again simultaneously.
Claims (11)
1. a manufacture method for the semiconductor device with a barrier layer, is characterized in that, comprises the following steps:
One. groove or the hole of desired depth is etched at silicon chip back side;
Two. doping content of growing up from the groove or hole of described silicon chip back side is greater than the polysilicon of a 19 powers charge carrier of every cubic centimetre 10;
Three. from the groove or hole of described silicon chip back side, carry out temperature higher than 950 degrees Celsius, the time be longer than 1 hour push away trap, formed back surface field barrier layer;
Four. silicon chip is inverted, carry out the conventional face technique of semiconductor device.
2. the manufacture method of the semiconductor device on barrier layer, band field according to claim 1, is characterized in that, further comprising the steps of after described step 4:
Five. after front side of silicon wafer technique is finished, silicon chip back side is thinning, leave required barrier layer, field, then carry out polishing;
Six. on barrier layer, silicon chip back side field, do silicon chip back side collector electrode carrier injection and annealing;
Seven. make the smithcraft of silicon chip back side, form collector contact metal.
3. the manufacture method of the semiconductor device on barrier layer, band field according to claim 1, is characterized in that,
Described silicon wafer thickness is more than or equal to 500 microns.
4. the manufacture method of the semiconductor device on barrier layer, band field according to claim 2, is characterized in that, the degree of depth in described groove or hole is more than or equal to 20 microns.
5. the manufacture method of the semiconductor device on barrier layer, band field according to claim 2, it is characterized in that, in step, at silicon chip back side growth silicon oxide film, then front side of silicon wafer is protected, carry out the exposure of back surface field barrier layer figure, then silicon chip back side is carried out the etching of silicon oxide film, etch into silicon face; Then utilize silicon oxide film as barrier layer, silicon is etched, etch groove or the hole of desired thickness at silicon chip back side, remove described silicon oxide film.
6. the manufacture method of the semiconductor device on barrier layer, band field according to claim 2, it is characterized in that, in step 2, the highly doped polysilicon of growing up in the groove of described silicon chip back side or hole is N-type, in step 6, barrier layer, silicon chip back side field is done silicon chip back side P type collector electrode carrier injection.
7. the manufacture method of the semiconductor device on barrier layer, band field according to claim 2, it is characterized in that, in step 2, the highly doped polysilicon of growing up in the groove of described silicon chip back side or hole is P type, in step 6, barrier layer, silicon chip back side field is done silicon chip back side N-type collector electrode carrier injection.
8. the manufacture method of the semiconductor device on barrier layer, band field according to claim 2, is characterized in that, in step 3, carries out temperature higher than 1100 degrees Celsius, the time be longer than 5 hours push away trap, formed back surface field barrier layer.
9. the manufacture method of the semiconductor device on barrier layer, band field according to claim 2, is characterized in that, in step 4, silicon chip is inverted, carries out the conventional face technique of vertical double diffused metal-oxide semiconductor field effect transistor.
10. the manufacture method of the semiconductor device on barrier layer, band field according to claim 2, is characterized in that, the semiconductor device on barrier layer, described band field is insulated gate bipolar transistor.
The manufacture method of the semiconductor device of 11. barrier layer, band fields according to claim 2, is characterized in that, the semiconductor device on barrier layer, described band field is fast recovery diode.
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| CN104637813B (en) * | 2013-11-13 | 2019-10-01 | 江苏物联网研究发展中心 | The production method of IGBT |
| CN109994544B (en) * | 2018-01-03 | 2022-05-27 | 宁波达新半导体有限公司 | Method for manufacturing field stop type power device |
| CN109659236B (en) * | 2018-12-17 | 2022-08-09 | 吉林华微电子股份有限公司 | Process method for reducing VDMOS recovery time and VDMOS semiconductor device thereof |
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| US3961353A (en) * | 1974-10-21 | 1976-06-01 | International Business Machines Corporation | High power semiconductor device |
| CN101826552A (en) * | 2010-05-06 | 2010-09-08 | 天津环鑫科技发展有限公司 | Non-punch-through deep trench IGBT with field stop structure and manufacturing method thereof |
| CN102110605A (en) * | 2009-12-24 | 2011-06-29 | 北大方正集团有限公司 | Method and device for manufacturing insulated gate bipolar transistor (IGBT) chip |
| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
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| US7132321B2 (en) * | 2002-10-24 | 2006-11-07 | The United States Of America As Represented By The Secretary Of The Navy | Vertical conducting power semiconductor devices implemented by deep etch |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3961353A (en) * | 1974-10-21 | 1976-06-01 | International Business Machines Corporation | High power semiconductor device |
| CN102110605A (en) * | 2009-12-24 | 2011-06-29 | 北大方正集团有限公司 | Method and device for manufacturing insulated gate bipolar transistor (IGBT) chip |
| CN101826552A (en) * | 2010-05-06 | 2010-09-08 | 天津环鑫科技发展有限公司 | Non-punch-through deep trench IGBT with field stop structure and manufacturing method thereof |
| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
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