CN105097828A - Tft基板结构的制作方法及tft基板结构 - Google Patents

Tft基板结构的制作方法及tft基板结构 Download PDF

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CN105097828A
CN105097828A CN201510312477.8A CN201510312477A CN105097828A CN 105097828 A CN105097828 A CN 105097828A CN 201510312477 A CN201510312477 A CN 201510312477A CN 105097828 A CN105097828 A CN 105097828A
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substrate structure
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tft substrate
grid
metal segments
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CN105097828B (zh
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郭文帅
明星
申智渊
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种TFT基板结构的制作方法及TFT基板结构。本发明的TFT基板结构的制作方法,在制作栅极的同时,在栅极两侧形成间隔分布的数个金属段,并以栅极和数个金属段作为光罩,对多晶硅层进行离子注入,在多晶硅层上形成n型重掺杂区的同时,在n型重掺杂区之间形成未掺杂区,增加了阻值,分散了电极附近的强电场,避免了因局部强电场的存在而发生的热载流子效应对器件特性的影响,提高了工作电流,简化了制程,降低了生产成本,减小了TFT基板的尺寸。本发明的TFT基板结构,多晶硅层的n型重掺杂区之间形成有未掺杂区,避免了局部强电场的产生,消除了热载流子效应对器件特性的影响,具有较高的工作电流,结构简单,生产成本低。

Description

TFT基板结构的制作方法及TFT基板结构
技术领域
本发明涉及显示技术领域,尤其涉及一种TFT基板结构的制作方法及TFT基板结构。
背景技术
液晶显示装置(LiquidCrystalDisplay,LCD)具有机身薄、省电、无辐射等众多优点,得到了广泛的应用,如:移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
通常液晶显示装置包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlightmodule)。其中,液晶面板的结构主要是由一薄膜晶体管阵列基板(ThinFilmTransistorArraySubstrate,TFTArraySubstrate)、一彩色滤光片基板(ColorFilter,CF)、以及配置于两基板间的液晶层(LiquidCrystalLayer)所构成,其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转,将背光模组的光线折射出来产生画面。
随着移动显示技术在生活中的应用起到的作用越来越大,移动显示技术向更高画质、更高精细程度、更轻薄和更低功耗的方向发展,在器件上就要求尺寸越来越小,器件内部局部区域的电场强度也因此而增强,特别是在漏极附近存在强电场。载流子在强电场的作用下获得较高的能量成为热载流子。热载流子对器件性能的影响主要表现在以下两个方面:
(1)热载流子越过绝缘层注入到氧化层,不断积累,改变阈值电压,影响器件寿命;
(2)在漏极附近的耗尽区与晶格碰撞产生新的电子空穴对,以金属氧化物半导体(MetalOxidSemiconductor,MOS)场效应晶体管为例,碰撞产生的电子形成附加的漏电流,空穴则被衬底收集,形成衬底电流,使总电流成为饱和漏电流与衬底电流之和。热载流子效应是限制器件最高工作电压的基本因素之一。
为了解决热载流子的出现对器件特性的影响,技术人员想出了各种办法来避免局部强电场的产生。请参阅图1,为一种现有的TFT基板结构的示意图,所述TFT基板结构包括基板100、设于基板100上的半导体层200、设于所述半导体层200上的源/漏极300、设于所述源/漏极300及半导体层200上的绝缘层400、及设于所述绝缘层400上的栅极500,具体的,所述半导体层200包括对应于所述栅极500下方的沟道区210、位于所述沟道区210两侧且与所述源/漏极300相接触的两N型重掺杂区220、及位于两N型重掺杂区220与沟道区210之间的两偏移区230,由于偏移区230没有掺杂,阻值较高,可以分散电极附近的强电场,从而减少热载流子的产生,但是,该种TFT基板结构的漏电流虽然变小了,其工作电流也相应减小,导致功耗增大。
发明内容
本发明的目的在于提供一种TFT基板结构的制作方法,可以在多晶硅层形成n型重掺杂区的同时,在n型重掺杂区之间形成未掺杂区,以增加阻值,分散电极附近的强电场,避免因局部强电场的存在而发生的热载流子效应对器件特性造成影响,提高工作电流。
本发明的目的还在于提供一种TFT基板结构,多晶硅层的n型重掺杂区之间形成有未掺杂区,可避免局部强电场的产生,消除热载流子效应对器件特性的影响,提高工作电流。
为实现上述目的,本发明提供一种TFT基板结构的制作方法,包括如下步骤:
步骤1、提供基板,在所述基板上沉积缓冲层;
步骤2、在所述缓冲层上沉积多晶硅层;
步骤3、在所述多晶硅层上沉积栅极绝缘层,在所述栅极绝缘层上沉积金属层;
步骤4、在所述金属层上涂布光阻层,通过一道光罩对所述光阻层进行曝光、显影,得到位于中间的第一光阻段、及间隔分布于所述第一光阻段两侧的数个第二光阻段;
步骤5、以所述第一光阻段、及数个第二光阻段为阻挡层,对所述金属层进行蚀刻,对应所述第一光阻段下方得到栅极,分别对应所述数个第二光阻段下方得到数个金属段;
步骤6、剥离所述第一光阻段、及数个第二光阻段,以所述栅极、及数个金属段为光罩,对所述多晶硅层进行离子注入,在所述多晶硅层上对应所述栅极下方形成未掺杂的沟道区,对应所述沟道区的两侧形成数个n型重掺杂区,对应所述数个金属段下方形成位于所述数个n型重掺杂区之间的数个未掺杂区。
所述步骤4采用单缝光罩、半色调光罩、或灰阶光罩得到所述第一光阻段、及数个第二光阻段。
靠近所述第一光阻段两侧的两个第二光阻段与所述第一光阻段之间的距离均小于1μm,所述第二光阻段的宽度为1μm~2μm。
所述步骤5采用干法蚀刻或湿法蚀刻得到所述栅极、及数个金属段。
靠近所述栅极两侧的两个金属段与所述栅极之间的距离均小于1μm,所述金属段的宽度为1μm~2μm。
所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合。
所述金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种TFT基板结构,包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、及设于所述栅极绝缘层上间隔分布于所述栅极两侧的数个金属段;
所述多晶硅层包括对应于所述栅极下方的沟道区,位于所述沟道区两侧的数个n型重掺杂区,以及对应于所述数个金属段下方且位于所述数个n型重掺杂区之间的数个未掺杂区。
靠近所述栅极两侧的两个金属段与所述栅极之间的距离均小于1μm,所述金属段的宽度为1μm~2μm。
所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合;所述栅极、及数个金属段的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果:本发明的TFT基板结构的制作方法,在制作栅极的同时,在栅极两侧形成间隔分布的数个金属段,并以栅极和数个金属段作为光罩,对多晶硅层进行离子注入,在多晶硅层上形成n型重掺杂区的同时,在n型重掺杂区之间形成未掺杂区,增加了阻值,分散了电极附近的强电场,避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响,提高了工作电流,简化了制程,降低了生产成本,减小了TFT基板的尺寸。本发明的TFT基板结构,多晶硅层的n型重掺杂区之间形成有未掺杂区,避免了局部强电场的产生,消除了热载流子效应对器件特性的影响,具有较高的工作电流,结构简单,生产成本低。
附图说明
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图中,
图1为一种现有的TFT基板结构的示意图;
图2为本发明的TFT基板结构的制作方法的流程图;
图3为本发明的TFT基板结构的制作方法的步骤1的示意图;
图4为本发明的TFT基板结构的制作方法的步骤2的示意图;
图5为本发明的TFT基板结构的制作方法的步骤3的示意图;
图6-7为本发明的TFT基板结构的制作方法的步骤4的示意图;
图8为本发明的TFT基板结构的制作方法的步骤5的示意图;
图9-10为本发明的TFT基板结构的制作方法的步骤6的示意图;
图11为本发明的TFT基板结构的制作方法另一种实施方式的示意图;
图12为本发明的TFT基板结构的第一实施例的剖面示意图;
图13为本发明的TFT基板结构的第二实施例的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2,本发明首先提供一种TFT基板结构的制作方法,包括如下步骤:
步骤1、如图3所示,提供基板1,在所述基板1上沉积缓冲层2。
具体地,所述基板1可以是玻璃基板或塑料基板。所述缓冲层2的材料可以是氧化硅(SiOx)、氮化硅(SiNx)、或二者的组合。
步骤2、如图4所示,在所述缓冲层2上沉积多晶硅(poly-Si)层3。
步骤3、如图5所示,在所述多晶硅层3上沉积栅极绝缘层4,在所述栅极绝缘层4上沉积金属层5。
具体地,所述栅极绝缘层4的材料可以是氧化硅、氮化硅、或二者的组合。所述金属层5的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
步骤4、如图6、图7所示,在所述金属层5上涂布光阻层6,通过一道光罩对所述光阻层6进行曝光、显影,得到位于中间的第一光阻段61、及间隔分布于所述第一光阻段61两侧的两个第二光阻段62。
具体地,可以采用单缝光罩(SingleSlitMask,SSM)、半色调光罩(HakfToneMask,HTM)、或灰阶光罩(GrayToneMask,GTM)得到所述第一光阻段61、及两个第二光阻段62。
优选的,所述第一光阻段61与两个第二光阻段62之间的距离均小于1μm,所述第二光阻段62的宽度为1μm~2μm。
步骤5、如图8所示,以所述第一光阻段61、及两个第二光阻段62为阻挡层,对所述金属层5进行蚀刻,对应所述第一光阻段61下方得到栅极51,分别对应所述两个第二光阻段62下方得到两个金属段52。
具体地,可以采用干法蚀刻(DryEtch)或湿法蚀刻(WetEtch)得到所述栅极51、及两个金属段52。
具体的,由于所述栅极51与两个金属段52分别对应于所述第一光阻段61与两个第二光阻段62形成,因此,所述两个金属段52与所述栅极51之间的距离均小于1μm,所述金属段52的宽度为1μm~2μm。
本发明通过采用SSM/HTM/GTM光罩,将所述金属段52与栅极51之间的距离缩小为1μm以下,使得TFT基板的尺寸也能相应减小,有利于小尺寸器件的制造。
步骤6、剥离所述第一光阻段61、及两个第二光阻段62,以所述栅极51、及两个金属段52为光罩,对所述多晶硅层3进行离子注入,在所述多晶硅层3上对应所述栅极51下方形成未掺杂的沟道区33,对应所述沟道区33的两侧形成四个n型重掺杂区(n+)31,对应所述两个金属段52下方形成位于所述四个n型重掺杂区31之间的两个未掺杂区32。后续步骤可以采用现有技术实现。
具体的,与所述沟道区33相邻的两个n型重掺杂区31的宽度均小于1μm,所述未掺杂区32的宽度为1μm~2μm。
具体的,所述n型重掺杂区31中的n型离子浓度范围为1014~1015ions/cm3
请参阅图11,为本发明的TFT基板结构的制作方法的另一种实施方式的示意图,其不同之处在于:对光阻层进行曝光、显影后,分别得到位于中间的第一光阻段、及间隔分布于所述第一光阻段两侧的四个第二光阻段。对所述金属层进行蚀刻后,对应所述第一光阻段下方得到栅极51,分别对应所述四个第二光阻段下方得到四个金属段52,剥离所述第一光阻段、及四个第二光阻段后,以所述栅极51、及四个金属段52为光罩,对所述多晶硅层3进行离子注入,在所述多晶硅层3上对应所述沟道区33的两侧形成六个n型重掺杂区31,对应所述四个金属段52下方形成位于所述六个n型重掺杂区31之间的四个未掺杂区32,其余步骤均与上一实施方式相同,此处不再赘述。
因此,可以理解的是,所述间隔分布于第一光阻段两侧的第二光阻段的个数不受本发明实施例的具体限制,可以为两个或两个以上;从而对应的,在多晶硅层3上对应沟道区33的两侧形成的多个n型重掺杂区的数量也可以根据实际需要进行调整,不受具体数量限制。
本发明的TFT基板结构的制作方法,在制作栅极的同时,在栅极两侧形成间隔分布的数个金属段,并以栅极和数个金属段作为光罩,对多晶硅层进行离子注入,在多晶硅层上形成n型重掺杂区的同时,在n型重掺杂区之间形成未掺杂区,增加了阻值,分散了电极附近的强电场,避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响,提高了工作电流,简化了制程,降低了生产成本,减小了TFT基板的尺寸。
本发明还提供一种TFT基板结构,请参阅图12,为本发明的TFT基板结构的第一实施例的剖面示意图,包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的多晶硅层3、设于所述多晶硅层3上的栅极绝缘层4、设于所述栅极绝缘层4上的栅极51、及设于所述栅极绝缘层4上间隔分布于所述栅极51两侧的两个金属段52。
所述多晶硅层3包括对应于所述栅极51下方的未掺杂的沟道区33,位于所述沟道区33两侧的四个n型重掺杂区31,对应于所述两个金属段52下方且位于所述四个n型重掺杂区31之间的两个未掺杂区32。
优选的,所述两个金属段52与所述栅极51之间的距离均小于1μm,所述金属段52的宽度为1μm~2μm。与此相对应的,所述多晶硅层3上与所述沟道区33相邻的两个n型重掺杂区31的宽度均小于1μm,所述未掺杂区32的宽度为1μm~2μm。
具体的,所述n型重掺杂区31中的n型离子浓度范围为1014~1015ions/cm3
具体地,所述缓冲层2、及栅极绝缘层4的材料为氧化硅、氮化硅、或二者的组合;所述栅极51、及两个金属段52的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
请参阅图13,为本发明的TFT基板结构的第二实施例的剖面示意图,与第一实施例的区别在于,所述栅极绝缘层4上于所述栅极51两侧形成有四个金属段52,所述多晶硅层3上对应所述沟道区33的两侧形成有六个n型重掺杂区31,对应所述四个金属段52下方形成有位于所述六个n型重掺杂区31之间的四个未掺杂区32,其余结构均与第一实施例相同,此处不再赘述。
因此,可以理解的是,所述栅极绝缘层4上于栅极51两侧形成的金属段52的个数不受本发明实施例的具体限制,可以为两个或两个以上;从而对应的,在多晶硅层3上对应沟道区33的两侧形成的n型重掺杂区的数量也可以根据实际需要进行调整,不受具体数量限制。
上述TFT基板结构,多晶硅层的n型重掺杂区之间形成有未掺杂区,避免了局部强电场的产生,消除了热载流子效应对器件特性的影响,具有较高的工作电流,结构简单,生产成本低。
综上所述,本发明的TFT基板结构的制作方法,在制作栅极的同时,在栅极两侧形成间隔分布的数个金属段,并以栅极和数个金属段作为光罩,对多晶硅层进行离子注入,在多晶硅层形成n型重掺杂区的同时,在n型重掺杂区之间形成未掺杂区,增加了阻值,分散了电极附近的强电场,避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响,提高了工作电流,简化了制程,降低了生产成本,减小了TFT基板的尺寸。本发明的TFT基板结构,多晶硅层的n型重掺杂区之间形成有未掺杂区,避免了局部强电场的产生,消除了热载流子效应对器件特性的影响,具有较高的工作电流,结构简单,生产成本低。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

1.一种TFT基板结构的制作方法,其特征在于,包括如下步骤:
步骤1、提供基板(1),在所述基板(1)上沉积缓冲层(2);
步骤2、在所述缓冲层(2)上沉积多晶硅层(3);
步骤3、在所述多晶硅层(3)上沉积栅极绝缘层(4),在所述栅极绝缘层(4)上沉积金属层(5);
步骤4、在所述金属层(5)上涂布光阻层(6),通过一道光罩对所述光阻层(6)进行曝光、显影,得到位于中间的第一光阻段(61)、及间隔分布于所述第一光阻段(61)两侧的数个第二光阻段(62);
步骤5、以所述第一光阻段(61)、及数个第二光阻段(62)为阻挡层,对所述金属层(5)进行蚀刻,对应所述第一光阻段(61)下方得到栅极(51),分别对应所述数个第二光阻段(62)下方得到数个金属段(52);
步骤6、剥离所述第一光阻段(61)、及数个第二光阻段(62),以所述栅极(51)、及数个金属段(52)为光罩,对所述多晶硅层(3)进行离子注入,在所述多晶硅层(3)上对应所述栅极(51)下方形成未掺杂的沟道区(33),对应所述沟道区(33)的两侧形成数个n型重掺杂区(31),对应所述数个金属段(52)下方形成位于所述数个n型重掺杂区(31)之间的数个未掺杂区(32)。
2.如权利要求1所述的TFT基板结构的制作方法,其特征在于,所述步骤4采用单缝光罩、半色调光罩、或灰阶光罩得到所述第一光阻段(61)、及数个第二光阻段(62)。
3.如权利要求1所述的TFT基板结构的制作方法,其特征在于,靠近所述第一光阻段(61)两侧的两个第二光阻段(62)与所述第一光阻段(61)之间的距离均小于1μm,所述第二光阻段(62)的宽度为1μm~2μm。
4.如权利要求1所述的TFT基板结构的制作方法,其特征在于,所述步骤5采用干法蚀刻或湿法蚀刻得到所述栅极(51)、及数个金属段(52)。
5.如权利要求1所述的TFT基板结构的制作方法,其特征在于,靠近所述栅极(51)两侧的两个金属段(52)与所述栅极(51)之间的距离均小于1μm,所述金属段(52)的宽度为1μm~2μm。
6.如权利要求1所述的TFT基板结构的制作方法,其特征在于,所述缓冲层(2)、及栅极绝缘层(4)的材料为氧化硅、氮化硅、或二者的组合。
7.如权利要求1所述的TFT基板结构的制作方法,其特征在于,所述金属层(5)的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
8.一种TFT基板结构,其特征在于,包括基板(1)、设于所述基板(1)上的缓冲层(2)、设于所述缓冲层(2)上的多晶硅层(3)、设于所述多晶硅层(3)上的栅极绝缘层(4)、设于所述栅极绝缘层(4)上的栅极(51)、及设于所述栅极绝缘层(4)上且间隔分布于所述栅极(51)两侧的数个金属段(52);
所述多晶硅层(3)包括对应于所述栅极(51)下方的沟道区(33),位于所述沟道区(33)两侧的数个n型重掺杂区(31),以及对应于所述数个金属段(52)下方且位于所述数个n型重掺杂区(31)之间的数个未掺杂区(32)。
9.如权利要求8所述的TFT基板结构,其特征在于,靠近所述栅极(51)两侧的两个金属段(52)与所述栅极(51)之间的距离均小于1μm,所述金属段(52)的宽度为1μm~2μm。
10.如权利要求8所述的TFT基板结构,其特征在于,所述缓冲层(2)、及栅极绝缘层(4)的材料为氧化硅、氮化硅、或二者的组合;所述栅极(51)、及数个金属段(52)的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390451A (zh) * 2015-12-03 2016-03-09 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法
CN107980176A (zh) * 2016-12-24 2018-05-01 深圳市柔宇科技有限公司 薄膜晶体管阵列基板、低温多晶硅薄膜晶体管及制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340475A (ja) * 1999-04-22 1999-12-10 Sharp Corp トランジスタの製造方法
US20010028058A1 (en) * 1996-06-21 2001-10-11 Lg Electronics, Inc. Thin film transistor and a method of forming the same
US20050142680A1 (en) * 2003-12-29 2005-06-30 Lg Philips Lcd Co., Ltd. Method for fabrication liquid crystal display device and diffraction mask therefor
KR20070002491A (ko) * 2005-06-30 2007-01-05 엘지.필립스 엘시디 주식회사 폴리 실리콘형 박막 트랜지스터와 그를 가지는 폴리실리콘형 박막트랜지스터 기판 및 그 제조 방법
CN102194890A (zh) * 2010-03-15 2011-09-21 三星移动显示器株式会社 薄膜晶体管及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580094B1 (en) * 1999-10-29 2003-06-17 Semiconductor Energy Laboratory Co., Ltd. Electro luminescence display device
US6384427B1 (en) * 1999-10-29 2002-05-07 Semiconductor Energy Laboratory Co., Ltd. Electronic device
JP3522216B2 (ja) * 2000-12-19 2004-04-26 シャープ株式会社 薄膜トランジスタおよびその製造方法ならびに液晶表示装置
US7807516B2 (en) * 2005-06-30 2010-10-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US8115206B2 (en) * 2005-07-22 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2011024911A1 (ja) * 2009-08-28 2011-03-03 シャープ株式会社 半導体装置、アクティブマトリクス基板、及び表示装置
KR101284709B1 (ko) * 2010-09-20 2013-07-16 엘지디스플레이 주식회사 액정 표시장치와 이의 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010028058A1 (en) * 1996-06-21 2001-10-11 Lg Electronics, Inc. Thin film transistor and a method of forming the same
JPH11340475A (ja) * 1999-04-22 1999-12-10 Sharp Corp トランジスタの製造方法
US20050142680A1 (en) * 2003-12-29 2005-06-30 Lg Philips Lcd Co., Ltd. Method for fabrication liquid crystal display device and diffraction mask therefor
KR20070002491A (ko) * 2005-06-30 2007-01-05 엘지.필립스 엘시디 주식회사 폴리 실리콘형 박막 트랜지스터와 그를 가지는 폴리실리콘형 박막트랜지스터 기판 및 그 제조 방법
CN102194890A (zh) * 2010-03-15 2011-09-21 三星移动显示器株式会社 薄膜晶体管及其制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390451A (zh) * 2015-12-03 2016-03-09 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法
WO2017092142A1 (zh) * 2015-12-03 2017-06-08 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法
CN105390451B (zh) * 2015-12-03 2018-03-30 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法
CN107980176A (zh) * 2016-12-24 2018-05-01 深圳市柔宇科技有限公司 薄膜晶体管阵列基板、低温多晶硅薄膜晶体管及制造方法

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