CN104900704A - 一种纵向dmos器件 - Google Patents
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Abstract
一种纵向DMOS芯片,包括纵向DMOS器件,所述纵向DMOS器件包括A型漏区,位于A型漏区上方的B型漂移区,所述漂移区内有纵向栅极,所述纵向栅极侧壁和底部被纵向栅极绝缘层包围;所述纵向栅极绝缘层外侧设置有B型体区,所述B型体区远离纵向栅极绝缘层的一侧设置有A型源区,所述B型体区深度浅于纵向栅极深度,体区上方设置有横向栅极绝缘层,所述横向栅极绝缘层上方设置有横向栅极;所述漂移区掺杂浓度低于体区,所述A型、B型为载流子是空穴或电子的导电类型。本发明显著提高了栅源之间的器件耐压能力,同时提高了器件导通时的电流能力,导电沟道包括横向和纵向两个导电方向,进一步提高了器件的导通击穿电压。
Description
技术领域
本发明属于半导体器件领域,涉及一种纵向DMOS芯片。
背景技术
DMOS与CMOS器件结构类似,由源、漏、栅、体区等部分组成,DMOS还包括掺杂浓度较低的漂移区,使得可以在漏端得到较高的击穿电压。
DMOS主要有两种类型,垂直双扩散金属氧化物半导体场效应管VDMOS(vertical double-diffused MOSFET)和横向双扩散金属氧化物半导体场效应管LDMOS(lateral double-dif fused MOSFET)。其中VDMOS由于采用垂直结构,可以得到较大的电流导通能力和较低的导通电阻,同时由于漂移区的存在,在源漏之间的击穿电压值也较高。
DMOS器件是由成百上千的单一结构的DMOS 单元所组成的。这些单元的数目是根据一个芯片所需要的驱动能力所决定的,DMOS的性能直接决定了芯片的驱动能力和芯片面积。对于一个由多个基本单元结构组成的LDMOS器件,其中一个最主要的考察参数是导通电阻,用R ds(on)表示。导通电阻是指在器件工作时,从漏到源的电阻。对于 LDMOS器件应尽可能减小导通电阻,当导通电阻很小时,器件会提供一个很好的开关特性,因为漏源之间小的导通电阻,会有较大的输出电流,从而可以具有更强的驱动能力。DMOS的主要技术指标有:导通电阻、阈值电压、击穿电压等。
如图1所示给出了一种现有的VDMOS结构示意图,栅极内侧从上到下依次为源区和体区,当栅极通电时,体区反型形成沟道,由体区下方的漂移区承受高压,载流子在源极和漂移区下方的漏极之间形成导电通道,该器件的栅氧部分在栅极沟槽的底部和侧壁下部的厚度大于侧壁上部,以便在体区能够得到反型沟道,上述结构虽然取得了较高的漏源间击穿电压,但在栅极和源极之间紧邻且仅由较薄的栅氧化层隔离,使得栅极和源极之间耐压恶化,栅源之间击穿电压值大幅降低。
发明内容
为克服现有纵向DMOS器件在栅源处电压耐受能力低,容易被击穿的技术缺陷,本发明公开了一种纵向DMOS芯片。
本发明所述一种纵向DMOS芯片,包括纵向DMOS器件,所述纵向DMOS器件包括A型漏区,位于A型漏区上方的B型漂移区,所述漂移区内有纵向栅极,所述纵向栅极侧壁和底部被纵向栅极绝缘层包围;
所述纵向栅极绝缘层外侧设置有B型体区,所述B型体区远离纵向栅极绝缘层的一侧设置有A型源区,所述B型体区深度浅于纵向栅极深度,体区上方设置有横向栅极绝缘层,所述横向栅极绝缘层上方设置有横向栅极;
所述漂移区掺杂浓度低于体区,所述A型、B型为载流子是空穴或电子的导电类型。
优选的,所述横向栅极厚度大于纵向栅极位于体区和纵向栅极之间的纵向栅极绝缘层厚度。
优选的,所述源区与体区深度一致。
优选的,位于纵向栅极底部和侧壁下方的纵向栅极绝缘层厚度大于侧壁上方的纵向栅极绝缘层厚度,所述侧壁上方和侧壁下方的界线为体区底部。
优选的,所述纵向栅极、纵向栅极绝缘层、体区、源区在水平方向为依次从内到外的同心圆形状,所述横向栅极和横向栅极绝缘层为圆环形。
优选的,所述横向栅极和纵向栅极具有各自独立的电极引出孔。
优选的,所述体区宽度和深度之比为1:0.8-1.5,所述体区宽度为从源区到纵向栅极绝缘层在水平方向的距离。
采用本发明所述的纵向DMOS芯片,综合了纵向DMOS器件和横向DMOS器件优点,相对现有的纵向DMOS器件显著提高了栅源之间的器件耐压能力,同时采用对称布置的体区和源区,提高了器件导通时的电流能力,导电沟道包括横向和纵向两个导电方向,改善了沟道电场分布,进一步提高了器件的导通击穿电压。
附图说明
图1为现有的一种纵向DMOS芯片截面示意图;
图2示出本发明所述纵向DMOS芯片的一种具体实施方式结构示意图;
图3示出本发明所述纵向DMOS芯片的一种具体实施方式俯视示意图;
图2及图3中附图标记名称为:1-源区 2-体区 3-漂移区 4-漏区 5-横向栅极绝缘层 6-横向栅极7-纵向栅极侧壁上方的纵向栅极绝缘层8-纵向栅极 9-纵向栅极侧壁底部和侧壁下方的纵向栅极绝缘层,10-折线形沟道。
具体实施方式
下面结合附图,对本发明的具体实施方式作进一步的详细说明。
本发明所述一种纵向DMOS芯片,包括纵向DMOS器件,所述纵向DMOS器件包括A型漏区4,位于A型漏区上方的B型漂移区3,所述漂移区内有纵向栅极8,所述纵向栅极侧壁和底部被纵向栅极绝缘层包围;所述纵向栅极绝缘层外侧设置有B型体区2,所述B型体区远离纵向栅极绝缘层的一侧设置有A型源区,所述B型体区深度浅于纵向栅极深度,体区上方设置有横向栅极绝缘层,所述横向栅极绝缘层上方设置有横向栅极;所述漂移区掺杂浓度低于体区,所述A型、B型为载流子是空穴或电子的导电类型。
所述A型、B型为载流子是空穴或电子的导电类型,例如A型为P型时,B型为N型。
如图2所示的本发明一种具体实施方式中,以A型为P型,B型为N型为例,位于底部的为漏极,漏极掺杂类型为N型,通常掺杂浓度较大,漏极上方为P型漂移区,在DMOS中,漂移区是导通时的主要耐压区域,掺杂浓度较低,电阻较大。
在本发明中,体区2的垂直方向设置有纵向栅极8,水平方向设置有横向栅极6,纵向栅极4和横向栅极6与体区2之间分别由纵向栅极绝缘层和横向栅极绝缘层5隔离,栅极绝缘层可以为二氧化硅。
在纵向栅极和横向栅极均加以正向栅压,在体区上表面被横向栅极感应出横向沟道,体区靠近纵向栅极的侧面感应出纵向沟道,横向沟道与纵向沟道组成折线形沟道10,折线形沟道10连接源区1和漂移区3形成导电通路。
以往由于纵向栅极必须兼顾到体区与纵向栅极的感应反型,厚度不能取得太厚,造成纵向栅极与源区绝缘层有限,本发明采用上述结构设计,源区和栅极之间不再受限于纵向绝缘层厚度,源区与横向栅极形成的横向沟道实现电学连接,在横向栅极下方的横向栅极绝缘层厚度可以根据耐压需要自由控制,大幅度提高了栅源击穿电压。
同时,采用横向和纵向两个导电沟道组成折线形沟道,改善了体区中的沟道电场分布,进一步提高了器件的导通击穿电压。
其中,为保证横向沟道和纵向沟道的电流能力均衡,在横向栅极和纵向栅极施加的栅极电压一致时,所述体区宽度和深度之比优选设置为1:0.8-1.5,能够保证横向沟道和纵向沟道的完整成型,并在拐角处实现反型区的圆滑过渡,同时时折线形沟道的电流能力大致相同。所述体区宽度为从源区到纵向栅极绝缘层在水平方向的距离。
一种优选实施方式为横向栅极厚度大于纵向栅极位于体区和纵向栅极之间的纵向栅极绝缘层厚度,以增大横向栅极厚度的方式增强栅源耐压,并保证纵向栅极对体区的反型感应能力。
现有技术中纵向栅极与源区平行紧贴,容易聚集电荷造成击穿,本发明中横向栅极与体区并非紧邻,进一步改善了栅源交界处的电场分布,降低了电力线密度,提高了器件耐压性能。
在集成电路制造工艺中,横向栅极和纵向栅极可以由与之邻近的上层金属连接,使用公共电极,但横向栅极和纵向栅极也可以分别连接金属作为各自独立的电极引出孔,例如由于纵向栅极在垂直方向具有电阻,在较深处仍然需要具备感应反型能力,因此纵向栅极上可以施加高于横向栅极的电压。
源区与体区深度通常一致,方便形成源极到体区的电流通路,减小导通电阻并方便工艺刻蚀实现。
图2所示的具体实施方式中,位于纵向栅极底部和侧壁下方的纵向栅极绝缘层9厚度大于侧壁上方的纵向栅极绝缘层7的厚度,所述侧壁上方和侧壁下方的界线为体区2底部,以底部为限,底部以上为侧壁上方,底部以下为侧壁下方。
纵向栅极深入体区以下,可以改善纵向栅极对体区的感应,提高器件导通电流,但会在漂移区感应反型,在侧壁下方和纵向栅极底部采用加厚的绝缘层结构,削弱了纵向栅极对于漂移区的感应能力,提高了漂移区电压承受力,进一步提高了器件的耐压能力。
图2所示的具体实施方式中,可以以纵向栅极为中心,对称布置体区、源区和横向栅极,图3给出一种具体实施方式的俯视示意图,
如图3所示,所述纵向栅极、纵向栅极绝缘层、体区、源区在水平方向为依次从内到外的同心圆形状,所述横向栅极和横向栅极绝缘层为圆环形。采用上述同心圆形状,充分利用纵向栅极在水平方向的全向感应作用,最大限度扩展器件导通电流能力。
前文所述的为本发明的各个优选实施例,各个优选实施例中的优选实施方式如果不是明显自相矛盾或以某一优选实施方式为前提,各个优选实施方式都可以任意叠加组合使用,所述实施例以及实施例中的具体参数仅是为了清楚表述发明人的发明验证过程,并非用以限制本发明的专利保护范围,本发明的专利保护范围仍然以其权利要求书为准,凡是运用本发明的说明书及附图内容所作的等同结构变化,同理均应包含在本发明的保护范围内。
Claims (7)
1.一种纵向DMOS芯片,包括纵向DMOS器件,所述纵向DMOS器件包括A型漏区,位于A型漏区上方的B型漂移区,所述漂移区内有纵向栅极,所述纵向栅极侧壁和底部被纵向栅极绝缘层包围;
其特征在于,所述纵向栅极绝缘层外侧设置有B型体区,所述B型体区远离纵向栅极绝缘层的一侧设置有A型源区,所述B型体区深度浅于纵向栅极深度,体区上方设置有横向栅极绝缘层,所述横向栅极绝缘层上方设置有横向栅极;
所述漂移区掺杂浓度低于体区,所述A型、B型为载流子是空穴或电子的导电类型。
2. 如权利要求1所述的纵向DMOS芯片,其特征在于,所述横向栅极厚度大于纵向栅极位于体区和纵向栅极之间的纵向栅极绝缘层厚度。
3. 如权利要求1所述的纵向DMOS芯片,其特征在于,所述源区与体区深度一致。
4. 如权利要求1所述的纵向DMOS芯片,其特征在于,位于纵向栅极底部和侧壁下方的纵向栅极绝缘层厚度大于侧壁上方的纵向栅极绝缘层厚度,所述侧壁上方和侧壁下方的界线为体区底部。
5. 如权利要求1所述的纵向DMOS芯片,其特征在于,所述纵向栅极、纵向栅极绝缘层、体区、源区在水平方向为依次从内到外的同心圆形状,所述横向栅极和横向栅极绝缘层为圆环形。
6. 如权利要求1所述的纵向DMOS芯片,其特征在于,所述横向栅极和纵向栅极具有各自独立的电极引出孔。
7. 如权利要求1所述的纵向DMOS芯片,其特征在于,所述体区宽度和深度之比为1:0.8-1.5,所述体区宽度为从源区到纵向栅极绝缘层在水平方向的距离。
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