CN104752154A - Method for manufacturing capacitor - Google Patents
Method for manufacturing capacitor Download PDFInfo
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- CN104752154A CN104752154A CN201310739280.3A CN201310739280A CN104752154A CN 104752154 A CN104752154 A CN 104752154A CN 201310739280 A CN201310739280 A CN 201310739280A CN 104752154 A CN104752154 A CN 104752154A
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- capacitor
- bottom electrode
- dielectric layer
- electrode
- manufacture method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing a capacitor. A dielectric layer formed on the surface of a lower electrode is made to expose part of the lower electrode, and then, an upper electrode is formed on the surfaces of the dielectric layer and the exposed part of the lower electrode to make part of the upper electrode connected with the lower electrode. Thus, charges generated during formation of the upper electrode can be transferred to the lower electrode, there is no potential difference between the upper electrode and the lower electrode, and the formation of arc discharge defect is avoided. A capacitor is formed after the connecting part of the upper electrode and the lower electrode is removed. The formed capacitor is high in yield, and meets the requirements.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of capacitor.
Background technology
Usually metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor or metal-oxide-metal (Metal-Oxide-Metal, MOM) capacitor is used in semiconductor chip.Because metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor can obtain capacitance that is stable and that determine, therefore extensively adopt MIM capacitor in semiconductor chip.
In prior art, the manufacturing process of MIM capacitor comprises:
S1: Semiconductor substrate 10 is provided, form a bottom electrode 21 on the surface of described Semiconductor substrate 10, described bottom electrode 21 exposes the edge of Semiconductor substrate 10, as shown in Figure 1;
S2: form a dielectric layer 30 on the surface of described bottom electrode 21, described dielectric layer 30 all covers described bottom electrode 21, as shown in Figure 2;
S3: form a top electrode 22 on the surface of described dielectric layer 30, described top electrode 22 and bottom electrode 21 are kept apart by described dielectric layer 30, thus form mim capacitor structure, as shown in Figure 3;
S4: etch mim capacitor structure, forms MIM capacitor respectively in different chip unit.
But the MIM capacitor formed in prior art often meets with arc discharge defect (Arcingdefect), described arc discharge defect can cause MIM capacitor to lose efficacy, and affects the yield of semiconductor chip.
So how to solve arc discharge defect, the yield improving semiconductor chip just becomes the technical problem that those skilled in the art are badly in need of solution.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of capacitor, for the formation of qualified capacitor, avoid producing arc discharge defect.
To achieve these goals, the present invention proposes a kind of manufacture method of capacitor, comprise step:
Semiconductor crystal wafer is provided;
A bottom electrode is formed on the surface of described semiconductor crystal wafer;
Form a dielectric layer on the surface of described bottom electrode, make described dielectric layer expose a part of bottom electrode;
A top electrode is formed, the bottom electrode that described top electrode covers described dielectric layer and exposes on the surface of described dielectric layer;
Etch top electrode, dielectric layer and bottom electrode successively, and etching removes the part that described top electrode covers described bottom electrode, thus form multiple capacitor.
Further, after the surface of described bottom electrode forms described dielectric layer, the method for side washing is adopted to make described dielectric layer expose the marginal portion of described bottom electrode.
Further, before the surface of described bottom electrode forms described dielectric layer, use one to block ring and block a part of bottom electrode, then form described dielectric layer in the lower electrode surface exposed, then block ring described in removing, make the dielectric layer after formation expose a part of bottom electrode.
Further, after the described top electrode of formation, at surface-coated one deck photoresistance of described top electrode, exposure-processed is carried out to described photoresistance, then with described photoresistance for mask etches described top electrode, dielectric layer and bottom electrode successively, etching removes the part that described top electrode covers bottom electrode.
Further, described bottom electrode is aluminium or copper.
Further, described dielectric layer is the combination of silicon nitride, silica or silicon-nitride and silicon oxide-silicon nitride.
Further, power on described in very aluminium or copper.
Further, described wafer is provided with leading portion device architecture and back segment metal contact wires structure.
Further, described capacitor is MIM capacitor.
Further, described capacitor is MOM capacitor.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: make the dielectric layer being formed in lower electrode surface expose a part of bottom electrode, then top electrode is formed at dielectric layer and the lower electrode surface that exposes, some is connected with bottom electrode to make described top electrode, thus ensure that the time electric charge that produces forming top electrode also can conduct on described bottom electrode, make not there is electrical potential difference between top electrode and bottom electrode, thus avoid the formation of arc discharge defect, then the part that removal top electrode is connected with bottom electrode can form capacitor, thus make the capacitor yield of formation higher, meet the requirements.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the structural representation in the manufacturing process of MIM capacitor in prior art;
Fig. 4 is the flow chart of the manufacture method of capacitor in the embodiment of the present invention one;
Fig. 5 to Figure 10 is the structural representation in the manufacture method flow process of capacitor in the embodiment of the present invention one;
Figure 11 is the structural representation of the manufacture method of capacitor in the embodiment of the present invention two.
Embodiment
Be described in more detail below in conjunction with the manufacture method of schematic diagram to capacitor of the present invention, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
As mentioned by background technology, MIM capacitor of the prior art often suffers from arc discharge defect, inventor finds through large quantifier elimination, the reason producing arc discharge defect is in the process owing to being formed at top electrode, top electrode is constantly assembled electric charge, owing to there being the isolation of dielectric layer between top electrode and bottom electrode, both not conductings, along with the continuous increase of electric charge, electrical potential difference between top electrode and bottom electrode is increasing, due to Semiconductor substrate being formed with mark, the top electrode at mark place and bottom electrode all have a tip, because the electric field at tip place is very strong, electric charge is increased to and to a certain degree just can punctures dielectric layer, produce point discharge, and then form arc discharge defect.
Therefore, core concept of the present invention is: when forming top electrode, first make top electrode and bottom electrode short circuit, when top electrode produces electric charge, can transfer charge to bottom electrode, make top electrode and bottom electrode have identical electrical potential difference, thus avoid electric field to be formed, prevent from puncturing dielectric layer, ensure the performance of the capacitor formed.
Embodiment one
To achieve these goals, please refer to Fig. 4, propose a kind of manufacture method of capacitor in the present embodiment, comprise step:
S100: semiconductor crystal wafer 100 is provided, described semiconductor crystal wafer 100 is provided with leading portion device architecture and back segment metal contact wires structure;
S200: form a bottom electrode 210 on the surface of described semiconductor crystal wafer 100, as shown in Figure 5;
Described bottom electrode 210 can be copper or aluminium material, and as the bottom crown of capacitor, preferably, in order to the enforcement of subsequent chemical mechanical grinding technics, described bottom electrode 210 exposes the edge of described semiconductor crystal wafer 100.
S300: form a dielectric layer 300 on the surface of described bottom electrode 210, makes described dielectric layer 300 expose a part of bottom electrode 210, as shown in Figure 6 and Figure 7;
Concrete, in the present embodiment, after the surface of described bottom electrode 210 forms described dielectric layer 300, because described dielectric layer 300 covers described bottom electrode 210 completely, the method now can carrying out side washing to described semiconductor crystal wafer 100 makes described dielectric layer 300 expose the marginal portion of described bottom electrode 210, thus some is communicated with can to enable top electrode and bottom electrode during the follow-up formation top electrode in aspect.
S400: form a top electrode 220 on the surface of described dielectric layer 300, the bottom electrode 210 that described top electrode 220 covers described dielectric layer 300 and exposes, as shown in Figure 8;
Because now described top electrode 220 can be communicated with described bottom electrode 210, therefore when described top electrode 220 constantly has accumulation, also can by charge-conduction to described bottom electrode 210, make described top electrode 220 and bottom electrode 210 directly there is not electrical potential difference, thus prevent the generation of point discharge.
S500: etch top electrode 220, dielectric layer 300 and bottom electrode 210 successively, and etching removes the part that described top electrode 220 covers described bottom electrode 210, thus form multiple capacitor 500, as shown in Figure 9 and Figure 10.
In this step, first at the surface-coated photoresistance of described top electrode 220, then exposure-processed is carried out to described photoresistance, form the photoresistance 400 of patterning, then successively described top electrode 220, dielectric layer 300 and bottom electrode 210 are etched for mask with the photoresistance 400 of described patterning, etching removes the part that described top electrode 220 covers bottom electrode 210, and the marginal portion of the semiconductor crystal wafer 100 namely in the present embodiment, forms multiple capacitor 500.
In the present embodiment, the material of described bottom electrode 210, top electrode 220 is aluminium or copper, and the material of described dielectric layer 300 can be the combination of silicon nitride, silica or silicon-nitride and silicon oxide-silicon nitride (ONO).
In the present embodiment, described capacitor 500 can be MIM capacitor, also can be MOM capacitor.
Embodiment two
Please refer to Figure 11, in the present embodiment, manufacture method Integral Thought and the embodiment one of the capacitor of proposition are similar, expose a part of bottom electrode 210 unlike making described dielectric layer 300 in different ways.In the present embodiment, before the surface of described bottom electrode 210 forms described dielectric layer 300, use one to block ring 600 and block a part of bottom electrode 210, then described dielectric layer 300 is formed on bottom electrode 210 surface exposed, then ring 600 is blocked described in removing, the dielectric layer after formation 300 is made to expose a part of bottom electrode 210, the marginal portion that ring 600 can shelter from a part of bottom electrode 210(such as bottom electrode 210 is blocked) due to described, thus when forming dielectric layer 300, dielectric layer 300 all cannot cover described bottom electrode 210, thus described bottom electrode 210 can be made to expose a part, ensure that the top electrode of follow-up formation can be connected with a part for bottom electrode, avoid producing arc discharge defect.
Other steps forming capacitor are all identical with embodiment one, do not repeat them here, specifically please refer to embodiment one.
To sum up, in the manufacture method of the capacitor provided in the embodiment of the present invention, the dielectric layer being formed in lower electrode surface is made to expose a part of bottom electrode, then top electrode is formed at dielectric layer and the lower electrode surface that exposes, some is connected with bottom electrode to make described top electrode, thus ensure that the time electric charge that produces forming top electrode also can conduct on described bottom electrode, make not there is electrical potential difference between top electrode and bottom electrode, thus avoid the formation of arc discharge defect, then the part that removal top electrode is connected with bottom electrode can form capacitor, thus make the capacitor yield of formation higher, meet the requirements.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (10)
1. a manufacture method for capacitor, comprises step:
Semiconductor crystal wafer is provided;
A bottom electrode is formed on the surface of described semiconductor crystal wafer;
Form a dielectric layer on the surface of described bottom electrode, make described dielectric layer expose a part of bottom electrode;
A top electrode is formed, the bottom electrode that described top electrode covers described dielectric layer and exposes on the surface of described dielectric layer;
Etch top electrode, dielectric layer and bottom electrode successively, and etching removes the part that described top electrode covers described bottom electrode, thus form multiple capacitor.
2. the manufacture method of capacitor as claimed in claim 1, is characterized in that, after the surface of described bottom electrode forms described dielectric layer, adopts the method for side washing to make described dielectric layer expose the marginal portion of described bottom electrode.
3. the manufacture method of capacitor as claimed in claim 1, it is characterized in that, before the surface of described bottom electrode forms described dielectric layer, use one to block ring and block a part of bottom electrode, then described dielectric layer is formed in the lower electrode surface exposed, then block ring described in removing, make the dielectric layer after formation expose a part of bottom electrode.
4. the manufacture method of the capacitor as described in claim 1,2 or 3, it is characterized in that, after the described top electrode of formation, at surface-coated one deck photoresistance of described top electrode, exposure-processed is carried out to described photoresistance, then with described photoresistance for mask etches described top electrode, dielectric layer and bottom electrode successively, etching removes the part that described top electrode covers bottom electrode.
5. the manufacture method of capacitor as claimed in claim 1, it is characterized in that, described bottom electrode is aluminium or copper.
6. the manufacture method of capacitor as claimed in claim 1, it is characterized in that, described dielectric layer is the combination of silicon nitride, silica or silicon-nitride and silicon oxide-silicon nitride.
7. the manufacture method of capacitor as claimed in claim 1, is characterized in that, described in power on very aluminium or copper.
8. the manufacture method of capacitor as claimed in claim 1, it is characterized in that, described wafer is provided with leading portion device architecture and back segment metal contact wires structure.
9. the manufacture method of capacitor as claimed in claim 1, it is characterized in that, described capacitor is MIM capacitor.
10. the manufacture method of capacitor as claimed in claim 1, it is characterized in that, described capacitor is MOM capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310739280.3A CN104752154A (en) | 2013-12-27 | 2013-12-27 | Method for manufacturing capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310739280.3A CN104752154A (en) | 2013-12-27 | 2013-12-27 | Method for manufacturing capacitor |
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| CN104752154A true CN104752154A (en) | 2015-07-01 |
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| CN201310739280.3A Pending CN104752154A (en) | 2013-12-27 | 2013-12-27 | Method for manufacturing capacitor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107978590A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for eliminating MIM capacitor arc discharge defect |
| CN111933612A (en) * | 2020-10-09 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1111817A (en) * | 1993-12-28 | 1995-11-15 | 松下电子工业株式会社 | Manufacturing method of semiconductor devices |
| CN1577866A (en) * | 2003-07-25 | 2005-02-09 | 台湾积体电路制造股份有限公司 | Capacitor with improved capacitance density and method of manufacture |
| CN1750265A (en) * | 2004-09-14 | 2006-03-22 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN1937337A (en) * | 2005-06-15 | 2007-03-28 | 阿瓦戈科技Ecbuip(新加坡)股份有限公司 | Single epitaxial lateral overgrowth transverse p-n junction nitride semiconductor laser |
-
2013
- 2013-12-27 CN CN201310739280.3A patent/CN104752154A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1111817A (en) * | 1993-12-28 | 1995-11-15 | 松下电子工业株式会社 | Manufacturing method of semiconductor devices |
| CN1577866A (en) * | 2003-07-25 | 2005-02-09 | 台湾积体电路制造股份有限公司 | Capacitor with improved capacitance density and method of manufacture |
| CN1750265A (en) * | 2004-09-14 | 2006-03-22 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN1937337A (en) * | 2005-06-15 | 2007-03-28 | 阿瓦戈科技Ecbuip(新加坡)股份有限公司 | Single epitaxial lateral overgrowth transverse p-n junction nitride semiconductor laser |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107978590A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for eliminating MIM capacitor arc discharge defect |
| CN111933612A (en) * | 2020-10-09 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
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