CN212989976U - LDO circuit, LDO and SOC system - Google Patents
LDO circuit, LDO and SOC system Download PDFInfo
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- CN212989976U CN212989976U CN202022205384.4U CN202022205384U CN212989976U CN 212989976 U CN212989976 U CN 212989976U CN 202022205384 U CN202022205384 U CN 202022205384U CN 212989976 U CN212989976 U CN 212989976U
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Abstract
The utility model provides a LDO circuit, LDO and SOC system, the amplifier in the circuit or system adjusts the difference of reference voltage and output voltage partial pressure; when the output is low or low, the conduction of the output voltage low-surge control tube is weakened, the grid voltage of the power tube is reduced, the driving current of the power tube is increased, and the output voltage is quickly increased; when output overshoot is performed, the output voltage of the amplifier is reduced, the conduction of the low-overshoot control tube is enhanced, the grid voltage of the power tube is raised, and the output current of the power tube is reduced; because the grid voltage of the power tube is the same as that of the overshoot control tube, the grid voltage is increased to discharge the output of the overshoot voltage control tube, and the output voltage is quickly recovered; the output voltage low-surge control tube and the output voltage overshoot control tube are used for realizing the rapid load transient response of the LDO output; the circuit structure is simple, and the quiescent current and the cost are hardly increased.
Description
Technical Field
The utility model relates to a linear voltage regulator circuit technical field especially relates to a LDO circuit, LDO and SOC system.
Background
Due to the Board-level space limitation of PCBs (Printed Circuit boards), more and more Circuit modules are integrated into SOC (system on chip, also called system on chip) systems. Because of the features of small size, low noise, low ripple, etc., the power management circuit in the SOC system generally adopts a LDO (low dropout regulator) circuit architecture. In order to achieve fast transient response when a load suddenly changes, a conventional LDO circuit architecture generally terminates a μ F large external capacitor at an output terminal. In the SOC system, for convenience of on-chip integration, output capacitors of the LDO are all built-in, and capacitance values of the capacitors are generally not large, which causes load transient response of the LDO to be poor. In order to improve the transient response performance of the load, the LDO circuit usually adopts a complex architecture to control the charging and discharging of the grid electrode of the output power tube; the complex circuit architecture means more current branches, which inevitably increases the quiescent current of the LDO.
In order to prolong the service time of a battery power supply system, the SOC system has a low power consumption requirement in a standby mode, which conflicts with the above method for improving the transient response of the LDO, and only the quiescent current of the LDO can be reduced under the condition of ensuring low power consumption, thereby causing the load transient response performance of the LDO to be deteriorated.
Therefore, the prior art has yet to be improved.
Disclosure of Invention
An object of the utility model is to provide a LDO circuit, LDO and SOC system aims at solving current LDO circuit and can not compromise the problem of low LDO quiescent current and the quick load transient response performance of LDO simultaneously.
The technical scheme of the utility model as follows: an LDO circuit comprises a feedback voltage Amplifier (AMP), an output voltage low-surge control tube (MP 2), an output voltage overshoot control tube (MN 1), a first compensation network, a second compensation network, a first current source I1, a second current source I2, an output power tube (MP 1), an output voltage feedback divider resistance network and an output Capacitor (CL) of an internal voltage VDD;
the positive input end of the feedback voltage amplifier AMP is connected with a reference voltage VREF, the negative input end of the feedback voltage amplifier AMP is connected with an output voltage feedback divider resistance network, and the output end of the feedback voltage amplifier AMP is connected with the grid electrode of the output voltage low-surge control tube MP 2;
the output voltage undershoot control tube MP2 is provided with a grid electrode connected with the output end of the feedback voltage amplifier AMP, a source electrode connected with the output voltage VDD, and a drain electrode connected with the connection point of the grid electrode of the output voltage overshoot control tube MN1 and the grid electrode of the output power tube MP 1;
the gate of the output voltage overshoot control tube MN1 is connected with the connection point of the drain of the output voltage overshoot control tube MP2 and the gate of the output power tube MP1, the source is grounded, and the drain is connected with the output voltage VDD;
one end of the first compensation network is connected with the output end of the feedback voltage amplifier, and the other end of the first compensation network is grounded: the first compensation network is used for providing a compensation zero point;
one end of the second compensation network is connected with a power supply voltage VCC, the other end of the second compensation network is connected with the grid electrode of the output power tube MP1, and the second compensation network is used for providing another compensation zero point;
the connection point of the first current source I1 and the second current source I2 is connected with the grid of the output power tube MP1, the other end of the first current source I1 is connected with a power supply voltage VCC, and the other end of the second current source I2 is grounded;
the source of the output power tube MP1 is connected with a power supply voltage VCC, the grid of the output power tube MP1 is connected with the connection point of a first current source I1 and a second current source I2, and the drain of the output power tube MP1 is connected with an output voltage VDD;
one end of the output voltage feedback voltage-dividing resistance network is connected with an output voltage VDD, and the other end of the output voltage feedback voltage-dividing resistance network is grounded;
and one end of the output capacitor CL of the internal voltage VDD is connected with the output voltage VDD, and the other end of the output capacitor CL is grounded.
The LDO circuit, wherein the first compensation network includes a first compensation resistor Rf1 and a first compensation capacitor Cf1, one end of the first compensation resistor Rf1 is connected to the output terminal of the feedback voltage amplifier AMP, the other end of the first compensation resistor Rf1 is connected to the other end of the first compensation capacitor Cf1, and one end of the first compensation capacitor Cf1 is grounded.
The LDO circuit, wherein the second compensation network includes a second compensation resistor Rf2 and a second compensation capacitor Cf2, one end of the second compensation resistor Rf2 is connected to the gate of the output power transistor MP1, the other end of the second compensation resistor Rf2 is connected to the other end of the second compensation capacitor Cf2, and one end of the second compensation capacitor Cf2 is connected to the power supply voltage VCC.
The LDO circuit, wherein the output voltage feedback voltage-dividing resistor network includes a first output voltage feedback voltage-dividing resistor R1 and a second output voltage feedback voltage-dividing resistor R2, one end of the first output voltage feedback voltage-dividing resistor R1 is connected to the output voltage VDD, and the other end of the first output voltage feedback voltage-dividing resistor R1 is connected to the other end of the second output voltage feedback voltage-dividing resistor R2; one end of the second output voltage feedback divider resistor R2 is grounded.
The LDO circuit is characterized in that the feedback voltage amplifier AMP comprises a second NMOS transistor MN2, a third NMOS transistor MN3, a third current mirror PMOS transistor MP3 and a fourth current mirror PMOS transistor MP4, the divided voltage VFB of the output feedback resistor is connected with the grid electrode of the second NMOS transistor MN2, the reference voltage VREF is connected with the grid electrode of the third NMOS transistor MN3, the source electrodes of the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected together and then connected with one end of a current source I3, and the other end of the current source I3 is grounded; the drain terminal of the third NMOS transistor MN3 is connected with the drain electrode of the fourth current mirror PMOS transistor MP4, and the drain terminal of the second NMOS transistor MN2 is connected with the drain electrode of the third current mirror PMOS transistor MP 3; the grid electrode and the drain electrode of the fourth current mirror PMOS transistor MP4 are in short circuit, and the grid electrode of the fourth current mirror PMOS transistor MP4 is connected to the grid electrode of the third current mirror PMOS transistor MP 3; the source of the third current mirror PMOS transistor MP3 is connected to the output voltage VDD or the power supply voltage VCC, and the source of the fourth current mirror PMOS transistor MP4 is connected to the output voltage VDD or the power supply voltage VCC; the grid electrode of the output voltage low-surge control tube MP2 is connected with the connection point of the second NMOS tube MN2 and the third current mirror PMOS tube MP3, the source electrode of the output voltage low-surge control tube P2 is connected with the output voltage VDD, and the drain electrode of the output voltage low-surge control tube MP2 is connected with the connection point of the grid electrode of the output power tube MP1 and the grid electrode of the output voltage overshoot control tube MN 1; one end of the first compensation network is connected with the connection point of the second NMOS transistor MN2 and the third current mirror PMOS transistor MP3, and the other end of the first compensation network is grounded.
The LDO circuit is characterized in that the feedback voltage amplifier AMP comprises a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth current mirror NMOS tube MN4, a fifth current mirror NMOS tube MN5 and a source follower PMOS tube MP7, the output feedback resistor divided voltage VFB is connected with the grid electrode of the fifth PMOS tube MP5, the reference voltage VREF is connected with the grid electrode of the sixth PMOS tube MP6, the source electrodes of the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected together and then connected with one end of a current source I5, and the other end of the current source I5 is connected with the output voltage VDD or the power supply voltage VCC; the drain of the sixth PMOS transistor MP6 is connected to the drain of the fifth current mirror NMOS transistor MN5, and the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth current mirror NMOS transistor MN 4; the grid electrode and the drain electrode of the fifth NMOS tube MN5 are connected to the grid electrode of the fourth current mirror NMOS tube MN4 after being in short circuit; the grid electrode of the source following PMOS tube MP7 is connected with the connection point of the fourth current mirror NMOS tube MN4 and the fifth PMOS tube MP5, the drain electrode of the source following PMOS tube MP7 is grounded, and the source electrode of the source following PMOS tube MP7 is connected with the connection point of the current source I4 and the grid electrode of the output voltage low-surge control tube MP 2; one end of the current source I4 is connected with the output voltage VDD, and the other end is connected with the connection point of the grid electrode of the output voltage low-surge control tube MP2 and the source electrode of the source follower MOS tube MP 7; the grid electrode of the output voltage low-surge control tube MP2 is connected with the connection point of the PMOS tube MP7 and the current source I4, the source electrode of the output voltage low-surge control tube MP2 is connected with the output voltage VDD, and the drain electrode of the output voltage low-surge control tube MP2 is connected with the grid electrode of the output power tube MP1 and the grid electrode connection point of the output voltage overshoot control tube MN 1; one end of the first compensation network is connected with the connection point of the fourth current mirror NMOS transistor MN4 and the fifth PMOS transistor MP5, and the other end of the first compensation network is grounded.
In the LDO circuit, the output voltage low-surge control transistor MP2 is a PMOS transistor.
In the LDO circuit, the output voltage overshoot control transistor MN1 is an NMOS transistor.
In the LDO circuit, the output power transistor MP1 is a PMOS transistor.
An LDO, comprising an LDO circuit as claimed in any preceding claim.
An SOC system comprising an LDO circuit as claimed in any preceding claim.
The utility model has the advantages that: the utility model provides an LDO circuit, LDO and SOC system, adopt feedback voltage amplifier AMP to enlarge or reduce the difference of reference voltage VREF and output voltage's feedback voltage VFB; when the output voltage is low or low, the conduction of the output voltage low-surge control tube MP2 is weakened, the grid voltage of the output power tube MP1 is reduced, the driving current of the output power tube MP1 is increased, and the output voltage is quickly increased; when the output voltage overshoots, the output voltage of the amplifier is reduced, the conduction of the low-impact control tube MP2 is enhanced, the grid voltage of the output power tube MP1 is raised, and the output current of the output power tube MP1 is reduced; meanwhile, as the grid voltage of the output power tube MP1 is the same as the grid voltage potential of the overshoot control tube MN1, the rise of the grid voltage causes the overshoot control tube MN1 to discharge the output voltage VDD, and the output voltage is rapidly recovered to the set value; according to the scheme, the rapid load transient response of the output voltage of the LDO is realized through the output voltage low-surge control tube MP2 and the output voltage overshoot control tube MN 1; the circuit structure of realization is simple, and the branch current is all used for in the main loop, and quiescent current and cost hardly have the extra increase.
Drawings
Fig. 1 is a schematic structural diagram of the LDO circuit of the present invention.
Fig. 2a is a schematic diagram of one embodiment of the feedback voltage amplifier of the present invention.
Fig. 2b is a schematic diagram of another embodiment of the feedback voltage amplifier of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, an LDO circuit includes a feedback voltage amplifier AMP, an output voltage undershoot control tube MP2, an output voltage overshoot control tube MN1, a first compensation network, a second compensation network, a first current source I1, a second current source I2, an output power tube MP1, an output voltage feedback divider resistance network, and an output capacitor CL of an internal voltage VDD;
the positive input end of the feedback voltage amplifier AMP is connected with the reference voltage VREF, and the negative input end of the feedback voltage amplifier AMP is connected with the output voltage feedback divider resistance network: amplifying the difference value between the reference voltage VREF and the output feedback resistor divided voltage VFB; the output end of the voltage-controlled rectifier is connected with the grid of an output voltage low-surge control tube MP 2;
the output voltage undershoot control tube MP2 has a gate connected to the output of the feedback voltage amplifier AMP, a source connected to the output voltage VDD, and a drain connected to the connection point of the gate of the output voltage overshoot control tube MN1 and the gate of the output power tube MP 1. The output voltage of the feedback voltage amplifier AMP is rapidly increased when the output voltage is low or low, the conduction capability of the output voltage low-surge control tube MP2 is weakened, the grid of the output power tube MP1 is rapidly pulled down, the driving capability of the output current is strengthened, and the output voltage VDD is rapidly increased to the set voltage;
the gate of the output voltage overshoot control tube MN1 is connected to the connection point of the drain of the output voltage overshoot control tube MP2 and the gate of the output power tube MP1, the source is grounded, and the drain is connected to the output voltage VDD: when the output voltage overshoots, the output voltage of the feedback voltage amplifier AMP is rapidly reduced, the conduction current of the output voltage undershoot control tube MP2 is rapidly increased, the grid voltage of the output power tube MP1 is rapidly raised, and the output current of the output power tube MP1 is reduced; meanwhile, the gate voltage of the output power tube MP1 is the same as the gate voltage of the output voltage overshoot control tube MN1, so that the output voltage overshoot control tube MN1 discharges the output voltage VDD, and the output voltage VDD rapidly returns to the set voltage;
one end of the first compensation network is connected with the output end of the feedback voltage amplifier, and the other end of the first compensation network is grounded: the first compensation network is used for providing a compensation zero point;
one end of the second compensation network is connected with a power supply voltage VCC, and the other end of the second compensation network is connected with the grid electrode of an output power tube MP 1: the second compensation network is used for the other compensation zero point;
the connection point of the first current source I1 and the second current source I2 is connected to the gate of the output power transistor MP1, the other end of the first current source I1 is connected to the power supply voltage VCC, and the other end of the second current source I2 is grounded: the first current source I1 and the second current source I2 provide a stable operating point for the gate of the output power transistor MP 1;
the source of the output power transistor MP1 is connected to the power supply voltage VCC, the gate is connected to the connection point of the first current source I1 and the second current source I2, and the drain is connected to the output voltage VDD: the output power tube MP1 is used for controlling and generating an output voltage VDD to provide an output current;
one end of the output voltage feedback divider resistance network is connected with an output voltage VDD, and the other end of the output voltage feedback divider resistance network is grounded: the output voltage feedback voltage division resistor network is used for providing the divided voltage of the output voltage for the negative input end of the voltage amplifier AMP;
and one end of the output capacitor CL of the internal voltage VDD is connected with the output voltage VDD, and the other end of the output capacitor CL is grounded. The output capacitor CL of the internal voltage VDD is used to stabilize the output voltage and supply power to other internal modules, and provides a dominant pole P1= (RDSON// RL) × CL of the loop, where RDSON is the on-resistance of the output power transistor MP1, and RL is the output load resistance of the output voltage VDD.
In some specific embodiments, the first compensation network includes a first compensation resistor Rf1 and a first compensation capacitor Cf1, one end of the first compensation resistor Rf1 is connected to the output terminal of the feedback voltage amplifier AMP, the other end of the first compensation resistor Rf1 is connected to the other end of the first compensation capacitor Cf1, and one end of the first compensation capacitor Cf1 is grounded: the first compensation network is used to provide one compensation zero Z1= Rf1 × Cf 1.
In some specific embodiments, the second compensation network includes a second compensation resistor Rf2 and a second compensation capacitor Cf2, one end of the second compensation resistor Rf2 is connected to the gate of the output power transistor MP1, the other end of the second compensation resistor Rf2 is connected to the other end of the second compensation capacitor Cf2, and one end of the second compensation capacitor Cf2 is connected to the power supply voltage VCC: the second compensation network is used to provide another compensation zero Z2= Rf2 × Cf 2.
In some embodiments, the output voltage feedback voltage-dividing resistor network includes a first output voltage feedback voltage-dividing resistor R1 and a second output voltage feedback voltage-dividing resistor R2, one end of the first output voltage feedback voltage-dividing resistor R1 is connected to the output voltage VDD, and the other end of the first output voltage feedback voltage-dividing resistor R1 is connected to the other end of the second output voltage feedback voltage-dividing resistor R2; one end of the second output voltage feedback divider resistor R2 is grounded: the junction of the first output voltage feedback divider resistor R1 and the second output voltage feedback divider resistor R2 is connected to the negative input terminal of the feedback voltage amplifier AMP: the output voltage feedback voltage-dividing resistance network is used for providing the divided voltage of the output voltage for the negative input end of the voltage amplifier AMP.
The feedback voltage amplifier AMP amplifies or reduces the difference between the voltage VREF at the positive input end and the voltage VFB at the negative input end, the output voltage directly controls the grid electrode of the output voltage low-surge control tube MP2, and the conduction current of the output voltage low-surge control tube MP2 is enhanced or weakened according to the magnitude of the output voltage, so that the grid electrode voltage of the output power tube MP1 is controlled, the magnitude of the output current is adjusted, and the output voltage is stabilized; the output end node of the feedback voltage amplifier AMP introduces a high frequency pole P3= Cp3 Rp3 in the loop, wherein Cp3 is the sum of the capacitances connected to the output end of the feedback voltage amplifier AMP, and Rp3 is the sum of the resistances connected to the output end of the feedback voltage amplifier AMP.
In some embodiments, the feedback voltage amplifier AMP may be implemented by using different circuit architectures:
in fig. 2a, the feedback voltage amplifier AMP includes a second NMOS transistor MN2, a third NMOS transistor MN3, a third current mirror PMOS transistor MP3, and a fourth current mirror PMOS transistor MP4, the output feedback resistor divided voltage VFB is connected to the gate of the second MOS transistor MN2, the reference voltage VREF is connected to the gate of the third MOS transistor MN3, the sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected together and then connected to one end of a current source I3, and the other end of the current source I3 is grounded; the drain terminal of the third NMOS transistor MN3 is connected with the drain electrode of the fourth current mirror PMOS transistor MP4, and the drain terminal of the second NMOS transistor MN2 is connected with the drain electrode of the third current mirror PMOS transistor MP 3; the grid electrode and the drain electrode of the fourth current mirror PMOS transistor MP4 are in short circuit, and the grid electrode of the fourth current mirror PMOS transistor MP4 is connected to the grid electrode of the third current mirror PMOS transistor MP 3; according to the magnitude of the output voltage VDD and the power voltage VCC, the source voltages of the third current mirror PMOS transistor MP3 and the fourth current mirror PMOS transistor MP4 can be connected to the output voltage VDD or the power voltage VCC; the grid electrode of the output voltage low-surge control tube MP2 is connected with the connection point of the second NMOS tube MN2 and the third current mirror PMOS tube MP3, the source electrode of the output voltage low-surge control tube MP2 is connected with the output voltage VDD, and the drain electrode of the output voltage low-surge control tube MP2 is connected with the connection point of the grid electrode of the output power tube MP1 and the grid electrode of the output voltage overshoot control tube MN 1; one end of the first compensation resistor Rf1 is connected to the connection point of the second NMOS transistor MN2 and the third current mirror PMOS transistor MP3, the other end of the first compensation resistor Rf1 is connected to the other end of the first compensation capacitor Cf1, and one end of the first compensation capacitor Cf1 is grounded.
In fig. 2b, the feedback voltage amplifier AMP includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fourth current mirror NMOS transistor MN4, a fifth current mirror NMOS transistor MN5, and a source follower PMOS transistor MP7, the output feedback resistor divided voltage VFB is connected to the gate of the fifth PMOS transistor MP5, the reference voltage VREF is connected to the gate of the sixth PMOS transistor MP6, the sources of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected together and then connected to one end of a current source I5, and the other end of the current source I5 is connected to the power supply: according to the output voltage VDD and the power supply voltage VCC, the power supply voltage of the current source I5 can be connected with the output voltage VDD or the power supply voltage VCC; the drain of the sixth PMOS transistor MP6 is connected to the drain of the fifth current mirror NMOS transistor MN5, and the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth current mirror NMOS transistor MN 4; the grid electrode and the source electrode of the fifth NMOS transistor MN5 are connected to the grid electrode of the fourth current mirror NMOS transistor MN4 after being in short circuit; in order to construct a static operating point, a source following PMOS pipe MP7 is added; the grid electrode of the source following PMOS tube MP7 is connected with the connection point of the fourth current mirror NMOS tube MN4 and the fifth PMOS tube MP5, the drain electrode of the source following PMOS tube MP7 is grounded, and the source electrode of the source following PMOS tube MP7 is connected with the connection point of the current source I4 and the grid electrode of the output voltage low-surge control tube MP 2; one end of the current source I4 is connected with the output voltage VDD, and the other end is connected with the connection point of the grid electrode of the output voltage low-surge control tube MP2 and the source electrode of the source follower PMOS tube MP 7; the grid electrode of the output voltage low-surge control tube MP2 is connected with the connection point of the PMOS tube MP7 and the current source I4, the source electrode of the output voltage low-surge control tube MP2 is connected with the output voltage VDD, and the drain electrode of the output voltage low-surge control tube MP2 is connected with the grid electrode of the output power tube MP1 and the grid electrode connection point of the output voltage overshoot control tube MN 1; one end of the first compensation resistor Rf1 is connected to the connection point of the fourth current mirror NMOS transistor MN4 and the fifth PMOS transistor MP5, and the other end of the first compensation resistor Rf1 is connected to the other end of the first compensation capacitor Cf 1; one end of the first compensation capacitor Cf1 is grounded.
Naturally, there are many other circuit architectures of the feedback voltage amplifier AMP, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the circuit function that can be realized by the present invention, and these corresponding changes and modifications should fall within the protection scope of the present invention.
The output voltage low-surge control tube MP2 enhances or slows down its own (i.e. the output voltage low-surge control tube MP 2) conducting capability according to the magnitude of the output voltage of the voltage feedback amplifier AMP: when the output voltage is too low or low, the conduction current of the output voltage low-surge control tube MP2 is reduced, the gate voltage of the output power tube MP1 is reduced, the output current is increased, and the output voltage is increased.
When the output voltage overshoots, the output voltage overshoot control tube MN1 reduces the output voltage of the voltage feedback amplifier AMP, increases the on-current of the output voltage undershoot control tube MP2, increases the gate voltage of the output voltage overshoot control tube MN1, discharges the output voltage, and restores the output voltage to the set voltage.
The current source I1 and the current source I2 provide a stable operating point for the output power transistor MP 1.
The output power tube MP1 provides an output current and an output voltage, and the gate thereof introduces a sub-pole P2= Cp2 Rp2 in the loop, where Cp2 is the sum of the capacitances connected to the gate of the output power tube MP1, and Rp2 is the sum of the resistances connected to the gate of the output power tube MP 1.
Wherein the first compensation network introduces a first compensation zero Z1= Rf1 × Cf1 in the loop.
Wherein the second compensation network introduces a second compensation zero Z2= Rf2 × Cf2 in the loop.
The output capacitor CL of the internal voltage VDD provides energy storage for the output node, which generates a dominant pole P1= (RDSON// RL) × CL in the loop, where RDSON is the on-resistance of the output power transistor MP1, and RL is the output load resistance.
The output voltage divider resistance network mainly divides the output voltage, outputs the feedback resistor divided voltage VFB to the negative input end of the feedback voltage amplifier AMP, and amplifies or reduces the difference value between the output voltage VFB and the reference voltage VREF at the positive input end of the feedback voltage amplifier AMP.
According to the technical scheme, the difference value between the reference voltage VREF and the output feedback resistor divided voltage VFB is amplified or reduced by the feedback voltage amplifier AMP, and the low-surge voltage control tube MP2 and the overshoot voltage control tube MN1 are combined, so that the rapid load transient response of the LDO can be realized under the condition of low quiescent current.
This technical scheme still includes an LDO, includes the LDO circuit as described above.
This technical scheme still includes an SOC system, includes the LDO circuit as described above.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. The LDO circuit is characterized by comprising a feedback voltage amplifier AMP, an output voltage low-surge control tube MP2, an output voltage overshoot control tube MN1, a first compensation network, a second compensation network, a first current source I1, a second current source I2, an output power tube MP1, an output voltage feedback divider resistance network and an output capacitor CL of an internal voltage VDD;
the positive input end of the feedback voltage amplifier AMP is connected with a reference voltage VREF, the negative input end of the feedback voltage amplifier AMP is connected with an output voltage feedback divider resistance network, and the output end of the feedback voltage amplifier AMP is connected with the grid electrode of the output voltage low-surge control tube MP 2;
the output voltage undershoot control tube MP2 is provided with a grid electrode connected with the output end of the feedback voltage amplifier AMP, a source electrode connected with the output voltage VDD, and a drain electrode connected with the connection point of the grid electrode of the output voltage overshoot control tube MN1 and the grid electrode of the output power tube MP 1;
the gate of the output voltage overshoot control tube MN1 is connected with the connection point of the drain of the output voltage overshoot control tube MP2 and the gate of the output power tube MP1, the source is grounded, and the drain is connected with the output voltage VDD;
one end of the first compensation network is connected with the output end of the feedback voltage amplifier, and the other end of the first compensation network is grounded: the first compensation network is used for providing a compensation zero point;
one end of the second compensation network is connected with a power supply voltage VCC, and the other end of the second compensation network is connected with the grid electrode of an output power tube MP 1: the second compensation network is used for providing another compensation zero point;
the connection point of the first current source I1 and the second current source I2 is connected with the grid of the output power tube MP1, the other end of the first current source I1 is connected with a power supply voltage VCC, and the other end of the second current source I2 is grounded;
the source of the output power tube MP1 is connected with a power supply voltage VCC, the grid of the output power tube MP1 is connected with the connection point of a first current source I1 and a second current source I2, and the drain of the output power tube MP1 is connected with an output voltage VDD;
one end of the output voltage feedback voltage-dividing resistance network is connected with an output voltage VDD, and the other end of the output voltage feedback voltage-dividing resistance network is grounded;
and one end of the output capacitor CL of the internal voltage VDD is connected with the output voltage VDD, and the other end of the output capacitor CL is grounded.
2. The LDO circuit of claim 1, wherein the first compensation network comprises a first compensation resistor Rf1 and a first compensation capacitor Cf1, one end of the first compensation resistor Rf1 is connected to the output terminal of the feedback voltage amplifier AMP, the other end of the first compensation resistor Rf1 is connected to the other end of the first compensation capacitor Cf1, and one end of the first compensation capacitor Cf1 is grounded.
3. The LDO circuit of claim 1, wherein the second compensation network comprises a second compensation resistor Rf2 and a second compensation capacitor Cf2, one end of the second compensation resistor Rf2 is connected to the gate of the output power transistor MP1, the other end of the second compensation resistor Rf2 is connected to the other end of the second compensation capacitor Cf2, and one end of the second compensation capacitor Cf2 is connected to the power supply voltage VCC.
4. The LDO circuit of claim 1, wherein the output voltage feedback voltage-dividing resistor network comprises a first output voltage feedback voltage-dividing resistor R1 and a second output voltage feedback voltage-dividing resistor R2, one end of the first output voltage feedback voltage-dividing resistor R1 is connected to the output voltage VDD, and the other end of the first output voltage feedback voltage-dividing resistor R1 is connected to the other end of the second output voltage feedback voltage-dividing resistor R2; one end of the second output voltage feedback divider resistor R2 is grounded.
5. The LDO circuit of claim 1, wherein the feedback voltage amplifier AMP comprises a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fourth current mirror NMOS transistor MN4, a fifth current mirror NMOS transistor MN5 and a source follower PMOS transistor MP7, an output feedback resistor divided voltage VFB is connected to a gate of the fifth PMOS transistor MP5, a reference voltage VREF is connected to a gate of the sixth PMOS transistor MP6, sources of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected together and then connected to one end of a current source I5, and the other end of the current source I5 is connected to the output voltage VDD or the power supply voltage VCC; the drain of the sixth PMOS transistor MP6 is connected to the drain of the fifth current mirror NMOS transistor MN5, and the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth current mirror NMOS transistor MN 4; the grid electrode and the drain electrode of the NMOS tube MN5 are connected to the grid electrode of the fourth current mirror NMOS tube MN4 after being in short circuit; the grid electrode of the source following PMOS tube MP7 is connected with the connection point of the fourth current mirror NMOS tube MN4 and the fifth PMOS tube MP5, the drain electrode of the source following PMOS tube MP7 is grounded, and the source electrode of the source following PMOS tube MP7 is connected with the connection point of the current source I4 and the grid electrode of the output voltage low-surge control tube MP 2; one end of the current source I4 is connected with the output voltage VDD, and the other end is connected with the connection point of the grid electrode of the output voltage low-surge control tube MP2 and the source electrode of the source follower PMOS tube MP 7; the grid electrode of the output voltage low-surge control tube MP2 is connected with the connection point of the PMOS tube MP7 and the current source I4, the source electrode of the output voltage low-surge control tube MP2 is connected with the output voltage VDD, and the drain electrode of the output voltage low-surge control tube MP2 is connected with the grid electrode of the output power tube MP1 and the grid electrode connection point of the output voltage overshoot control tube MN 1; one end of the first compensation network is connected with the connection point of the fourth current mirror NMOS transistor MN4 and the fifth PMOS transistor MP5, and the other end of the first compensation network is grounded.
6. The LDO circuit of claim 1, wherein the output voltage low-surge control transistor MP2 is a PMOS transistor.
7. The LDO circuit of claim 1, wherein the output voltage overshoot control transistor MN1 is an NMOS transistor.
8. The LDO circuit of claim 1, wherein the output power transistor MP1 is a PMOS transistor.
9. An LDO, comprising the LDO circuit according to any of claims 1 to 8.
10. An SOC system comprising the LDO circuit according to any of claims 1 to 8.
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| CN202022205384.4U CN212989976U (en) | 2020-09-30 | 2020-09-30 | LDO circuit, LDO and SOC system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114510112A (en) * | 2022-01-12 | 2022-05-17 | 电子科技大学 | Transient enhancement circuit applied to low-power-consumption fully-integrated low dropout linear regulator |
| CN114647271A (en) * | 2022-05-23 | 2022-06-21 | 芯海科技（深圳）股份有限公司 | LDO circuit, control method, chip and electronic equipment |
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2020
- 2020-09-30 CN CN202022205384.4U patent/CN212989976U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114510112A (en) * | 2022-01-12 | 2022-05-17 | 电子科技大学 | Transient enhancement circuit applied to low-power-consumption fully-integrated low dropout linear regulator |
| CN114647271A (en) * | 2022-05-23 | 2022-06-21 | 芯海科技（深圳）股份有限公司 | LDO circuit, control method, chip and electronic equipment |
| CN115079763A (en) * | 2022-05-23 | 2022-09-20 | 芯海科技（深圳）股份有限公司 | LDO circuit, control method, chip and electronic equipment |
| CN115079763B (en) * | 2022-05-23 | 2023-06-06 | 芯海科技（深圳）股份有限公司 | LDO circuit, control method, chip and electronic equipment |
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