CN104681608A - n-type lateral diffusion metal oxide semiconductor (LDMOS) device with high isolation and manufacturing method thereof - Google Patents
n-type lateral diffusion metal oxide semiconductor (LDMOS) device with high isolation and manufacturing method thereof Download PDFInfo
- Publication number
- CN104681608A CN104681608A CN201310641803.0A CN201310641803A CN104681608A CN 104681608 A CN104681608 A CN 104681608A CN 201310641803 A CN201310641803 A CN 201310641803A CN 104681608 A CN104681608 A CN 104681608A
- Authority
- CN
- China
- Prior art keywords
- trap
- heavy doping
- annular
- light dope
- heavily doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title abstract description 3
- 238000009792 diffusion process Methods 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000002210 silicon-based material Substances 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 238000005516 engineering process Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000012163 sequencing technique Methods 0.000 claims 2
- 210000000746 body region Anatomy 0.000 abstract 2
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 51
- 238000001259 photo etching Methods 0.000 description 10
- 238000000137 annealing Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application discloses an n-type lateral diffusion metal oxide semiconductor (LDMOS) device with high isolation. A deep n-trap, a lightly doped n-trap and a lightly doped p-trap I are arranged in a p-type silicon substrate. A lightly doped p-trap is arranged in the deep n-trap; a heavily doped p-trap II and a heavily doped n-trap I are arranged in the lightly doped p-trap; an n-type heavily doped source and a body region leading out area are arranged in the heavily doped p-trap II; a drain is arranged in the heavily doped n-trap I; a gate oxide layer is arranged on a part of the heavily doped p-trap II and a part of the heavily doped n-trap I; polycrystalline silicon grids are arranged on the gate oxide and the adjacent partial isolation structure IV. The heavily doped p-trap I is arranged in the lightly doped p-trap I; a substrate leading out area is arranged in the heavily doped p-trap I. the heavily doped n-trap II is arranged in the lightly doped n-trap; a protection ring leading out area is arranged in the heavily doped n-trap II. A plurality of isolation structures are arranged on the surface of a silicon material. By utilizing the n-type LDMOS device disclosed by the application, the excellent electrical isolation between the body region and the substrate, between the substrate and the protection ring and between the drain and the protection ring can be realized.
Description
Technical field
The application relates to a kind of semiconductor device, particularly relates to a kind of LDMOS(laterally diffused MOS transistor) device.
Background technology
Refer to Fig. 1, this is a kind of cross-sectional view of existing N-shaped LDMOS device.In p-type silicon substrate (or epitaxial loayer) 100, have the lightly doped drift region 101 of N-shaped and heavy doping p trap 2 192, the latter is as tagma.In silicon substrate 100, also have the light dope p trap 1 of annular to be enclosed in outside drift region 101 and tagma 192.Also there is the heavy doping p trap 1 of annular in light dope p trap 1.There is the heavily doped substrate draw-out area 221 of p-type of annular in heavy doping p trap 1.There is draw-out area, p-type heavily doped tagma 225 and the heavily doped source electrode 223 of N-shaped in tagma 192.There is the heavily doped drain electrode 224 of N-shaped in drift region 101.There is on the surface of silicon substrate 100 isolation structure of multiple dielectric material.Wherein, the isolation structure 1 of annular is enclosed in the outside of substrate draw-out area 221.The isolation structure 170 of annular in the inner side of substrate draw-out area 221, and in the outside of drain electrode 224 and draw-out area, tagma 225.Isolation structure 4 174 is between grid 210 and drain electrode 224.On part tagma 192, part drift region 101, there is gate oxide 200.On gate oxide 200 and portions of isolation structure 4 174, there is polysilicon gate 210.
Said n type LDMOS device has following shortcoming:
One, because p-type body district 192 is arranged in p-type silicon substrate 100, thus can not realize the electric isolation of tagma and substrate.
Its two, can not high side circuitry be applied to.Refer to Fig. 2, this is high-end (high side) circuit diagram of N-shaped MOS transistor, and its drain electrode connects power supply, and source electrode is connected load then ground connection with draw-out area, tagma.If said n type LDMOS device is applied to high side circuitry, then because tagma and substrate can not be isolated, and source electrode is caused to be connected load then ground connection with draw-out area, tagma with substrate three.When the LDMOS device conducting of said n type, loaded level is raised, and makes source electrode and draw-out area, tagma and substrate three current potential also raise simultaneously, have impact on normal electric isolation between device and substrate.
Its three, drain electrode can not be applied to and add the situation of negative pressure, Substrate ground.If silicon substrate 100 ground connection, drain simultaneously and 224 add negative voltage, the PN junction so formed between p-type silicon substrate 100 and N-shaped drift region 101 will forward bias and conducting, can not realize the electric isolation of the N-shaped drain electrode 224 in N-shaped drift region 101 and substrate.
Refer to Fig. 3, this is the cross-sectional view of another kind of existing N-shaped LDMOS device.Compared to Figure 1, it instead of drift region 101 with lightly doped dark n trap 120.In FIG, drift region 101 roughly has identical junction depth with tagma 192, and does not comprise mutually, both or do not contact, or only contacts side surfaces.In figure 3, dark n trap 120 has surrounded tagma 192.Due to the existence of dark n trap 120, achieve the electric isolation between tagma 192 and silicon substrate 100, thus can be applied to high side circuitry.But device shown in Fig. 3 still can not be applied to the situation that drain electrode adds negative pressure, Substrate ground.
Refer to Fig. 4, this is the cross-sectional view of another existing N-shaped LDMOS device.There is lightly doped dark n trap 120 and light dope p trap 1 in the lightly doped silicon substrate of p-type (or epitaxial loayer) 100.The light dope p trap 1 of annular is enclosed in the outside of dark n trap 120.In dark n trap 120, have light dope p trap 2 132 and heavy doping n trap 2 180, the heavy doping n trap 2 180 of annular is enclosed in the outside of light dope p trap 2 132.In light dope p trap 2 132, have heavy doping p trap 2 192 and heavy doping n trap 1, the heavy doping p trap 2 192 of annular is enclosed in the outside of heavy doping n trap 1.On the heavy doping p trap 2 192 of part and the heavy doping n trap 1 of part, there is gate oxide 200.On gate oxide 200 with the portions of isolation structure 4 174 of next-door neighbour, there is polysilicon gate 210.There is the heavy doping p trap 1 of annular in light dope p trap 1.There is the p-type heavy doping substrate draw-out area 221 of annular in heavy doping p trap 1.There is the heavily doped guard ring draw-out area 222 of N-shaped of annular in heavy doping n trap 2 180.There is the draw-out area, p-type heavily doped tagma 225 of the heavily doped source electrode of N-shaped 223 and annular in heavy doping p trap 2 192.There is the heavily doped drain electrode 224 of N-shaped in heavy doping n trap 1.On the surface of silicon materials, there is multiple isolation structure 171 ~ 175.The isolation structure 1 of annular is enclosed in the outside of substrate draw-out area 221.The isolation structure 2 172 of annular is between substrate draw-out area 221 and guard ring draw-out area 222.The isolation structure 173 of annular is between guard ring draw-out area 222 and draw-out area, tagma 225.Isolation structure 4 174 is arranged in heavy doping n trap 1, and between polysilicon gate 210 and drain electrode 224.Isolation structure 5 175 is between drain electrode 224 and draw-out area, tagma 225.
Compared with Fig. 3, Fig. 4 has increased guard ring draw-out area 222 newly, and does guard ring by dark n trap 120 is double.Owing to having increased again light dope p trap 2 132 newly in dark n trap 120, the situation that drain electrode adds negative pressure, Substrate ground thus can be applied to.If but presenting reverse bias between substrate draw-out area 221 and guard ring draw-out area 222, then the junction depth due to dark n trap 120 is very large, is difficult to exhaust completely, is thus withstand voltagely restricted.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of N-shaped LDMOS device with high isolation, and its high isolation is embodied in:
One, realizes the electric isolation between tagma and substrate, to meet the application demand of high side circuitry.
Its two, realize the electric isolation of the High Pressure Difference between substrate and guard ring, withstand voltagely reach more than 100V, such as, reach 100 ~ 200V.
Its three, realize drain electrode and guard ring between electric isolation, add the application demand of negative pressure with satisfied drain electrode.
For solving the problems of the technologies described above, the N-shaped LDMOS device of the application's high isolation has lightly doped dark n trap, light dope n trap and light dope p trap one in the lightly doped silicon substrate of p-type or epitaxial loayer; The light dope n trap of annular is enclosed in the outside of dark n trap; The light dope p trap one of annular is enclosed in the outside of light dope n trap;
There is light dope p trap two in dark n trap; There is the heavy doping p trap two of heavy doping n trap one and annular in light dope p trap two; There is the draw-out area, p-type heavily doped tagma of the heavily doped source electrode of N-shaped and annular in heavy doping p trap two; There is the heavily doped drain electrode of N-shaped in heavy doping n trap one; On the heavy doping p trap two of part and the heavy doping n trap one of part, there is gate oxide; On the portions of isolation structure four of gate oxide and next-door neighbour, there is polysilicon gate;
There is the heavy doping p trap one of annular in light dope p trap one; There is the p-type heavy doping substrate draw-out area of annular in heavy doping p trap one;
There is the heavy doping n trap two of annular in light dope n trap; There is the heavily doped guard ring draw-out area of N-shaped of annular in heavy doping n trap two;
On the surface of silicon materials, there is multiple isolation structure; The isolation structure one of annular is enclosed in the outside of substrate draw-out area; The isolation structure two of annular is between substrate draw-out area and guard ring draw-out area; The isolation structure three of annular is between guard ring draw-out area and draw-out area, tagma; Isolation structure four is arranged in heavy doping n trap one, and between polysilicon gate and drain electrode; Isolation structure five is between drain electrode and draw-out area, tagma.
The manufacture method of the N-shaped LDMOS device of the high isolation of the application comprises the steps:
1st step, goes out one deck screen oxide in the Film by Thermal Oxidation of p-type silicon substrate or epitaxial loayer, then carries out ion implantation in a silicon substrate to form lightly doped dark n trap;
2nd step, carries out ion implantation in a silicon substrate to form the light dope p trap one of annular, is enclosed in the outside of dark n trap; In dark n trap, form light dope p trap two simultaneously;
3rd step, carry out ion implantation in a silicon substrate to form the light dope n trap of annular, it is positioned at the inner side of light dope p trap one, and is enclosed in the outside of dark n trap;
4th step, carries out ion implantation to form heavy doping n trap one in light dope p trap two;
5th step, first deposit one deck silicon nitride on screen oxide, then adopt selective oxidation or shallow grooved-isolation technique to form each isolation structure on silicon materials surface, then remove remaining silicon nitride;
6th step, carries out ion implantation to form the heavy doping n trap two of annular in light dope n trap; In light dope p trap one, carry out ion implantation to form the heavy doping p trap one of annular, in light dope p trap two, also form the heavy doping p trap two of annular simultaneously;
7th step, first removes all screen oxide, then at Film by Thermal Oxidation one deck gate oxide of silicon materials, then deposit one deck polysilicon on gate oxide and each isolation structure, finally etching is polysilicon gate;
8th step, first remove except below polysilicon gate with the gate oxide of exterior domain, in heavy doping p trap one, carry out the heavily doped substrate draw-out area of p-type that ion implantation forms annular again, in heavy doping p trap two, also form the draw-out area, p-type heavily doped tagma of annular simultaneously; In heavy doping n trap two, carry out ion implantation to form the heavily doped guard ring draw-out area of N-shaped of annular, in heavy doping p trap two, also form the heavily doped source electrode of N-shaped simultaneously, in heavy doping n trap one, also form the heavily doped drain electrode of N-shaped simultaneously.
The N-shaped LDMOS device of the application's high isolation can realize the electric isolation between tagma and substrate, the electric isolation between substrate and guard ring, electric isolation between drain electrode and guard ring.
Accompanying drawing explanation
Fig. 1 is the structural representation one of existing N-shaped LDMOS device;
Fig. 2 is the annexation schematic diagram of the high side circuitry of N-shaped MOS device;
Fig. 3 is the structural representation two of existing N-shaped LDMOS device;
Fig. 4 is the structural representation three of existing N-shaped LDMOS device;
Fig. 5 is the structural representation of the N-shaped LDMOS device of the application's high isolation;
Fig. 6 a ~ Fig. 6 g is each step schematic diagram of the manufacture method of the N-shaped LDMOS device of the application's high isolation.
Description of reference numerals in figure:
100 is the lightly doped silicon substrate of p-type (or epitaxial loayer); 101 is the lightly doped drift region of N-shaped; 110 is screen oxide; 120 is lightly doped dark n trap; 131 is light dope p trap one; 132 is light dope p trap two; 140 is light dope n trap; 150 attach most importance to Doped n trap one; 160 is silicon nitride; 170 ~ 175 is isolation structure; 180 attach most importance to Doped n trap two; 191 is heavy doping p trap one; 192 is heavy doping p trap two; 200 is gate oxide; 210 is polysilicon gate; 221 is the heavily doped substrate draw-out area of p-type; 222 is the heavily doped guard ring draw-out area of N-shaped; 223 is the heavily doped source electrode of N-shaped; 224 is the heavily doped drain electrode of N-shaped; 225 is draw-out area, p-type heavily doped tagma.
Embodiment
Refer to Fig. 5, this is the cross-sectional view of the N-shaped LDMOS device of the high isolation of the application.There is lightly doped dark n trap 120, light dope n trap 140 and light dope p trap 1 in the lightly doped silicon substrate of p-type (or epitaxial loayer) 100.Dark n trap 120 has maximum junction depth.If observed from depression angle, light dope n trap 140 is loop configuration, and be enclosed in the outside of dark n trap 120, both contact with each other side.Light dope p trap 1 is also loop configuration, and be enclosed in the outside of light dope n trap 140, both also contact with each other side.There is light dope p trap 2 132 in dark n trap 120.There is heavy doping p trap 2 192 and heavy doping n trap 1 in light dope p trap 2 132.Heavy doping p trap 2 192 is also loop configuration, is enclosed in the outside of heavy doping n trap 1.Heavy doping n trap 1 contacts with the side of the part that heavy doping p trap 2 192 is positioned at below polysilicon gate 210, and does not contact with the side of the remainder of heavy doping p trap 2 192 and isolated by light dope p trap 2 132.The puncture voltage of the PN junction between heavy doping p trap 2 192 and heavy doping n trap 1 can be improved like this.On the heavy doping p trap 2 192 of part and the heavy doping n trap 1 of part, there is gate oxide 200.On gate oxide 200 with the portions of isolation structure 4 174 of next-door neighbour, there is polysilicon gate 210.Polysilicon gate 210 is positioned at part on isolation structure 4 174 higher than the part be positioned on gate oxide 200.A part for polysilicon gate 210 is separated by gate oxide 200 directly over part heavy doping p trap 2 192, and another part is separated by gate oxide 200 or isolation structure 4 174 directly over part heavy doping n trap 1.There is the heavy doping p trap 1 of annular in light dope p trap 1.There is the p-type heavy doping substrate draw-out area 221 of annular in heavy doping p trap 1.There is the heavy doping n trap 2 180 of annular in light dope n trap 140.There is the heavily doped guard ring draw-out area 222 of N-shaped of annular in heavy doping n trap 2 180.There is the draw-out area, p-type heavily doped tagma 225 of the heavily doped source electrode of N-shaped 223 and annular in heavy doping p trap 2 192.There is the heavily doped drain electrode 224 of N-shaped in heavy doping n trap 1.On the surface of silicon materials, there is multiple isolation structure 171 ~ 175.The isolation structure 1 of annular is enclosed in the outside of substrate draw-out area 221.The isolation structure 2 172 of annular between substrate draw-out area 221 and guard ring draw-out area 222, for isolating both.The isolation structure 3 173 of annular between guard ring draw-out area 222 and draw-out area, tagma 225, for isolating both.Isolation structure 4 174 is arranged in heavy doping n trap 1, and polysilicon gate 210 and drain electrode 224 between, be used for isolation both.Isolation structure 5 175 between drain electrode 224 and draw-out area, tagma 225, for isolating both.
Wherein, the junction depth of heavy doping n trap 2 180, heavy doping p trap 1, heavy doping p trap 2 192 is roughly the same.And the junction depth of heavy doping n trap 1 is greater than former three.Heavy doping p trap 1 is roughly the same with the doping content of heavy doping p trap 2 192.And the doping content of heavy doping n trap 1 is less than heavy doping n trap 2 180.Why there is this feature, because heavy doping n trap 1 was formed by ion implantation technology before isolation structure 171 ~ 175 is formed, and heavy doping n trap 2 180, heavy doping p trap 1, heavy doping p trap 2 192 are all formed by ion implantation technology after isolation structure 171 ~ 175 is formed.The manufacture of isolation structure 171 ~ 175 needed in high temperature furnace through the long period, this can make, and the degree of depth of heavy doping n trap 1 becomes large, doping content diminishes, also make the doping of heavy doping n trap 1 more even simultaneously, electric field near drain electrode can be optimized when LDMOS device is operated in off state, improve puncture voltage.
The N-shaped LDMOS device tool of the high isolation of the application has the following advantages:
One, achieves the electric isolation between tagma and substrate, thus can be applicable to high side circuitry.Dark n trap 120 light dope p trap 2 132 is enclosed in the inside, thus heavy doping p trap two 192(achieved in light dope p trap 2 132 and tagma) and substrate between electric isolation.
Its two, achieve drain electrode and guard ring between electric isolation.Heavy doping n trap 1 is enclosed in the inside by light dope p trap 2 132; thus the electric isolation between the drain electrode 224 achieved in heavy doping n trap 1 and dark n trap 120, also just achieve drain electrode 224 and light dope n trap 140(and guard ring) between electric isolation.
Its three, meeting drain electrode and adding the application demand of negative pressure.Heavy doping n trap 1 is the drift region of drain electrode 224.Because itself and dark n trap 120 are kept apart by light dope p trap 2 132, so drain electrode 224 can add negative pressure.The application can add negative pressure in drain electrode 224, and draw-out area, tagma 225 adds identical or less negative pressure, and guard ring draw-out area 222 adds malleation, substrate draw-out area 221 ground connection, and LDMOS device also normally can work in specific operating voltage range.
Further, in the application, the junction depth of described dark n trap 120 is 8 ~ 10 μm, and its bulk concentration is 1 × 10
15~ 2.5 × 10
15atoms per cubic centimeter.The junction depth of light dope p trap 2 132 is 4 ~ 4.5 μm, and its bulk concentration is 1 × 10
16~ 2 × 10
16atoms per cubic centimeter.The junction depth of heavy doping n trap 1 is 1.2 ~ 1.4 μm, and its bulk concentration is 6 × 10
16~ 8 × 10
16atoms per cubic centimeter.Junction depth as the light dope n trap 140 of guard ring (Guard Ring) is 2.5 ~ 3 μm, and its bulk concentration is 5 × 10
14~ 7 × 10
14atoms per cubic centimeter.
Each trap parameter can bring following bonus effect above:
Its four, the withstand voltage of PN junction that dark n trap 120 and light dope p trap 2 132 are formed is brought up to more than 100V by the 50V in Fig. 4; Can avoid that tagma 192 and dark n trap 120 add high pressure simultaneously, substrate 100 ground connection time, there is horizontal and vertical punchthrough issues in PNP triode (being made up of p-type body district 192, dark n trap 120, p-type substrate 100) parasitic in device.
Its five, the withstand voltage of PN junction that substrate 100 and dark n trap 120 are formed is brought up to more than 100V by the 50V in Fig. 4; Reduce surface field based on RESURF(simultaneously, Reduced SURfsce Field) principle, interacted by the light dope p trap 1 of transverse direction and the p-type silicon substrate 100 of longitudinal direction and light dope n trap 140 is all exhausted before lateral junction reaches critical avalanche breakdown electric field.Compare with dark n trap 120, the junction depth of light dope n trap 140 is more shallow, bulk concentration is lighter, thus can apply higher voltage, and the withstand voltage of the PN junction formed by guard ring 140 and silicon substrate 100 can reach 100 ~ 200V.
In Fig. 4; guard ring is done because dark n trap 120 is double; if the bulk concentration of dark n trap 120 is light to enough making withstand voltage more than the 100V of reaching of the PN junction formed between dark n trap 120 and p-type substrate 100 and keeping the junction depth of dark n trap 120 constant, so because of too light as the dark n trap 120 of base, the parasitic PNP triode (being made up of p-type body district 192, dark n trap 120, p-type substrate 100) of device can not ensure that punch through voltage is constant.Therefore, Fig. 4 cannot meet simultaneously: improve the PN junction formed between dark n trap 120 and p-type substrate 100 withstand voltage, improve the conflicting demand of the punch through voltage these two of parasitic PNP triode (being made up of p-type body district 192, dark n trap 120, p-type substrate 100), limit the range of application of device operation voltage, the structure of the application then solves this pair demand simultaneously.
Its six, the withstand voltage of PN junction that light dope p trap 2 132 and heavy doping n trap 1 are formed is brought up to more than 100V by the 50V in Fig. 4; When can avoid that tagma 192 and heavy doping n trap 1 connect negative pressure, dark n trap 120 connects high pressure, there is horizontal and vertical punchthrough issues in NPN triode (being made up of heavy doping n trap 1, light dope n trap 2 132, dark n trap 120) parasitic in device simultaneously.
They are seven years old, based on RESURF principle, being interacted by the tagma 192 of transverse direction and the light dope p trap 2 132 of longitudinal direction makes heavy doping n trap 1 all exhaust before lateral junction reaches critical avalanche breakdown electric field, thus the puncture voltage of whole LDMOS device is brought up to more than 100V by the 50V in Fig. 4.
The manufacture method of the N-shaped LDMOS device of the high isolation of the application comprises the steps:
1st step, refer to Fig. 6 a, adopt thermal oxide growth technique to go out one deck screen oxide 110 in the superficial growth of p-type silicon substrate (or epitaxial loayer) 100, then adopt photoetching and ion implantation technology in silicon substrate 100, form lightly doped dark n trap 120, finally carry out annealing process.
2nd step, refers to Fig. 6 b, adopts photoetching and ion implantation technology in silicon substrate 100, form the light dope p trap 1 of annular, is enclosed in the outside of dark n trap 120.Same step p-type impurity injects and also forms light dope p trap 2 132 at dark n trap 120, then carries out annealing process.
3rd step, refers to Fig. 6 c, and adopt photoetching and ion implantation technology in silicon substrate 100, form the light dope n trap 140 of annular, it is positioned at the inner side of light dope p trap 1, and is enclosed in the outside of dark n trap 120.Then annealing process is carried out.
4th step, refers to Fig. 6 d, adopts photoetching and ion implantation technology to form heavy doping n trap 1 in light dope p trap 2 132, then carries out annealing process.
5th step, refers to Fig. 6 e, first adopts chemical vapor deposition (CVD) technique deposit one deck silicon nitride 160 on screen oxide 110, then adopts photoetching and etching technics the silicon nitride 160 of subregion and screen oxide 110 to be removed and expose silicon materials.Then selective oxidation (LOCOS) or shallow-trench isolation (STI) technique is adopted to expose the region formation isolation structure 171 ~ 175 of silicon materials.The isolation structure 1 of annular crosses over the line of demarcation of silicon substrate 100 and light dope p trap 1.The isolation structure 2 172 of annular crosses over the line of demarcation of light dope p trap 1 and light dope n trap 140.The isolation structure 3 173 of annular crosses over the line of demarcation of light dope n trap 140, deeply n trap 120 and light dope p trap 2 132 three.Isolation structure 4 174 is positioned at the surface of heavy doping n trap 1.Isolation structure 5 175 crosses over the line of demarcation of heavy doping n trap 1 and light dope p trap 2 132.Then remove remaining silicon nitride 160, such as, adopt wet corrosion technique.
6th step, refers to Fig. 6 f, adopts photoetching and ion implantation technology in light dope n trap 140, form the heavy doping n trap 2 180 of annular.Adopt photoetching and ion implantation technology in light dope p trap 1, form the heavy doping p trap 1 of annular again, same step p-type impurity injects the heavy doping p trap 2 192 also forming annular at light dope p trap 2 132.Twi-lithography in this step and ion implantation technology (be respectively N-shaped injects, p-type inject) can exchange order.Finally carry out annealing process.
7th step, refers to Fig. 6 g, first adopts dry method to anti-carve or wet corrosion technique removes all screen oxide 110, then adopts thermal oxide growth technique at superficial growth one deck gate oxide 200 of silicon materials.Then chemical vapor deposition method deposit one deck polysilicon 210 on gate oxide 200 and each isolation structure 171 ~ 175 is adopted.Photoetching and etching technics is finally adopted to etch this layer of polysilicon 210 into polysilicon gate 210.The part of polysilicon gate 210 after etching is separated by gate oxide 200 directly over the heavy doping p trap 2 192 of part, and another part is separated by gate oxide 200 or isolation structure 4 174 directly over the heavy doping n trap 1 of part.
8th step, refers to Fig. 5, first adopt dry method anti-carve or wet corrosion technique remove except below polysilicon gate 210 with the gate oxide 200 of exterior domain.Adopt photoetching and ion implantation technology in heavy doping p trap 1, form the heavily doped substrate draw-out area 221 of p-type of annular again, same step p-type impurity injects the draw-out area, p-type heavily doped tagma 225 also forming annular at heavy doping p trap 2 192.Adopt photoetching and ion implantation technology in heavy doping n trap 2 180, form the heavily doped guard ring draw-out area 222 of N-shaped of annular again; same step N-shaped impurity injects and also forms the heavily doped source electrode 223 of N-shaped at heavy doping p trap 2 192, and same step N-shaped impurity injects and also forms the heavily doped drain electrode 224 of N-shaped at heavy doping n trap 1.Twi-lithography in this step and ion implantation technology (be respectively p-type is injected, N-shaped inject) can exchange order.Finally carry out annealing process.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (7)
1. a N-shaped LDMOS device for high isolation, is characterized in that, has lightly doped dark n trap, light dope n trap and light dope p trap one in the lightly doped silicon substrate of p-type or epitaxial loayer; The light dope n trap of annular is enclosed in the outside of dark n trap; The light dope p trap one of annular is enclosed in the outside of light dope n trap;
There is light dope p trap two in dark n trap; There is the heavy doping p trap two of heavy doping n trap one and annular in light dope p trap two; There is the draw-out area, p-type heavily doped tagma of the heavily doped source electrode of N-shaped and annular in heavy doping p trap two; There is the heavily doped drain electrode of N-shaped in heavy doping n trap one; On the heavy doping p trap two of part and the heavy doping n trap one of part, there is gate oxide; On the portions of isolation structure four of gate oxide and next-door neighbour, there is polysilicon gate;
There is the heavy doping p trap one of annular in light dope p trap one; There is the p-type heavy doping substrate draw-out area of annular in heavy doping p trap one;
There is the heavy doping n trap two of annular in light dope n trap; There is the heavily doped guard ring draw-out area of N-shaped of annular in heavy doping n trap two;
On the surface of silicon materials, there is multiple isolation structure; The isolation structure one of annular is enclosed in the outside of substrate draw-out area; The isolation structure two of annular is between substrate draw-out area and guard ring draw-out area; The isolation structure three of annular is between guard ring draw-out area and draw-out area, tagma; Isolation structure four is arranged in heavy doping n trap one, and between polysilicon gate and drain electrode; Isolation structure five is between drain electrode and draw-out area, tagma.
2. the N-shaped LDMOS device of high isolation according to claim 1, is characterized in that, the degree of depth of heavy doping n trap one is greater than heavy doping n trap two, heavy doping p trap one and heavy doping p trap two; The doping content of heavy doping n trap two is greater than heavy doping n trap one.
3. the N-shaped LDMOS device of high isolation according to claim 1, is characterized in that, the junction depth of dark n trap is 8 ~ 10 μm, and bulk concentration is 1 × 10
15~ 2.5 × 10
15atoms per cubic centimeter; The junction depth of light dope p trap two is 4 ~ 4.5 μm, and bulk concentration is 1 × 10
16~ 2 × 10
16atoms per cubic centimeter; The junction depth of heavy doping n trap one is 1.2 ~ 1.4 μm, and bulk concentration is 6 × 10
16~ 8 × 10
16atoms per cubic centimeter; The junction depth of light dope n trap is 2.5 ~ 3 μm, and bulk concentration is 5 × 10
14~ 7 × 10
14atoms per cubic centimeter.
4. the N-shaped LDMOS device of high isolation according to claim 1, is characterized in that, the junction depth of light dope n trap is more shallow than dark n trap, and the doping content of light dope n trap is less than dark n trap.
5. a manufacture method for the N-shaped LDMOS device of high isolation, is characterized in that, comprise the steps:
1st step, goes out one deck screen oxide in the Film by Thermal Oxidation of p-type silicon substrate or epitaxial loayer, then carries out ion implantation in a silicon substrate to form lightly doped dark n trap;
2nd step, carries out ion implantation in a silicon substrate to form the light dope p trap one of annular, is enclosed in the outside of dark n trap; In dark n trap, form light dope p trap two simultaneously;
3rd step, carry out ion implantation in a silicon substrate to form the light dope n trap of annular, it is positioned at the inner side of light dope p trap one, and is enclosed in the outside of dark n trap;
4th step, carries out ion implantation to form heavy doping n trap one in light dope p trap two;
5th step, first deposit one deck silicon nitride on screen oxide, then adopt selective oxidation or shallow grooved-isolation technique to form each isolation structure on silicon materials surface, then remove remaining silicon nitride;
6th step, carries out ion implantation to form the heavy doping n trap two of annular in light dope n trap; In light dope p trap one, carry out ion implantation to form the heavy doping p trap one of annular, in light dope p trap two, also form the heavy doping p trap two of annular simultaneously;
7th step, first removes all screen oxide, then at Film by Thermal Oxidation one deck gate oxide of silicon materials, then deposit one deck polysilicon on gate oxide and each isolation structure, finally etching is polysilicon gate;
8th step, first remove except below polysilicon gate with the gate oxide of exterior domain, in heavy doping p trap one, carry out the heavily doped substrate draw-out area of p-type that ion implantation forms annular again, in heavy doping p trap two, also form the draw-out area, p-type heavily doped tagma of annular simultaneously; In heavy doping n trap two, carry out ion implantation to form the heavily doped guard ring draw-out area of N-shaped of annular, in heavy doping p trap two, also form the heavily doped source electrode of N-shaped simultaneously, in heavy doping n trap one, also form the heavily doped drain electrode of N-shaped simultaneously.
6. the manufacture method of the N-shaped LDMOS device of high isolation according to claim 5, is characterized in that, has twice ion implantation technology in described method the 6th step, and be that N-shaped impurity injects, p-type impurity injects respectively, its sequencing exchanges.
7. the manufacture method of the N-shaped LDMOS device of high isolation according to claim 5, is characterized in that, has twice ion implantation technology in described method the 8th step, and be that p-type impurity injects, N-shaped impurity injects respectively, its sequencing exchanges.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310641803.0A CN104681608B (en) | 2013-12-03 | 2013-12-03 | The n-type LDMOS device and its manufacture method of a kind of high isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310641803.0A CN104681608B (en) | 2013-12-03 | 2013-12-03 | The n-type LDMOS device and its manufacture method of a kind of high isolation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104681608A true CN104681608A (en) | 2015-06-03 |
| CN104681608B CN104681608B (en) | 2017-12-05 |
Family
ID=53316430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310641803.0A Active CN104681608B (en) | 2013-12-03 | 2013-12-03 | The n-type LDMOS device and its manufacture method of a kind of high isolation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104681608B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403751A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造（天津）有限公司 | The preparation method of localized oxidation of silicon isolating device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000183181A (en) * | 1998-12-10 | 2000-06-30 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
| KR100289056B1 (en) * | 1997-12-19 | 2001-10-24 | 정선종 | Method for manufacturing power device using sloped etching of insulating layer |
| US20020109184A1 (en) * | 2000-12-31 | 2002-08-15 | Texas Instruments Incorporated | LDMOS with improved safe operating area |
| US20060086973A1 (en) * | 2004-10-21 | 2006-04-27 | Mitsuharu Hitani | Semiconductor integrated circuit and a semiconductor device |
| CN102623353A (en) * | 2012-04-17 | 2012-08-01 | 上海华力微电子有限公司 | Manufacturing method of N-LDMOS (N-Laterally Diffused Metal Oxide Semiconductor) |
| US20130277742A1 (en) * | 2012-04-24 | 2013-10-24 | United Microelectronics Corp. | Semiconductor structure and method for manufacturing the same |
-
2013
- 2013-12-03 CN CN201310641803.0A patent/CN104681608B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100289056B1 (en) * | 1997-12-19 | 2001-10-24 | 정선종 | Method for manufacturing power device using sloped etching of insulating layer |
| JP2000183181A (en) * | 1998-12-10 | 2000-06-30 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
| US20020109184A1 (en) * | 2000-12-31 | 2002-08-15 | Texas Instruments Incorporated | LDMOS with improved safe operating area |
| US20060086973A1 (en) * | 2004-10-21 | 2006-04-27 | Mitsuharu Hitani | Semiconductor integrated circuit and a semiconductor device |
| CN102623353A (en) * | 2012-04-17 | 2012-08-01 | 上海华力微电子有限公司 | Manufacturing method of N-LDMOS (N-Laterally Diffused Metal Oxide Semiconductor) |
| US20130277742A1 (en) * | 2012-04-24 | 2013-10-24 | United Microelectronics Corp. | Semiconductor structure and method for manufacturing the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403751A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造（天津）有限公司 | The preparation method of localized oxidation of silicon isolating device |
| CN107403751B (en) * | 2016-05-20 | 2020-08-28 | 中芯国际集成电路制造（天津）有限公司 | Method for preparing local silicon oxidation isolation device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104681608B (en) | 2017-12-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102088022B (en) | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof | |
| CN103178093B (en) | The structure of high-voltage junction field-effect transistor and preparation method | |
| US9059281B2 (en) | Dual L-shaped drift regions in an LDMOS device and method of making the same | |
| CN102254946B (en) | Radio frequency transverse diffusion N-type Metal Oxide Semiconductor (MOS) tube and manufacturing method thereof | |
| CN103050541A (en) | Radio frequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof | |
| CN105720098A (en) | Nldmos and manufacturing method thereof | |
| CN104716177A (en) | Radio frequency LOMOS device for overcoming electricity leakage and manufacturing method of radio frequency LOMOS device for overcoming electricity leakage | |
| CN103633089B (en) | Polysilicon resistance and manufacture method thereof | |
| CN105448916A (en) | Transistor and method of forming same | |
| CN104377244A (en) | Device structure lowering LDMOS on resistance | |
| CN104658913B (en) | NLDMOS manufacture method | |
| CN104716179A (en) | LDMOS device with deep hole and manufacturing method thereof | |
| CN103545346B (en) | Isolated form N-type LDMOS device and manufacture method thereof | |
| US8673712B2 (en) | Power transistor with high voltage counter implant | |
| CN105140289A (en) | N-type LDMOS device and technical method thereof | |
| CN102646712B (en) | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof | |
| CN102983161B (en) | Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices | |
| CN104681608A (en) | n-type lateral diffusion metal oxide semiconductor (LDMOS) device with high isolation and manufacturing method thereof | |
| CN104576730A (en) | Superjunction device and manufacturing method thereof | |
| KR20120069417A (en) | Semiconductor device and method of manufacturing the same | |
| CN103199110B (en) | A kind of NLDMOS device and manufacture method thereof | |
| CN201918391U (en) | Radio frequency transverse diffusion N-type MOS (metal oxide semiconductor) tube | |
| CN102064193B (en) | Double diffusion drain metal oxide semiconductor field effect transistor (DDDMOS) and manufacturing method thereof | |
| CN104681609A (en) | n-type LDMOS device and manufacturing method thereof | |
| CN105551944A (en) | Manufacturing method for power transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |