CN104716179A - LDMOS device with deep hole and manufacturing method thereof - Google Patents

LDMOS device with deep hole and manufacturing method thereof Download PDF

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Publication number
CN104716179A
CN104716179A CN201310675662.4A CN201310675662A CN104716179A CN 104716179 A CN104716179 A CN 104716179A CN 201310675662 A CN201310675662 A CN 201310675662A CN 104716179 A CN104716179 A CN 104716179A
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drift region
tagma
doping type
ldmos device
polysilicon
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陈瑜
陈华伦
邢超
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention discloses an LDMOS device with a deep hole. A drift region and a body region are arranged in a silicon substrate or an epitaxial layer. The drift region is provided with a liner oxidation layer and filling structures, a gate oxidation layer is arranged on a silicon material and is provided with a polysilicon grid, the filling structures are made of polysilicon materials, are vertical and are divided into two parts in the vertical direction, the top of the first part penetrates through the gate oxidization layer and is connected with the bottom of the polysilicon grid, the side wall of the first part is surrounded by the gate oxidation layer, and the side wall and the bottom of the second part are surrounded by the liner oxidation layer. The polysilicon grid is divided into two parts in the horizontal direction, the first part is spaced with the gate oxidation layer and is over part of the body region, and the second part is spaced with the gate oxidation layer and is over part of the drift region. The second part of the polysilicon grid is over all the filling structures and is connected with the top ends of all the filling structures. The LDMOS device can improve breakdown voltage and meanwhile reduce on-resistance.

Description

A kind of LDMOS device and manufacture method thereof with deep hole
Technical field
The application relates to a kind of semiconductor device, particularly relates to a kind of LDMOS(laterally diffused MOS transistor) device.
Background technology
Refer to Fig. 1, this is a kind of cross-sectional view of existing LDMOS device.In p-type silicon substrate (or epitaxial loayer) 100, have N-shaped drift region 101 and p-type body district 102, both sides can contact with each other, and also can not contact.There is isolation structure 103 and N-shaped drain electrode 107 that side contacts with each other in drift region 101.Isolation structure 103 is the dielectric materials such as such as silica, adopts selective oxidation (LOCOS) or shallow-trench isolation (STI) manufacture technics.In tagma 102, have N-shaped source electrode 106 and draw-out area, p-type body district 108, both sides can contact with each other, and also can not contact.Gate oxide 104 is had on silicon materials (comprising silicon substrate 100, drift region 101, tagma 102, source electrode 106, drain electrode 107, draw-out area, tagma 108) except isolation structure 103.On the isolation structure 103 of part and the gate oxide 104 of part, there is polysilicon gate 105.This polysilicon gate 105 can be divided into three parts in the horizontal direction, Part I is separated by gate oxide 104 directly over part tagma 102, Part II is separated by gate oxide 104 directly over part drift region 101, and Part III is separated by isolation structure 103 directly over part drift region 101.The doping type of the Each part of above-mentioned LDMOS device becomes on the contrary, is also feasible.
The structure of the LDMOS device shown in Fig. 1 can be deformed into shown in Fig. 1 a, and difference is only that N-shaped drift region 101 does not contact with the side in p-type body district 102, and centre has p-type silicon substrate (or epitaxial loayer) 100 to isolate.
In above-mentioned LDMOS device, if the side in N-shaped drift region 101 and p-type body district 102 contacts, then the PN junction that both are formed operationally bears the high pressure between source, leakage.If N-shaped drift region 101 does not contact with the side in p-type body district 102, then the PIN structural formed together with the silicon substrate (or epitaxial loayer) 100 of centre both operationally bears the high pressure between source, leakage.
Refer to Fig. 4 and Fig. 5, they show respectively the Electric Field Distribution of device architecture shown in Fig. 1 and Fig. 1 a.In the diagram, electric field distribution triangular in shape, the electric field strength highest point of depletion region is positioned at gate oxide 104 and drift region 101 intersection.In Figure 5, electric field is distribution triangular in shape also, and the electric field strength highest point of depletion region is positioned at three's intersection of gate oxide 104, silicon substrate (or epitaxial loayer) 100, drift region 101.When intersection electric field reaches the avalanche breakdown critical electric field of silicon materials, device starts avalanche breakdown occurs, and now in whole depletion region, carries out the puncture voltage that integration just obtains device to electric field, Fig. 4 and Fig. 5 equals leg-of-mutton area.
For LDMOS device, high puncture voltage requires thick light dope epitaxial loayer, long drift region, low-doped drift region, and low conducting resistance then requires thin heavy doping epitaxial loayer, short drift region, highly doped drift region.Obviously, the low on-resistance of LDMOS device and high-breakdown-voltage are the technical indicators of a pair needs balance.In order to improve device withstand voltage, the doping content reducing drift region can be selected, and this can bring adverse effect to conducting resistance.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of LDMOS device with deep hole, can obtain higher puncture voltage on the one hand, can obtain lower conducting resistance on the other hand, thus improve the performance of device.
For solving the problems of the technologies described above, the LDMOS device that the application has deep hole has the drift region of the second doping type and the tagma of the first doping type in the silicon substrate or epitaxial loayer of the first doping type; There is cushion oxide layer and interstitital texture in drift region; There is gate oxide on silicon materials except cushion oxide layer and interstitital texture, on gate oxide partly and whole cushion oxide layer and whole interstitital textures, there is polysilicon gate;
Described interstitital texture is polycrystalline silicon material, and in vertical shape, in the vertical direction is divided into two parts; The top of Part I is passed through gate oxide and is connected with the bottom of polysilicon gate, the sidewall of Part I surround by gate oxide; The sidewall of Part II and bottom all surround by cushion oxide layer;
Described polysilicon gate is divided into two parts in the horizontal direction; Part I is separated by gate oxide directly over part tagma, and Part II is separated by gate oxide directly over part drift region; The Part II of polysilicon gate also directly over all interstitital textures, and is connected with the top of all interstitital textures.
The manufacture method that the application has the LDMOS device of deep hole comprises the steps:
1st step, injects the impurity of the second doping type in the silicon substrate or epitaxial loayer of the first doping type, forms drift region;
2nd step, injects the impurity of the first doping type in silicon substrate or epitaxial loayer, forms tagma;
3rd step, adopts photoetching and etching technics in drift region, etch shape and goes out multiple groove or hole;
4th step, adopts sidewall in described groove or hole of thermal oxide growth and/or chemical vapor deposition method and bottom to form cushion oxide layer, then adopts flatening process to be got rid of by the silica beyond groove;
5th step, adopts the silicon materials superficial growth beyond removing groove or hole, removing cushion oxide layer of thermal oxide growth technique to go out gate oxide;
6th step, first at whole wafer deposition one deck polysilicon, described groove or hole are filled completely, the polysilicon being arranged in groove or hole is interstitital texture; Photoetching and etching technics is adopted to etch to form polysilicon gate to this layer of polysilicon again; Finally adopt flatening process that the end face of polysilicon gate is become flat surfaces;
7th step, adopts photoetching and ion implantation technology in drift region and tagma, inject the impurity of the second doping type simultaneously, forms drain electrode and the source electrode of the second doping type respectively; Photoetching and ion implantation technology is adopted in tagma, also to inject the impurity of the first doping type to form draw-out area, tagma.
The LDMOS device of the application introduces deep trench or deep hole in drift region, in deep trench or deep hole, fill polysilicon, and these polysilicon interstitital textures are connected with grid, thus can introduce gate electric field in the inside of drift region.The extra electric field introduced can make drift region fully exhaust, and is conducive to the puncture voltage improving LDMOS device.Therefore, the doping content of drift region can be improved, while reduction puncture voltage, improve conducting resistance, obtain both balances, finally improve device performance.
Accompanying drawing explanation
Fig. 1 is a kind of cross-sectional view of existing LDMOS device;
Fig. 1 a is the one distortion of Fig. 1;
Fig. 2 is the cross-sectional view with the LDMOS device of deep hole of the application;
Fig. 2 a is the one distortion of Fig. 2;
Fig. 3 a ~ Fig. 3 f is each step generalized section with the manufacture method of the LDMOS device of deep hole of the application;
Fig. 4 is the Electric Field Distribution schematic diagram of device architecture shown in Fig. 1;
Fig. 5 is the Electric Field Distribution schematic diagram of device architecture shown in Fig. 1 a;
Fig. 6 is the Electric Field Distribution schematic diagram of device architecture shown in Fig. 2;
Fig. 7 is the Electric Field Distribution schematic diagram of device architecture shown in Fig. 2 a; .
Description of reference numerals in figure:
100 is silicon substrate or epitaxial loayer; 101 is drift region; 102 is tagma; 103 is isolation structure; 104 is gate oxide; 105 is grid; 106 is source electrode; 107 is drain electrode; 108 is draw-out area, tagma; 200 is groove or hole; 201 is cushion oxide layer; 202 is interstitital texture.
Embodiment
Refer to Fig. 2, this is the cross-sectional view with the LDMOS device of deep hole of the application.In p-type silicon substrate (or epitaxial loayer) 100, have N-shaped drift region 101 and p-type body district 102, both sides can contact with each other, and also can not contact.There is cushion oxide layer 201, interstitital texture 202 and N-shaped drain region 107 in drift region 101.Interstitital texture 202, in vertical column (if in hole) or vertical wall shape (if in the trench), is polycrystalline silicon material.Interstitital texture 202 in the vertical direction can be divided into two parts, the top of Part I is passed through gate oxide 104 and is connected with the bottom of polysilicon gate 105, the sidewall of Part I surround by gate oxide 104, the bottom of Part I is connected with the top of Part II; The sidewall of Part II and bottom all surround by cushion oxide layer 201.Strictly speaking, the horizontal sectional area of the Part I of interstitital texture 202 is slightly larger than the horizontal sectional area of Part II.In tagma 102, have N-shaped source region 106 and draw-out area, p-type body district 108, both sides can contact with each other, and also can not contact.Gate oxide 104 is had on silicon materials (comprising silicon substrate 100, drift region 101, tagma 102, source electrode 106, drain electrode 107, draw-out area, tagma 108) except cushion oxide layer 201 and interstitital texture 202.On gate oxide 104 partly and whole cushion oxide layer 201 and whole interstitital textures 202, there is polysilicon gate 105.This polysilicon gate 105 can be divided into two parts in the horizontal direction, Part I is separated by gate oxide 104 directly over part tagma 102, Part II is separated by gate oxide 104 directly over part drift region 101, and Part I is connected in the horizontal direction with Part II.The Part II of polysilicon gate 105 also directly over all interstitital textures 202, and is connected with the top of all interstitital textures 202.The doping type of the Each part of above-mentioned LDMOS device becomes on the contrary, is also feasible.
The structure of the LDMOS device shown in Fig. 2 can be deformed into shown in Fig. 2 a, and difference is only that N-shaped drift region 101 does not contact with the side in p-type body district 102, and centre has p-type silicon substrate (or epitaxial loayer) 100 to isolate.
Compared with existing LDMOS device, the application eliminates isolation structure, has increased the interstitital texture be connected with polysilicon gate newly.The electric field of polysilicon gate is incorporated into the darker inside of drift region downwards by described interstitital texture, thus drift region can be made fully to exhaust, and is conducive to bearing high pressure.Since the LDMOS device this with deep hole can obtain higher puncture voltage, so just suitably can improve the doping content of drift region, although can puncture voltage be reduced like this, but still higher than the puncture voltage of existing LDMOS device, and the conducting resistance lower than existing LDMOS device can be obtained.
Refer to Fig. 6 and Fig. 7, they show respectively the Electric Field Distribution of device architecture shown in Fig. 2 and Fig. 2 a.In fig. 2, because the polysilicon interstitital texture 202 in deep hole introduces the electric field of grid 105, thus form depletion region in drift region 101, and drift region 101 just can be made all to exhaust under lower than silicon materials avalanche critical field.When maximum electric field in depletion region is close to avalanche critical field, the voltage uniform between drain electrode 107 to tagma 102 is distributed in drift region 101, and depleted region electric field is trapezoidal profile.Under the condition that doping content is close, the area of whole trapezoid area much larger than the area of traditional structure intermediate cam shape, namely will can reach higher device electric breakdown strength under the condition of identical doping content.Fig. 2 a is similar with it.
The manufacture method with the LDMOS device of deep hole of the application comprises the steps:
1st step, refers to Fig. 3 a, implant n-type impurity in p-type silicon substrate (or epitaxial loayer) 100, forms N-shaped drift region 101.
2nd step, refers to Fig. 3 b, implanted with p-type impurity in p-type silicon substrate 100, forms p-type body district 102.This p-type body district 102 is as the channel region of LDMOS device.
This p-type body district 102 can contact with each other with the side of N-shaped drift region 101, thus forms a PN junction.
Or this p-type body district 102 also can not contact with the side of N-shaped drift region 101, because the doping content in p-type body district is much larger than p-type silicon substrate, thus this p-type body district 102 and N-shaped drift region 101 form PIN structural together with the p-type silicon substrate 100 of centre.
3rd step, refers to Fig. 3 c, adopts photoetching and etching technics to etch in drift region 101 and forms multiple groove 200.The bottom of these grooves 200 is all in drift region 101.These grooves 200 also can change hole into.Preferably, the degree of depth in groove or hole 200 is more than or equal to 3:1 with the ratio of width.
4th step, refer to Fig. 3 d, thermal oxide growth and/or chemical vapor deposition (CVD) technique is adopted to form cushion oxide layer 201 at the sidewall of groove 200 and bottom, now also can form silica on silicon substrate 100, drift region 101, surface, tagma 102, therefore also need to adopt cmp (CMP) and/or dry method the flatening process such as to anti-carve and the silica beyond groove 200 is got rid of.The thickness of cushion oxide layer 201 must bear maximum voltage difference between polysilicon interstitital texture 202 and drift region 101 and not breakdown.
5th step, refers to Fig. 3 e, adopts thermal oxide growth technique to go out gate oxide 104 in silicon substrate 100, drift region 101, tagma 102 superficial growth.
6th step, refers to Fig. 3 f, first at whole wafer deposition one deck polysilicon, is not only filled completely by groove 200, but also cover certain thickness on whole silicon chip.The polysilicon being arranged in groove 200 is interstitital texture 202.Photoetching and etching technics is adopted to etch to form polysilicon gate 105 to this layer of polysilicon again.This polysilicon gate 105 is divided into two parts in the horizontal direction, and Part I is separated by gate oxide 104 directly over part tagma 102, and Part II is separated by gate oxide 104 directly over part drift region 101.The Part II of polysilicon gate 105 also covers directly over all grooves 200, and is connected with the top of the interstitital texture 202 in all grooves 200.Due to the existence of groove 200, make the end face of polysilicon gate 500 may and uneven, therefore also need employing cmp and/or dry method the flatening process such as to anti-carve and the end face of polysilicon gate 500 become flat surfaces.
7th step, refers to Fig. 2, and implant n-type impurity while of adopting photoetching and ion implantation technology in drift region 101 and tagma 102, forms N-shaped drain electrode 107 and N-shaped source electrode 106 respectively in drift region 101 and tagma 102.Photoetching and ion implantation technology is adopted in tagma 102, to go back implanted with p-type impurity to form draw-out area, p-type body district 108.In this step, the order of N-shaped ion implantation, p-type ion implantation can be exchanged.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.

Claims (8)

1. there is a LDMOS device for deep hole, there is the drift region of the second doping type and the tagma of the first doping type in the silicon substrate or epitaxial loayer of the first doping type; It is characterized in that there is cushion oxide layer and interstitital texture in drift region; There is gate oxide on silicon materials except cushion oxide layer and interstitital texture, on gate oxide partly and whole cushion oxide layer and whole interstitital textures, there is polysilicon gate;
Described interstitital texture is polycrystalline silicon material, and in vertical shape, in the vertical direction is divided into two parts; The top of Part I is passed through gate oxide and is connected with the bottom of polysilicon gate, the sidewall of Part I surround by gate oxide; The sidewall of Part II and bottom all surround by cushion oxide layer;
Described polysilicon gate is divided into two parts in the horizontal direction; Part I is separated by gate oxide directly over part tagma, and Part II is separated by gate oxide directly over part drift region; The Part II of polysilicon gate also directly over all interstitital textures, and is connected with the top of all interstitital textures.
2. the LDMOS device with deep hole according to claim 1, is characterized in that, the horizontal sectional area of the Part I of described interstitital texture is greater than the horizontal sectional area of Part II.
3. the LDMOS device with deep hole according to claim 1, is characterized in that, the tagma of described first doping type contacts with the side of the drift region of the second doping type, forms PN junction;
Or the tagma of described first doping type does not contact with the side of the drift region of the second doping type, form PIN structural together with silicon substrate between the two or epitaxial loayer.
4. there is a manufacture method for the LDMOS device of deep hole, it is characterized in that, comprise the steps:
1st step, injects the impurity of the second doping type in the silicon substrate or epitaxial loayer of the first doping type, forms drift region;
2nd step, injects the impurity of the first doping type in silicon substrate or epitaxial loayer, forms tagma;
3rd step, adopts photoetching and etching technics in drift region, etch shape and goes out multiple groove or hole;
4th step, adopts sidewall in described groove or hole of thermal oxide growth and/or chemical vapor deposition method and bottom to form cushion oxide layer, then adopts flatening process to be got rid of by the silica beyond groove or hole;
5th step, adopts the silicon materials superficial growth beyond removing groove or hole, removing cushion oxide layer of thermal oxide growth technique to go out gate oxide;
6th step, first at whole wafer deposition one deck polysilicon, described groove or hole are filled completely, the polysilicon being arranged in groove or hole is interstitital texture; Photoetching and etching technics is adopted to etch to form polysilicon gate to this layer of polysilicon again; Finally adopt flatening process that the end face of polysilicon gate is become flat surfaces;
7th step, adopts photoetching and ion implantation technology in drift region and tagma, inject the impurity of the second doping type simultaneously, forms drain electrode and the source electrode of the second doping type respectively; Photoetching and ion implantation technology is adopted in tagma, also to inject the impurity of the first doping type to form draw-out area, tagma.
5. the manufacture method with the LDMOS device of deep hole according to claim 4, is characterized in that, in described method the 2nd step, the side of tagma and drift region contacts with each other, and forms a PN junction;
Or tagma does not contact with the side of drift region, and form PIN structural with both middle silicon substrates or epitaxial loayer.
6. the manufacture method with the LDMOS device of deep hole according to claim 4, is characterized in that, in described method the 3rd step, the degree of depth in groove or hole is more than or equal to 3:1 with the ratio of width.
7. the manufacture method with the LDMOS device of deep hole according to claim 4, is characterized in that, in described method the 4th step, the thickness of cushion oxide layer wants the maximum voltage difference that can bear between polysilicon interstitital texture and drift region and not breakdown.
8. the manufacture method with the LDMOS device of deep hole according to claim 4, is characterized in that, in described method the 7th step, the order of N-shaped ion implantation, p-type ion implantation is exchanged.
CN201310675662.4A 2013-12-11 2013-12-11 LDMOS device with deep hole and manufacturing method thereof Pending CN104716179A (en)

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