CN104639176B - The asynchronous decoder and method of BMC signals - Google Patents
The asynchronous decoder and method of BMC signals Download PDFInfo
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- CN104639176B CN104639176B CN201310552559.0A CN201310552559A CN104639176B CN 104639176 B CN104639176 B CN 104639176B CN 201310552559 A CN201310552559 A CN 201310552559A CN 104639176 B CN104639176 B CN 104639176B
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Abstract
The invention discloses a kind of asynchronous decoder of BMC signals, including：One deburring circuit, phase hit detection circuit, a level counter, a register and adaptive logic circuit, a decision logic circuit.The edge of phase hit detection electric circuit inspection BMC signal phase changes, and the renewal point using the edge of the phase place change as the determination point of data, the reduction point of level counter and half bit sampling point number.Level counter is used to record the sampling point number of each level, and judge to receive by the magnitude relationship of comparative level counter and half bit sampling point number at the determination point of data is 0 or 1, and half bit sampling point number is obtained by adaptive logic circuit.The invention also discloses a kind of asynchronous decoding method of BMC signals.The present invention can improve the asynchronous decoder receptivity of BMC signals, avoid receiving corrupt data.
Description
Technical field
The present invention relates to a kind of asynchronous decoder of BMC (two-phase label coding) signal.The invention further relates to a kind of BMC letters
Number asynchronous decoding method.
Background technology
BMC Signal codings waveform is to mix clock and data as shown in figure 1, belong to a kind of coding method of phase-modulation
It is combined the coding method of transmission；Its principle is to use the clock frequency of a twice transmission bit rate as benchmark,
Originally a bit data splits into two parts, in current potential (1- of this intermediate change when data are 1>0 or 0->1) become
Into 10 or 01, do not change current potential then when data are 0, become 11 or 00.Simultaneously each beginning level with it is previous
The level of individual position ending however it is same, such receiving terminal could judge the border of each position.Using BMC coding can allow transmission end with
Receiving terminal only needs a data line can that data are correctly transmitted and received, and keeps synchronous well receiving both ends
Property.
The asynchronous decoder of existing BMC signals performance in the case where reception signal is jagged is bad, easily causes and connects
Receive corrupt data.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of asynchronous decoder of BMC signals, its receptivity can be improved,
Avoid receiving corrupt data；Therefore, the present invention also provides a kind of asynchronous decoding method of BMC signals.
In order to solve the above technical problems, the asynchronous decoder of the BMC signals of the present invention, including：
One deburring circuit, for removing the burr in BMC signals；
One phase hit detects circuit, is connected with the deburring circuit, for detecting the side of BMC signal phases change
Edge, and using the edge of the phase place change as the determination point of data, the reduction point of level counter and half bit sampling point number
Renewal point；
One level counter, it is connected with phase hit detection circuit, for remembering BMC signal level length；
One register and adaptive logic circuit, it is connected with the level counter, its adaptive logic circuit uses
Adaptive mode obtains half bit sampling point number；Its register is used to preserve the half bit sampling point number；
One decision logic circuit, detect circuit, level counter and register with the phase hit and adaptively patrol
Collect circuit to be connected, in the determination point of each data, count value and the deposit of half bit sampling point number to the level counter
The half bit sampling point number preserved in device is compared；It is 0 or 1 to adjudicate the data received；
The deburring circuit, 3 bats are adopted to the BMC signals of input using clock signal, compare the 2nd bat and the 3rd clap it is defeated
Go out it is whether equal, if equal using the 3rd clap output as new output, otherwise keep initial value.
The asynchronous decoding method of the BMC signals adopts the following technical scheme that realization：
Using clock of the frequency much larger than BMC signal bit rates as clock signal, remembered with a level counter
Record the clock signal number counted in the low level or high level of the BMC signals received；In the reduction point of level counter,
It will be counted again after the level counter clear 0；
The sampled point number that BMC signal half-bit width is recorded with a register is half bit sampling point number, hereafter
In the determination point of each data, to the value of the level counter compared with half bit sampling point number, if level counts
The value of device is that then to be received between 1.5 times~2.5 times of half bit sampling point number is 0, if the value of level counter be
Then represent to receive between 0.75 times~1.5 times of half bit sampling point number is 1；
The half bit sampling point number is obtained using adaptive mode, and method is：
The register reset defaults for recording half bit sampling point number are set to 0, later in each half bit sampling point number
Renewal point by the value of the level counter compared with the value of register；If the value of level counter is less than register
Value or 4 times of the value more than register, then the value of register is modernized into current Counter Value, otherwise the value of register
Keep initial value；After multiple bits, then the actual samples point number of half-bit width is obtained.
The asynchronous clock signal for referring to decoding circuit is not necessarily homologous clock with the BMC signals received and produced
Raw.
The present invention is demodulated using high speed sampling clock to BMC signals, and the asynchronous decoder for improving BMC signals receives
Data performance, it can avoid receiving corrupt data in the case where reception signal is jagged, and with adaptively soon, decoding is accurate
The advantages of true.
Brief description of the drawings
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is BMC signal waveform schematic diagrames；
Fig. 2 is the asynchronous decoder structured flowchart of the BMC signals.
Embodiment
The realization principle of the asynchronous decoder of the BMC signals is as follows with reference to shown in Fig. 2：
Much larger than the clock of BMC signal bit rates as sampling clock it is clock signal clk using a frequency, with one
The clock signal number counted in the low level or high level of the BMC signals that level counter record is receiving.In level meter
The reduction point of number device, will be counted again after the level counter clear 0.
Sampled point number (the hereinafter referred to as half bit sampling point of BMC signal half-bit width is recorded with a register
Number).Hereafter in the determination point of each data, by the value of level counter compared with half bit sampling point number, if electric
The value of flat counter is that then to be received between 1.5 times~2.5 times of half bit sampling point number is 0, if level counter
Value is then to represent that receive is 1 between 0.75 times~1.5 times of half bit sampling point number.Because the phase hit of data 1 occurs
Among the bit (bit), the phase hit of data 0 occurs at bit ends, therefore the determination point of visual data 1 is among bit, data 0
Determination point bit end.
As long as therefore obtain half bit sampling point number, it is possible to which be easy to judge to receive is 1 or 0.Next
The adaptive principle of half bit sampling point number is described.
The register reset defaults of half bit sampling point number of record are set to 0 first, later in each half bit sampling point
Number updates value of the point counter compared with the value of register.If the value of counter be less than register value or
More than 4 times of the value of register, then the value of register is modernized into current Counter Value, otherwise the value of register keeps former
Value.In this way after several bit, it is possible to obtain the actual samples point number of half-bit width.
It is assumed that electricity begins to count on level counter one, the time for starting transmission due to BMC signals does not know, because of system
It is and different.Therefore when the edge of first phase place change of BMC signals arrives, the numerical value of level counter be it is uncertain, can be with
It is divided into following 4 kinds of situations：
(1) it is less than or equal to the 1/2 of half bit sampling point number.
(2) it is more than the 1/2 of half bit sampling point number and is less than or equal to half bit sampling point number.
(3) it is more than half bit sampling point number and is less than whole bit sampling point number.
(4) it is more than whole bit sampling point number.
First due to half bit sampling point number makes value be 0, therefore at the edge of the 1st phase place change, level counter
Count value is certain to update in register.It is also the above 4 namely in the value of the edge late register of first phase place change
One kind in kind situation.
Follow-up adaptive process is analyzed as follows：
For (1) in this case, first have to after receiving a data 0, the value of register can update whole ratio
Special actual sampling point number；It will update to half bit is actual and adopt behind the edge for waiting until to receive the phase place change of a data 1 again
Sampling point number；It will not subsequently update again.
For (2), (3) and (4) in the case of these three, be all etc. the phase place change for receiving a data 1 edge after
It will update to half bit actual samples point number；It will not subsequently update again.
Therefore as long as this BMC signals demodulation method after each and every one more bits can carried out just to 1 and 0
Really judgement.And typically it can all provide training sequence, therefore the demodulation side when communicating incipient using the agreement of BMC communications
Method is very simple and effective.
Because this demodulation mode can use high speed sampling clock, decoded in error, BMC are prevented in order to eliminate the influence of burr
Signal one comes in need to be demodulated again after carrying out deburring processing using the i.e. clock signal clk of high speed sampling clock.
It is shown in Figure 2, in the embodiment shown in Figure 2, the asynchronous decoder of the BMC signals, including：One deburring
Circuit, phase hit detection circuit, a level counter, a register and adaptive logic circuit, a decision logic
Circuit.
The asynchronous decoder of the BMC signals has 3 input signals：
1st, clock signal clk；
2nd, reset signal rstn；
3rd, BMC signals decode_in；
The asynchronous decoder of the BMC signals has 1 output signal：Solve code value decode_out.
The deburring circuit, 3 bats are adopted to the BMC signals of input using clock signal clk, compare what the 2nd bat was clapped with the 3rd
Whether output is equal, otherwise the output clapped if equal using the 3rd keeps initial value as new output.The deburring circuit energy
The burr that length is less than in the BMC signals in 1 clock signal clk cycle is enough removed, is then input to phase hit detection circuit.
The phase hit detects circuit, is connected with the deburring circuit, for the output of deburring circuit to be believed
Number adopt 1 bat and export using clock signal clk, the output signal of the phase hit detection circuit and deburring circuit
Whether output signal is equal, produces phase hit indication signal, and 1 is exported if unequal and indicates phase hit, otherwise exports 0
Represent no phase hit.
The level counter, it is connected with phase hit detection circuit, for remembering BMC signal level length, i.e.,
Clk number of clock signal counted in BMC signals decode_in low level or high level, in BMC signal decode_in phases
Position hopping edge clear 0.There is one to be counted with door as level because the level counter is simultaneously also by rstn clear 0, therefore in Fig. 2
The asynchronous reset generation circuit of device, for reset signal rstn and phase hit indication signal inverted value phase and being processed into one
Individual signal is then sent through the reset terminal of level counter.
The register and adaptive logic circuit, are connected with the level counter, and its adaptive logic circuit is adopted
Half bit sampling point number is obtained with the mode of adaptation；Its register is used to preserve the half bit sampling point number.
Because BMC signal waveforms are all using half bit as least unit, data 0 are two double-lengths of half bit, and data 1 are by 2
Individual half bit composition, as long as therefore judging the big of the value of current level counter and half bit sampling point number in the determination point of data
It is 0 or 1 that small relation can, which rules out be currently received,.0 judgement is last in bit, and 1 judgement is among bit.Such as half
Bit sampling point number only needs several bit cans to complete adaptive process, accurately demodulation by way of hardware self-adapting
Go out data.
The decision logic circuit, with phase hit detection circuit, level counter and register and adaptively
Logic circuit is connected, and in the determination point of data, value and half bit sampling point number to the level counter are compared；Such as
The value of level counter described in fruit is that then to be received between 1.5 times~2.5 times of half bit sampling point number is 0, if described
The value of level counter is then to represent that receive is 1 between 0.75 times~1.5 times of half bit sampling point number.
The present invention is described in detail above by embodiment, but these are not formed to the present invention's
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (7)
- A kind of 1. asynchronous decoder of BMC signals, it is characterised in that including：One deburring circuit, for removing the burr in BMC signals；One phase hit detects circuit, is connected with the deburring circuit, for detecting the edge of BMC signal phases change, And using the edge of the phase place change as the determination point of data, the reduction point of level counter and half bit sampling point number more New point；One level counter, it is connected with phase hit detection circuit, for remembering BMC signal level length；One register and adaptive logic circuit, it is connected with the level counter, its adaptive logic circuit is using adaptive The mode answered obtains half bit sampling point number；Its register is used to preserve the half bit sampling point number；One decision logic circuit, with phase hit detection circuit, level counter and register and adaptive logic electricity Road is connected, the half bit sample preserved in the determination point of each data, the count value and register to the level counter Point number is compared；It is 0 or 1 to adjudicate the data received；The deburring circuit, 3 bats are adopted to the BMC signals of input using clock signal, comparing the 2nd bat and the 3rd output clapped is No equal, otherwise the output clapped if equal using the 3rd keeps initial value as new output.
- 2. asynchronous decoder as claimed in claim 1, it is characterised in that：The phase hit detects circuit, for unhairing The output signal of thorn circuit is adopted 1 bat using clock signal and exported, the output signal of phase hit detection circuit with Whether the output signal of deburring circuit is equal, phase hit is indicated if unequal, otherwise without phase hit.
- 3. asynchronous decoder as claimed in claim 1, it is characterised in that：The level counter remembers BMC signal level length, It is the clock signal number counted in the low level of BMC signals or high level, in the reduction point of level counter clear 0.
- 4. asynchronous decoder as claimed in claim 1, it is characterised in that：The adaptive logic circuit uses adaptive side The mode that formula obtains half bit sampling point number is：The register reset defaults are set to 0, later in each half bit sampling point The renewal point of number is by the value of the level counter compared with the value of register；Posted if the value of level counter is less than The value of storage or 4 times of the value more than register, then be modernized into the value of register current Counter Value, otherwise register Value keep initial value；After multiple bits, then the actual samples point number of half-bit width, i.e. half bit sampling point are obtained Number.
- 5. asynchronous decoder as claimed in claim 1, it is characterised in that：The decision logic circuit adjudicates the data received The foundation of " 0 " still " 1 " is, if the value of the level counter is between 1.5 times~2.5 times of half bit sampling point number What is received is 0, represents to receive if the value of the level counter is between 0.75 times~1.5 times of half bit sampling point number Be 1.
- A kind of 6. asynchronous decoding method of BMC signals, it is characterised in that：Using clock of the frequency much larger than BMC signal bit rates as clock signal, recorded just with a level counter The clock signal number counted in the low level of the BMC signals of reception or high level；In the reduction point of level counter, by this Counted again after level counter clear 0；The sampled point number that BMC signal half-bit width is recorded with a register is half bit sampling point number, hereafter every The determination point of individual data, to the value of the level counter compared with half bit sampling point number, if level counter Value is that then to be received between 1.5 times~2.5 times of half bit sampling point number is 0, if the value of level counter is compared half Then represent to receive between 0.75 times of special sampling point number~1.5 times is 1；The half bit sampling point number is obtained using adaptive mode, and method is：The register reset defaults for recording half bit sampling point number are set to 0, later number in each half bit sampling point more New point is by the value of the level counter compared with the value of register；If the value of level counter is less than the value of register Or 4 times of the value more than register, then the value of register is modernized into current Counter Value, otherwise the value of register is kept Initial value；After multiple bits, then the actual samples point number of half-bit width is obtained.
- 7. method as claimed in claim 6, it is characterised in that：It is characterized in that：Before carrying out asynchronous decoding to BMC signals, adopt The burr in BMC signals is removed with the following method；3 bats are adopted to the BMC signals of input using the clock signal, compare the 2nd bat Whether equal with the 3rd output clapped, otherwise the output clapped if equal using the 3rd keeps initial value as new output.
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| CN107515836B (en) * | 2017-09-21 | 2023-12-22 | 四川易冲科技有限公司 | BMC decoding device and method with dynamic double thresholds |
| CN108551433A (en) * | 2018-06-27 | 2018-09-18 | 珠海市微半导体有限公司 | The decoding system and coding/decoding method of BMC codes |
| CN110647483A (en) * | 2019-08-02 | 2020-01-03 | 福州瑞芯微电子股份有限公司 | BMC code asynchronous receiving method suitable for USB-PD protocol and storage device |
| CN114117972B (en) * | 2022-01-26 | 2022-06-10 | 之江实验室 | Synchronous device and method of asynchronous circuit |
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