CN104601317A - Synchronous clock device of FPGA and control method thereof - Google Patents
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Abstract
The invention provides a synchronous clock device of FPGA and a control method thereof. The synchronous clock device comprises a time source unit, an interior clock unit, a signal output unit and a multi-time source sliding step switching unit; and the time source unit comprises a reference source selection module, the reference source selection module selects the best time source according to the preset method and outputs to the multi-time source sliding step switching unit; an interior time unit offering the reference time signal for the reference source selection module of the time source unit and offering the pulse signal for the signal output unit and multi-time source sliding step switching unit; the multi-time source sliding step switching unit timely collects the signal outputted to the signal output unit during the time source signal transmission process and/or during the switching process of different time sources. The best time source can be automatically selected and the time source signal can be updated for the output unit through the collection module during the time source signal transmission process and/or during the switching process of different time sources.
Description
Technical field
The present invention relates to Synchronization Clock and the control method thereof of a kind of FPGA, particularly relating to is Synchronization Clock and the control method thereof of monolithic FPGA.
Background technology
Along with the development of power automation technology, in the requirement when requirement of Synchronization Clock has not only been rested on pair in precision, require that it has better stability simultaneously.Further raising requirement, Synchronization Clock should possess manageability.Stability is mainly reflected in the source switching of many times and keeps time in precision, generally, requires to approach its adjusted value gradually, slip stepping 0.2 μ s/s when many times, source switched; Require punctual 12 hours continuously, punctual precision is better than 1 μ s/h.
Relevant Synchronization Clock technology is disclosed in prior art, such as CN102540902A discloses a kind of single platform multi-sensor information integration processor and experimental system, it discloses a kind of single platform multi-sensor information integration processor and experimental system, single platform multi-sensor information integration processor comprises communication module, control module, use processing module and power module.Experimental system comprises single platform multi-sensor information integration processor equipment and a computer, is connected between the two, completes the mutual of data by USB data line.The present invention can simulate the terminal guidance process of multiple control and guide ammunition, comprise the target seeker minor loop of the terminal guidance be made up of digital guiding head servo system and the multi-sensor information integration processor of computer and combine by the missile-borne of computer guided missile that control computer and multi-sensor information integration processor form and target relative movement controls large loop, real-time emulation can be carried out to the algorithm of use processing, and Real time displaying can be carried out by computer to result.CN102593955B discloses a kind of comprehensive intelligent time frequency test macro and method of testing, and its system comprises GPS/ Beidou antenna receiver, be provided with database and the supervisor of testing results analysis management program and realize program control time and frequency standard source and timing pulse, standard frequency, IRIG-B code, NTP/SNTP message, PTP message testing equipment respectively by communication link connection management machine.Be provided with Intelligent time frequency signal switcher, the program control of supervisor is realized by test analysis hypervisor, carries out program control switching respectively by Intelligent time frequency signal switcher, tests for comprehensive intelligent time frequency.Can when need not manual intervention, easy and effectively to tested time synchronism equipment carry out effective intelligent comprehensive test, the intellectuality of practical raising time synchronism equipment complicated business function and performance test, standardization, systematization level, test performance is more accurate, testing efficiency is higher, and the testing time shortens greatly.CN203416271U discloses source optimal time synchronizer of a kind of many times, and it comprises the identical unit of at least two structures, and in each unit, global positioning system ground receiver is connected with counter, and counter also connects the comparator in this unit; Directly be connected between high stability crystal oscillator with the counter in each unit or connected by phaselocking frequency multiplier; In each unit, comparator accesses an input of MUX respectively; Counter in each unit, comparator are connected with single-chip microcomputer respectively with register; The output of single-chip microcomputer is also connected with MUX.There is integrated cost lower, algorithm strong adaptability, support the mutually standby optimizing of multipath clock source, supports multiple time difference compensation strategy, can realize high-precision punctual, and the feature such as time signal stable output is reliable.
But above-mentioned technology clock not up to standard in stability, its core component also cannot use programmable single-chip microcomputer.
Summary of the invention
Inventor is realizing finding in process of the present invention, above-mentioned disclosed patent document does not all relate to source sliding steps switching device shifter and the description of operational mode thereof of many times, can better not realize the source switching of many times to realize stability, above-mentioned disclosed patent document does not all possess log query device to realize manageability in addition.
In order to solve the problems of the technologies described above, the invention provides the Synchronization Clock of a kind of FPGA, it is characterized in that, comprising: time source unit, internal clock unit, signal output unit and Duo Shi source sliding steps switch unit; And source unit comprises three very first time sources in parallel, the second time source and the 3rd time source time described, described three time sources in parallel and reference source select model calling, described reference source selects model calling according to the time source of predetermined method choice the best, and exports source sliding steps switch unit of many times to; Described internal clock unit, can for source unit time described reference source select module reference time signal is provided, and can for described signal output unit and described many times source sliding steps switch unit pulse signal is provided; In described many times, sliding steps switch unit in source comprised correction module, and can signal be exported to described signal output unit, the pulse signal that described correction module provides according to the time source selecting module to provide from reference source and described internal clock unit compares, time source signal transmittance process in and/or different time source switches time, correct the signal exporting signal output unit in time.Automatically can select best time source like this, and time source signal transmittance process in and/or different time source switches time, can upgrade by correction module the time source signal that output unit needs constantly.
Preferably, described many times source sliding steps switch unit also comprise time difference comparison module, described time difference comparison module comprises pulse per second (PPS) comparator and time comparator; And input to many times source sliding steps switch units first after described time difference comparison module, then input to described correction module.Accurately can calculate the difference of time signal and internal reference time like this.
Preferably, described many times source sliding steps switch unit also comprise filtering module, described filtering module comprises fused filtering device and Color seperation grating device; And the signal of described correction module is after described filtering module, just export described signal output unit to.Advanced and/or the lag issues of signal can be adjusted in handoff procedure in time like this by correction module.
Preferably, time described, source unit also comprises three formation-decoding module of connecting with described very first time source, the second time source and the 3rd time source respectively.Time source can be allowed like this to transmit with a kind of more stable signal form.
Preferably, described very first time source is satellite-signal, and described second time source is the IRIG-B signal of Hot Spare synchronised clock, and described 3rd time source is local IRIG-B coded signal.These time sources, can allow the Synchronization Clock of FPGA can select the time signal of plurality of stable.
Preferably, after the parallel connection of described three decoder modules difference, then select model calling with described reference source, and described reference source selects module to comprise, and mode bit judges submodule, priority judges submodule and Duo Shi source judges submodule.These can allow reference source select the result of module more intelligent from module.
Preferably, times frequency module and filtering module is provided with in described internal clock unit.Can obtain high-precision reference time and reference pulse like this, and signal is more stable.
Preferably, the Synchronization Clock of described FPGA, also comprises log unit, and is provided with message output module in described signal output unit, and described message output module exports the information of described signal output unit to log unit.
Preferably, time described, the signal of source unit and the signal of described internal clock unit also all can input to described log unit.
Adopt log unit, like this can the operation conditions of recording synchronism clock apparatus in the past in a period of time objectively, help custodian better to manage Synchronization Clock.
The present invention also provides a kind of control method of FPGA Synchronization Clock in addition, and the method comprises: source unit and Duo Shi source sliding steps switch unit when the signal of internal clock unit inputs to by A.; Source signal when B. selecting best one in source signal when multiple; C. the time source signal and the difference of internal clock unit signal selected in set-up procedure B in described many times source sliding steps switch units, the pulse value of source signal when adjustment is described automatically; D. the pulse of source signal when described signal output unit corrects described, then successively through IRIG-B code generator and IRIG-B code transmitter, is sent to receiving system by IRIG-B code.
Adopt preferred embodiment above-mentioned, in time source handoff procedure, refusal sudden change, ensures gentle transition, improves the stability of Synchronization Clock.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that embodiment one relates to the Synchronization Clock of a kind of FPGA.
Fig. 2 is the structured flowchart of internal clock unit in Fig. 1.
Fig. 3 be in Fig. 1 many times source sliding steps switch unit structured flowchart.
Fig. 4 is the structured flowchart of signal output unit in Fig. 1.
Fig. 5 is the flow chart that embodiment one relates to the Synchronization Clock control method of a kind of FPGA.
Fig. 6 is the structured flowchart of embodiment two source unit when relating in the Synchronization Clock of a kind of FPGA.
Fig. 7 is the structured flowchart that embodiment three relates to the Synchronization Clock of a kind of FPGA.
Fig. 8 is the structured flowchart of log unit in Fig. 7.
Fig. 9 is the structured flowchart that Fig. 7 plants message signals output module.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail, it should be noted that, these specific descriptions just allow those of ordinary skill in the art be more prone to, clearly understand the present invention, but not limitation of the invention is explained.
Embodiment one
As shown in Figure 1, the present embodiment preferably provides a kind of FPGA Synchronization Clock of (abbreviation of field programmable gate array), comprising: time source unit 1, internal clock unit 2, signal output unit 3 and Duo Shi source sliding steps switch unit 4; And time source unit comprise three very first time source 11, second time sources 12 in parallel and the 3rd time source 13, three time sources in parallel select module 14 to be connected with reference source, reference source selects module 14 to connect time source according to predetermined method choice the best, and exports source sliding steps switch unit 4 of many times to; Wherein, internal clock unit 2, can for time source unit 1 reference source select module 14 to provide reference time signal, and pulse signal can be provided for signal output unit 3 and Duo Shi source sliding steps switch unit 4; In many times, sliding steps switch unit in source 4 comprised correction module, and can signal be exported to signal output unit, the pulse signal that correction module provides according to the time source selecting module to provide from reference source and internal clock unit compares, time source signal transmittance process in and/or different time source switches time, correct the signal exporting signal output unit in time.Automatically can select best time source like this, and time source signal transmittance process in and/or different time source switches time, can upgrade by correction module the time source signal that output unit needs constantly.
As shown in table 1 below, reference source select module 14 select Best Times source according to being, in " the source judgement of many times " module, for foundation with the multi-source decision logic in source time independent, in the present embodiment, clock correction threshold values for being preferably 20 μ s, source and following inner RTC (abbreviation of internal clock signal) when wherein clock correction threshold value refers to outside.
Table 1. reference source selects module 14 to select the foundation table in Best Times source
As shown in Figure 2, times frequency module 21 and filtering module (not shown) is provided with in internal clock unit 2; Can obtain high-precision reference time and reference pulse like this, and signal is more stable.Particularly, internal clock unit utilizes OCXO (Oven Controlled Crystal Oscillator, constant-temperature crystal oscillator, it is the temperature remained constant utilizing thermostat to make crystal oscillator or quartz-crystal unit, minimum crystal oscillator is cut to by changing by environment temperature the oscillator output frequencies variable quantity caused) clock signal that produces, through times frequency module 21, export high-speed clock signal, high-speed clock signal is that the high-speed cruising of dispensing device and the temporal resolution of nanosecond provide guarantee; Through times frequency module 21 produce time threshold values through impulse phase comparator 22, RTC clock 23 and clock correction threshold value 24 for time source unit 1 reference time and clock correction threshold time are provided; The time threshold values simultaneously produced through times frequency module 21 also can through divide ratio module 25, calculate divided signal, and be stored to memory cell, through the pps pulse per second signal 26 that divide ratio module 25 obtains, the coefficient that device sum counter stores frequently also can provide reference for signal output unit 3 and Duo Shi source sliding steps switch unit 4 respectively.
Preferably, the present embodiment exports 10Mhz clock with OCXO, and through " frequency multiplication " module, (a kind of chip applying FPGA technology, this chip adopts the 60-nm low-power consumption technique through optimizing to application EP4CE15, has very large advantage in power consumption.) in integrated phase locked looped function, ten frequencys multiplication are carried out to OCXO, generate the clock of 100Mhz.
As shown in Figure 3, above-mentioned many times source sliding steps switch unit 4 also comprise time difference comparison module 41, time difference comparison module 41 comprises pulse per second (PPS) comparator 42 and time comparator 43; And input to many times source sliding steps switch units 4 first after time difference comparison module 41, then input to correction module, so just accurately can calculate the difference of time signal and internal reference time.Preferably, correction module is provided with divide ratio adjustment submodule 44, the advanced adder 45 of phase place and delayed phase subtracter 46, and the result that can calculate according to time difference comparison module 41 like this adjusts the impulse ratio needing to correct automatically.Preferably, many times source sliding steps switch unit also comprise filtering module, filtering module comprises fused filtering device 47 and Color seperation grating device 48, pulse output unit 49; And the signal of correction module is after filtering module, just exports signal output unit to.Advanced and/or the lag issues of signal can be adjusted in handoff procedure in time like this by correction module.
As shown in Figure 5, preferably, output of pulse signal module 31 module produce pulse per second (PPS), point pulse, time pulse." output of pulse signal " module is first by pulse per second (PPS) divide ratio that " divide ratio reading " module reading system calculates; The time of delay needing to compensate is calculated through " receive delay modulator " module; Calculate divide ratio by " divide ratio adjustment " module, then pass through " pulse counter " module, so far pulse per second (PPS) just creates.Divide pulse to be trigger " point pulse counter " module with pulse per second (PPS), counting often reaches the generation of certain number of times and once divides pulse.Time the generation of pulse and point pulse similar, by a point pulse-triggered " time pulse counter " module, counting reaches pulse when certain number of times produces a time.IRIG-B coded signal output module 32 exports IRIG-B, and (IRIG time standard has two large classes: a class is parallel time code form, and this kind of code is owing to being parallel form, and transmission range is comparatively near, and is binary system, therefore can not show a candle to serial form extensive; Another kind of is serial time code, has six kinds of forms, i.e. A, B, D, E, G, H; Their essential difference is the frame rate difference of timing code, and IRIG-B is Type B code wherein) signal.First by the date Hour Minute Second information in " date Hour Minute Second " module reading system, then " stipulations organizer " format editing message content according to agreement is entered, " stipulations generator " afterwards by being produced by " IRIG-B code clock generator " module compiles IRIG-B code rule schemata, sends IRIG-B coded signal to receiving system.
As shown in Figure 5, in the present embodiment, preferably, also provide a kind of control method of FPGA Synchronization Clock, the method comprises:
S1. reference signal is obtained from internal clock unit: source unit and Duo Shi source sliding steps switch unit when being inputed to by the signal of internal clock unit;
Source when S2. selecting: source signal when selecting best in source signal when multiple;
S3. timing source signal: the time source signal and the difference of internal clock unit signal selected in set-up procedure B in described many times source sliding steps switch units, the pulse value of source signal when adjustment is described automatically;
S4. IRIG-B code is exported: the pulse of source signal when described signal output unit corrects described, then successively through IRIG-B code generator and IRIG-B code transmitter, is sent to receiving system by IRIG-B code.
Adopt the optimal technical scheme in the present embodiment, in time source handoff procedure, refusal sudden change, ensures gentle transition, improves the stability of Synchronization Clock.
Embodiment two
The technical scheme that embodiment two adopts is identical with embodiment one or substantially identical, for identical or substantially identical part, at this not in repeat specification.Difference is the setting of time source, specific as follows:
As shown in Figure 6, preferably, time, source unit 1 also comprises three formation-decoding module 15,16,17 of connecting with described very first time source 11, second time source 12 and the 3rd time source 13 respectively.Time source can be allowed like this to transmit with a kind of more stable signal form.When very first time source 11 is satellite-signal, and be that the Big Dipper is using a Big Dipper generation, GPS as time source, second time source 12 is the IRIG-B signal of Hot Spare synchronised clock, when 3rd time source 13 is local IRIG-B coded signal, the decoding device of satellite-signal can obtain respectively the state information of this time source signal, the time below second, second and second above information etc.; And Hot Spare clock output signal and local IRIG-B code information can obtain similar time, state information.And after the parallel connection of three decoder module 15,16,17 difference, module 14 is selected to be connected with described reference source again, and reference source selects module to comprise, and mode bit judges submodule, priority judges submodule and Duo Shi source judges submodule, table 1 such as in conjunction with the embodiments in one and the Fig. 6 in the present embodiment, when the effective criterion of satellite is, receipts star number is greater than three, positional information is stable, satellite antenna is normal; IRIG-B signal (being called for short IB1) the effective criterion of Hot Spare synchronised clock is that temporal quality is less than or equal to 4; Local IRIG-B code information (being called for short IB2) effective criterion is that temporal quality is less than or equal to 4.Judge in priority " in block, under equal conditions, time source priority be followed successively by from high to low: the IRIG-B signal of satellite-signal, Hot Spare synchronised clock, local IRIG-B code information.。This is a little can allow reference source select the result of module more intelligent from module.
Embodiment three
Execute technical scheme and embodiment one that example three adopts, embodiment two is identical or cardinal principle is identical, for identical or substantially identical part (time source unit, internal clock unit and Duo Shi source sliding steps switch unit in such as embodiment one, time source unit in embodiment two), at this not in repeat specification.Difference is to add log unit and message output module, specific as follows:
As shown in Fig. 7 ~ Fig. 9, the Synchronization Clock of the FPGA in the present embodiment, also comprises log unit, and is provided with message output module 33 in signal output unit 3, and message output module 33 exports the information of signal output unit 3 to log unit 5.Preferably, time, the signal of source unit 1 and the signal of internal clock unit 2 also all can input to described log unit.
Adopt log unit, like this can the operation conditions of recording synchronism clock apparatus in the past in a period of time objectively, help custodian better to manage Synchronization Clock.
As shown in Figure 7, Figure 8, message signals output module 33 outgoing message signal.Message signals output module 33, first by the date Hour Minute Second information in " date Hour Minute Second " module reading system, then message organizer is entered, according to the format editing message content of agreement, afterwards by by, UART rule schemata compiled by UART (abbreviation of asynchronous starting conveyer) the stipulations generator that Baud rate generator module produces, and finally sends message signals by message signals output module 33.IRIG-B coded signal output module exports IRIG-B signal." output of IRIG-B signal " module, first by the date Hour Minute Second information in " date Hour Minute Second " module reading system, then the format editing message content of stipulations organizer according to agreement is entered, IRIG-B code rule schemata compiled by stipulations generator afterwards by being produced by IRIG-B code clock generator block, finally by the log unit 5 of message signals output module 33 by the input of IRIG-B coded signal page.
As shown in Figure 9, the optimal technical scheme that the present embodiment provides has log query function.First signal enters case detecting module, once meet the trigger condition of time, case detecting module will record event result; Then enter event ordering module, the time of transmission is stamped timestamp, and event classification is numbered.Finally enter event memory module, preserve Time To Event and event code, preferably, the present embodiment has 15 kinds of events, be followed successively by: the time source of current selection, gps signal recovery or abnormal, Big Dipper signal recuperation or exception, the IRIG-B signal recovery or abnormal of Hot Spare synchronised clock, local IRIG-B coded signal recovery or abnormal, gps antenna recovery or abnormal, Beidou antenna recovery or abnormal, the saltus step recovery or abnormal of Big Dipper time, crystal oscillator tames recovery or abnormal, initialization recovery or abnormal, power module recovery or abnormal, user logins successfully or failure, gps time saltus step recovery or abnormal, IB1 time saltus step recovery or abnormal, the saltus step recovery or abnormal of Big Dipper time.Such time synchronism apparatus can also have log query module, to strengthen the management to this device.
Finally it should be noted that, above-mentioned explanation is only most preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Any those of ordinary skill in the art; do not departing within the scope of technical solution of the present invention; the way of above-mentioned announcement and technology contents all can be utilized to make many possible variations and simple replacement etc. to technical solution of the present invention, and these all belong to the scope of technical solution of the present invention protection.
Claims (10)
1. a Synchronization Clock of FPGA, is characterized in that, comprising: time source unit, internal clock unit, signal output unit and Duo Shi source sliding steps switch unit; And
Time described, source unit comprises three very first time sources in parallel, the second time source and the 3rd time source, described three time sources in parallel and reference source select model calling, described reference source selects model calling according to the time source of predetermined method choice the best, and exports source sliding steps switch unit of many times to;
Described internal clock unit, can for source unit time described reference source select module reference time signal is provided, and can for described signal output unit and described many times source sliding steps switch unit pulse signal is provided;
In described many times, sliding steps switch unit in source comprised correction module, and can signal be exported to described signal output unit, the pulse signal that described correction module provides according to the time source selecting module to provide from reference source and described internal clock unit compares, time source signal transmittance process in and/or different time source switches time, correct the signal exporting signal output unit in time.
2. the Synchronization Clock of FPGA as claimed in claim 1, is characterized in that, described many times source sliding steps switch unit also comprise time difference comparison module, described time difference comparison module comprises pulse per second (PPS) comparator and time comparator; And input to many times source sliding steps switch units first after described time difference comparison module, then input to described correction module.
3. the Synchronization Clock of FPGA as claimed in claim 1, is characterized in that, described many times source sliding steps switch unit also comprise filtering module, described filtering module comprises fused filtering device and Color seperation grating device; And the signal of described correction module is after described filtering module, just export described signal output unit to.
4. the Synchronization Clock of FPGA as claimed in claim 1, is characterized in that, time source unit also comprise three formation-decoding module of connecting with described very first time source, the second time source and the 3rd time source respectively.
5. the Synchronization Clock of FPGA as claimed in claim 4, it is characterized in that, described very first time source is satellite-signal, and described second time source is the IRIG-B signal of Hot Spare synchronised clock, and described 3rd time source is local IRIG-B coded signal.
6. the Synchronization Clock of FPGA as claimed in claim 4, it is characterized in that, after the parallel connection of described three decoder modules difference, select model calling with described reference source again, and described reference source selects module to comprise, and mode bit judges submodule, priority judges submodule and Duo Shi source judges submodule.
7. the Synchronization Clock of FPGA as claimed in claim 1, is characterized in that, be provided with times frequency module and filtering module in described internal clock unit.
8. the Synchronization Clock of FPGA as claimed in claim 1, it is characterized in that, also comprise log unit, and be provided with message output module in described signal output unit, described message output module exports the information of described signal output unit to log unit.
9. the Synchronization Clock of FPGA as claimed in claim 8, it is characterized in that, time described, the signal of source unit and the signal of described internal clock unit also all can input to described log unit.
10. a control method for FPGA Synchronization Clock, is characterized in that, the Synchronization Clock of described FPGA is a kind of Synchronization Clock as arbitrary in claim 1 ~ 9, and described method comprises:
Source unit and Duo Shi source sliding steps switch unit when A. the signal of internal clock unit being inputed to;
Source signal when B. selecting best one in source signal when multiple;
C. the time source signal and the difference of internal clock unit signal selected in set-up procedure B in described many times source sliding steps switch units, the pulse value of source signal when adjustment is described automatically;
D. the pulse of source signal when described signal output unit corrects described, then successively through IRIG-B code generator and IRIG-B code transmitter, is sent to receiving system by IRIG-B code.
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| CN106896863A (en) * | 2015-12-18 | 2017-06-27 | 南京南瑞继保电气有限公司 | A kind of embedded system self adaptation setting means |
| CN106896863B (en) * | 2015-12-18 | 2019-12-06 | 南京南瑞继保电气有限公司 | Self-adaptive time synchronization method for embedded system |
| CN106411295A (en) * | 2016-09-30 | 2017-02-15 | 西电通用电气自动化有限公司 | IRIG-B punctuality clock drift compensation method and circuit |
| CN106411295B (en) * | 2016-09-30 | 2019-03-08 | 西电通用电气自动化有限公司 | A kind of IRIG-B keeps time clock drift compensation method and circuit |
| CN107196725A (en) * | 2017-05-09 | 2017-09-22 | 合肥移顺信息技术有限公司 | Embedded device time service method based on priority |
| CN107727926A (en) * | 2017-09-29 | 2018-02-23 | 北京无线电计量测试研究所 | A kind of time and frequency measurement method and apparatus |
| CN111208726A (en) * | 2020-01-03 | 2020-05-29 | 中国船舶重工集团公司第七0七研究所 | Multi-source self-adaptive time service device and method |
| CN111208726B (en) * | 2020-01-03 | 2021-09-24 | 中国船舶重工集团公司第七0七研究所 | Multi-source self-adaptive time service device and method |
| CN115296769A (en) * | 2022-10-08 | 2022-11-04 | 中国电子科技集团公司第五十四研究所 | High-reliability timing method and device for satellite communication system of TDMA system |
| CN115296769B (en) * | 2022-10-08 | 2022-12-27 | 中国电子科技集团公司第五十四研究所 | High-reliability timing method and device for satellite communication system of TDMA system |
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