CN209433024U - Clock synchronization circuit and ocean bottom seismograph - Google Patents
Clock synchronization circuit and ocean bottom seismograph Download PDFInfo
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- CN209433024U CN209433024U CN201920324180.7U CN201920324180U CN209433024U CN 209433024 U CN209433024 U CN 209433024U CN 201920324180 U CN201920324180 U CN 201920324180U CN 209433024 U CN209433024 U CN 209433024U
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Abstract
The utility model discloses a clock synchronization circuit and ocean bottom seismograph, wherein, clock synchronization circuit includes: the earthquake monitoring system comprises a main clock circuit, at least one earthquake data acquisition circuit, a microprocessor control circuit and at least two frequency division circuits; the at least two frequency dividing circuits comprise a first frequency dividing circuit and a second frequency dividing circuit; the master clock circuit is used for generating a master clock signal; the first frequency division circuit is connected with the main clock circuit and used for carrying out frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal; the seismic data acquisition circuit is connected with the first frequency division circuit and used for acquiring a seismic data acquisition clock signal; the second frequency dividing circuit is connected with the main clock circuit and is used for carrying out frequency dividing processing on the main clock signal to obtain a real-time clock signal; microprocessor control circuit and second frequency-dividing circuit are connected, are used for acquireing real-time clock signal, the embodiment of the utility model provides a clock synchronization circuit time precision is high and the low power dissipation.
Description
Technical field
The utility model embodiment is related to phospecting apparatus field more particularly to a kind of clock synchronization circuit and submarine earthquake
Instrument.
Background technique
Submarine seismograph (OBS) is that one kind is placed on seabed, can directly receive artificial or earthquake signal record
Instrument, compared with common seismic data, the data of submarine seismograph record have a variety of advantages, for example, submarine seismograph is laid
In seabed, data record has higher signal-to-noise ratio not vulnerable to water body noise and effect of jitter.In addition, submarine earthquake
Instrument additionally provides the observation system of wide-azimuth, be conducive under complicated coating (such as salt dome) imaging on stratum and to angle phase
The reflectivity of pass is analyzed.The data processing of submarine seismograph is mainly concerned with the arrival time of seismic wave, to the standard of time
Exactness requirement is very high, so the time accuracy of submarine seismograph digital data recording system is extremely important.Existing submarine earthquake
The modules of instrument are all made of independent clock crystal oscillator, so that it is easy to cause time disorder between submarine seismograph modules, so that
The time accuracy of submarine seismograph data record is not high.
Utility model content
The utility model provides a kind of clock synchronization circuit and submarine seismograph, accurate with the time for improving submarine seismograph
Degree.
In a first aspect, the utility model embodiment provides a kind of clock synchronization circuit, comprising:
Master clock circuit, at least one earthquake data acquisition circuit, microprocessor control circuit and at least two frequency dividing electricity
Road；
At least two frequency dividing circuits include the first frequency dividing circuit and the second frequency dividing circuit；
The master clock circuit is for generating master clock signal；
First frequency dividing circuit is connect with the master clock circuit, for carrying out scaling down processing to the master clock signal
Obtain earthquake data acquisition clock signal；
The earthquake data acquisition circuit is connect with first frequency dividing circuit, when for obtaining the earthquake data acquisition
Clock signal；
Second frequency dividing circuit is connect with the master clock circuit, for carrying out scaling down processing to the master clock signal
Obtain real-time clock signal；
The microprocessor control circuit is connect with second frequency dividing circuit, for obtaining the real-time clock signal.
Optionally, second frequency dividing circuit is directly connect with the master clock circuit or second frequency dividing circuit
It is connect by first frequency dividing circuit with the master clock circuit.
Optionally, at least two frequency dividing circuit further includes third frequency dividing circuit；
The third frequency dividing circuit is connect with the master clock circuit, for carrying out scaling down processing to the master clock signal
Obtain second pulse signal；
The microprocessor control circuit is connect with the third frequency dividing circuit, for obtaining the second pulse signal.
Optionally, the third frequency dividing circuit is directly connect with the master clock circuit or the third frequency dividing circuit
It is connect by first frequency dividing circuit and/or second frequency dividing circuit with the master clock circuit.
Optionally, the microprocessor control circuit and the earthquake data acquisition circuit connection, for obtaining earthquake number
It is handled according to and to the seismic data.
Optionally, the clock synchronization circuit further includes GPS module, the GPS module and microprocessor control electricity
Road connection, for providing standard second pulse signal and World clock signal to the microprocessor control circuit.
Optionally, the clock synchronization circuit further includes power supply, the power supply respectively with the master clock circuit, described
Data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit and GPS module electrical connection are shaken, for distinguishing
To the master clock circuit, the earthquake data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit and described
GPS module power supply.
Second aspect, the utility model embodiment additionally provide a kind of submarine seismograph, including appointing described in first aspect
One clock synchronization circuit.
The utility model embodiment believes master clock by using a master clock circuit, using at least two frequency dividing circuits
Number carrying out scaling down processing obtains earthquake data acquisition clock signal and real-time clock signal, so that the clock signal of modules
Unanimously, the modules for solving submarine seismograph in the prior art use intermodule time disorder caused by independent clock crystal oscillator
The problem of, realize the submarine seismograph with high time accuracy.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of clock synchronization circuit provided by the embodiment of the utility model；
Fig. 2 is the structural schematic diagram of another clock synchronization circuit provided by the embodiment of the utility model；
Fig. 3 is the structural schematic diagram of another clock synchronization circuit provided by the embodiment of the utility model；
Fig. 4 is a kind of flow diagram of clock synchronizing method provided by the embodiment of the utility model；
Fig. 5 is the flow diagram of another clock synchronizing method provided by the embodiment of the utility model；
Fig. 6 is the flow diagram of another clock synchronizing method provided by the embodiment of the utility model；
Fig. 7 is a kind of flow chart of clock synchronizing method provided by the embodiment of the utility model.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than the restriction to the utility model.It further needs exist for
It is bright, part relevant to the utility model is illustrated only for ease of description, in attached drawing rather than entire infrastructure.
Fig. 1 is a kind of structural schematic diagram of clock synchronization circuit provided by the embodiment of the utility model, as shown in Figure 1, this
Utility model embodiment provide clock synchronization circuit include: master clock circuit 11, at least one earthquake data acquisition circuit 12,
Microprocessor control circuit 13 and at least two frequency dividing circuits 14；At least two frequency dividing circuits 14 include the first frequency dividing circuit 141
With the second frequency dividing circuit 142；Master clock circuit 11 is for generating master clock signal；First frequency dividing circuit 141 and master clock circuit
11 connections obtain earthquake data acquisition clock signal for carrying out scaling down processing to master clock signal；Earthquake data acquisition circuit
12 connect with the first frequency dividing circuit 141, for obtaining earthquake data acquisition clock signal；Second frequency dividing circuit 142 and master clock
Circuit 11 connects, and obtains real-time clock signal for carrying out scaling down processing to master clock signal；Microprocessor control circuit 13 with
Second frequency dividing circuit 142 connection, for obtaining real-time clock signal.
The technical solution of the utility model embodiment utilizes at least two frequency dividing electricity by using a master clock circuit 11
Road 14 carries out scaling down processing to master clock signal and obtains earthquake data acquisition clock signal and real-time clock signal, seismic data
The clock signal of Acquisition Circuit 12 and microprocessor control circuit 13 solves existing skill from the same master clock circuit 11
The problem of modules of submarine seismograph are using intermodule time disorder caused by independent clock crystal oscillator in art, realizing has
The submarine seismograph of high time accuracy.
Optionally, at least two frequency dividing circuits 14 further include third frequency dividing circuit 143；Third frequency dividing circuit 143 and it is main when
Clock circuit 11 connects, and obtains second pulse signal for carrying out scaling down processing to master clock signal；Microprocessor control circuit 13 with
Third frequency dividing circuit 143 connects, for obtaining second pulse signal.
Optionally, the second frequency dividing circuit 142 is directly connect with master clock circuit 11, or as shown in Figure 1, the second frequency dividing electricity
Road 142 is connect by the first frequency dividing circuit 141 with master clock circuit 11.
Optionally, third frequency dividing circuit 143 is directly connect with master clock circuit or third frequency dividing circuit 143 is by the
One frequency dividing circuit 141 and/or the second frequency dividing circuit 142 are connect with master clock circuit 11, and those skilled in the art can be by repairing
Change the parameter of frequency dividing circuit and use different connection types, so that the connection type to frequency dividing circuit and master clock circuit carries out
Variation and adjustment are without departing from the protection scope of the utility model.
Optionally, the second frequency dividing circuit 142 is independently arranged (as shown in Figure 1), or is integrated in microprocessor control circuit
In 13.Illustratively, Fig. 2 is the structural schematic diagram of another clock synchronization circuit provided by the embodiment of the utility model, such as Fig. 2
Shown, the second frequency dividing circuit 142 is integrated in inside microprocessor control circuit 13, and microprocessor control circuit 13 passes through first point
Frequency circuit 141 is connect with master clock circuit 11, and is carried out at frequency dividing by the second internal frequency dividing circuit 142 to master clock signal
Reason obtain real-time clock signal, the second frequency dividing circuit 142 is integrated in inside microprocessor control circuit 13 be conducive to reduce when
The volume of clock synchronous circuit.
Optionally, microprocessor control circuit 13 is connect with earthquake data acquisition circuit 12, for obtaining seismic data simultaneously
Seismic data is handled.
Shown in continuing to refer to figure 1, optionally, clock synchronization circuit provided by the embodiment of the utility model further includes GPS mould
Block 15, GPS module 15 are connect with microprocessor control circuit 13, for providing standard pulse per second (PPS) to microprocessor control circuit 13
Signal (Pulse Per Second, PPS) and World clock signal (UTC), when microprocessor control circuit 13 is also used to each
The management and calculating of clock.
Shown in continuing to refer to figure 1, optionally, clock synchronization circuit provided by the embodiment of the utility model further includes power supply
16, power supply 16 respectively with master clock circuit 11, earthquake data acquisition circuit 12, microprocessor control circuit 13, frequency dividing circuit 14
It is electrically connected with GPS module 15, for respectively to master clock circuit 11, earthquake data acquisition circuit 12, microprocessor control circuit
13, frequency dividing circuit 14 and GPS module 15 are powered.
Illustratively, Fig. 3 is the structural schematic diagram of another clock synchronization circuit provided by the embodiment of the utility model, such as
Shown in Fig. 3, master clock circuit 11 uses the high precision temperature compensation type quartz-crystal resonator TCXO of 16.384Mhz
(Temperature Compensate X'tal (crystal) Oscillator, TCXO), for providing master clock signal.This
The clock synchronization circuit that utility model embodiment provides includes four frequency dividing circuits, respectively 141, second points of the first frequency dividing circuit
Frequency circuit 142, third frequency dividing circuit 143 and divide by four circuit 144, clock synchronization circuit provided by the embodiment of the utility model
It further include two earthquake data acquisition circuits (ADC) 12, respectively the first earthquake data acquisition circuit 121 and the second seismic data
Acquisition Circuit 122, wherein the first frequency dividing circuit 141 is connect with master clock circuit 11, for carrying out at frequency dividing to master clock signal
Reason obtains earthquake data acquisition clock signal；First earthquake data acquisition circuit 121 is connect with the first frequency dividing circuit 141, is used for
Earthquake data acquisition clock signal needed for obtaining the first earthquake data acquisition circuit 121；Divide by four circuit 144 and first point
Frequency circuit 141 and the connection of the second earthquake data acquisition circuit 122, for obtaining needed for the second earthquake data acquisition circuit 122
Earthquake data acquisition clock signal；Second frequency dividing circuit 142 is connect with divide by four circuit 144, for obtaining real-time clock
Signal, wherein real-time clock signal is transferred to the real-time clock of submarine seismograph, and real-time clock is for being arranged submarine seismograph
System time；Third frequency dividing circuit 143 is connect with the second frequency dividing circuit 142, for obtaining second pulse signal；Microprocessor control
Circuit 13 is connect with the second frequency dividing circuit 142 and third frequency dividing circuit 143, for obtaining real-time clock signal and pulse per second (PPS) letter
Number, microprocessor control circuit 13 and the first earthquake data acquisition circuit 121 and the second earthquake data acquisition circuit 122 connect
It connects, for obtaining seismic data and handling seismic data.Optionally, the first frequency dividing circuit 141 uses 10 frequency dividing circuits,
Earthquake data acquisition clock signal for 1.6384Mhz needed for generating the first earthquake data acquisition circuit 121；4th frequency dividing
Circuit 144 uses 2 frequency dividing circuits, the seismic data for 0.8192Mhz needed for generating the second earthquake data acquisition circuit 122
Acquire clock signal；Second frequency dividing circuit 142 uses 25 frequency dividing circuits, for generating the real-time clock signal of 32.768Khz；The
Divide-by-3 circuit 143 uses 32768 frequency dividing circuits, for generating second pulse signal.GPS module 15 and microprocessor control circuit
13 connections, for providing standard second pulse signal (Pulse Per Second, PPS) and the world to microprocessor control circuit 13
Clock signal (UTC), microprocessor control circuit 13 is also used to the management and calculating of each clock, so that submarine seismograph
System time and GPS module standard second pulse signal is provided and World clock signal to carry out check and correction synchronous, with realizing seabed
The system time for shaking instrument is synchronous with the Microsecond grade of universal time.
The technical solution of the utility model embodiment utilizes at least two frequency dividing electricity by using a master clock circuit 11
Road 14 carries out scaling down processing to master clock signal and obtains earthquake data acquisition clock signal and real-time clock signal, seismic data
The clock signal of Acquisition Circuit 12 and microprocessor control circuit 13 solves existing skill from the same master clock circuit 11
The problem of modules of submarine seismograph are using intermodule time disorder caused by independent clock crystal oscillator in art, realizes multi-pass
Road seismic data Microsecond grade is synchronous, keeps submarine seismograph time system more accurate, it is ensured that the validity of seismic data, and
The use for avoiding multiple crystal oscillators reduces the power consumption of submarine seismograph.The technical solution of the utility model embodiment also uses GPS
Module provides standard second pulse signal and World clock signal, and submarine seismograph is believed by providing standard pulse per second (PPS) with GPS module
Number carry out that check and correction is synchronous with World clock signal, it is synchronous with the Microsecond grade of universal time to realize submarine seismograph, so that
The seismic data of submarine seismograph and the seismic data of other stations can do comparative analysis, it is ensured that same dispensing batch is not
With can more accurately carry out data analysis between the submarine seismograph station.
Conceived based on same utility model, the utility model embodiment additionally provides a kind of clock synchronizing method, is used for
The explanation of any clock synchronization circuit provided by the above embodiment, same as the previously described embodiments or corresponding structure and term exists
This is repeated no more, and Fig. 4 is a kind of flow diagram of clock synchronizing method provided by the embodiment of the utility model, as shown in figure 4,
This method comprises the following steps:
Step 110, earthquake data acquisition circuit carry out frequency dividing to master clock signal by the first frequency dividing circuit and obtain earthquake
Data acquire clock signal.
Step 120, microprocessor control circuit carry out frequency dividing to master clock signal by the second frequency dividing circuit and obtain in real time
Clock signal.
There is no sequencing requirement, this field in technical solution provided in this embodiment, between step 210 and step 220
Technical staff can convert above-mentioned sequencing and and without departing from the protection scope of the utility model.
The technical solution of the utility model embodiment carries out frequency dividing to master clock signal using the method for frequency dividing and obtains earthquake
Data acquire clock signal and real-time clock signal, when the modules for solving submarine seismograph in the prior art use independent
Caused by clock crystal oscillator the problem of the disorder of intermodule time, so that submarine seismograph time accuracy with higher.
Fig. 5 is the flow diagram of another clock synchronizing method provided by the embodiment of the utility model, as shown in figure 5,
Optionally, clock synchronizing method provided by the embodiment of the utility model may include:
Step 210, earthquake data acquisition circuit carry out frequency dividing to master clock signal by the first frequency dividing circuit and obtain earthquake
Data acquire clock signal.
Step 220, microprocessor control circuit carry out frequency dividing to master clock signal by the second frequency dividing circuit and obtain in real time
Clock signal.
Step 230, microprocessor control circuit carry out frequency dividing to master clock signal by third frequency dividing circuit and obtain second arteries and veins
Rush signal.
Clock synchronization circuit further includes GPS module 15, and GPS module 15 is connect with microprocessor control circuit 13, continues to join
It examines shown in Fig. 4, optionally, clock synchronizing method provided by the embodiment of the utility model further include:
The zebra time signal that step 240, the microprocessor control circuit are provided according to the GPS module is to the reality
When clock signal carry out the operation of first time time synchronization, first time time synchronization operation is accurate to a second rank.
The standard second pulse signal that step 250, the microprocessor control circuit are provided according to the GPS module is to described
Real-time clock signal carries out second of time synchronization operation, and second of time synchronization operation is accurate in 1 millisecond.
In technical solution provided in this embodiment, there is no sequencing to want between step 210, step 220 and step 230
It asks, those skilled in the art can convert above-mentioned sequencing and and without departing from the protection scope of the utility model.
Fig. 6 is the flow diagram of another clock synchronizing method provided by the embodiment of the utility model, the utility model
Embodiment has carried out further refinement on the basis of the technical solution that a upper embodiment provides, to step 250, with above-mentioned implementation
Example is identical or the explanation of corresponding term details are not described herein.
Optionally, the standard second pulse signal that the microprocessor control circuit is provided according to the GPS module is to described
Real-time clock signal carries out second of time synchronization operation, and second of time synchronization operation is accurate in 1 millisecond, comprising:
The microprocessor control circuit obtains the according to the first failing edge of standard second pulse signal moment that arrives
One real-time clock signal, first real-time clock signal are accurate to microsecond rank.
The microprocessor control circuit obtains the according to the second failing edge of standard second pulse signal moment that arrives
Two real-time clock signals, second real-time clock signal are accurate to microsecond rank；Under first failing edge and described second
Drop edge is two standard second pulse signal failing edges adjacent in the standard second pulse signal.
The standard is judged according to the time difference of second real-time clock signal and first real-time clock signal
Whether second pulse signal is continuous impulse signal, and calculates pulse per second (PPS) when the standard second pulse signal is continuous impulse signal
Pulse error between signal and the standard second pulse signal.
The pulse error is added into the real-time clock signal.
Optionally, the zebra time signal that the microprocessor control circuit is provided according to the GPS module is to the reality
When clock signal carry out the operation of first time time synchronization, first time time synchronization operation is also wrapped before being accurate to second rank
It includes:
The microprocessor control circuit repeatedly obtains the standard second pulse signal and zebra time that the GPS module provides
Signal；
It is that correct signal determines the GPS according to the standard second pulse signal and zebra time signal that repeatedly obtain
Module stability.
It, can be with as shown in fig. 6, clock synchronizing method provided by the embodiment of the utility model based on above-mentioned refinement and addition
Include the following steps:
Step 401, earthquake data acquisition circuit carry out frequency dividing to master clock signal by the first frequency dividing circuit and obtain earthquake
Data acquire clock signal.
Step 402, microprocessor control circuit carry out frequency dividing to master clock signal by the second frequency dividing circuit and obtain in real time
Clock signal.
Step 403, microprocessor control circuit carry out frequency dividing to master clock signal by third frequency dividing circuit and obtain second arteries and veins
Rush signal.
Step 404, the microprocessor control circuit repeatedly obtain the standard second pulse signal that the GPS module provides and
Zebra time signal.
The standard second pulse signal and zebra time signal that step 405, basis repeatedly obtain are that correct signal is true
The fixed GPS module is stablized.
The zebra time signal that step 406, the microprocessor control circuit are provided according to the GPS module is to the reality
When clock signal carry out the operation of first time time synchronization, first time time synchronization operation is accurate to a second rank.
When step 407, the microprocessor control circuit arrive according to the first failing edge of the standard second pulse signal
It carves and obtains the first real-time clock signal, first real-time clock signal is accurate to microsecond rank.
When step 408, the microprocessor control circuit arrive according to the second failing edge of the standard second pulse signal
It carves and obtains the second real-time clock signal, second real-time clock signal is accurate to microsecond rank；First failing edge and institute
Stating the second failing edge is two standard second pulse signal failing edges adjacent in the standard second pulse signal.
Wherein, optionally, microprocessor control circuit can also obtain first according to the rising edge of standard second pulse signal
Real-time clock signal and the second real-time clock signal, the utility model do not limit this.
Step 409 judges according to the time difference of second real-time clock signal and first real-time clock signal
Whether the standard second pulse signal is continuous impulse signal, and is counted when the standard second pulse signal is continuous impulse signal
Calculate the pulse error between second pulse signal and the standard second pulse signal.
The pulse error is added into the real-time clock signal by step 410.
Illustratively, Fig. 7 is a kind of flow chart of clock synchronizing method provided by the embodiment of the utility model, with reference to Fig. 7
It is shown, firstly, starting GPS module.Wherein, it is opening submarine seismograph and is ensuring microprocessor control circuit (MCU) normal work
After work, GPS module power supply is opened, starts GPS module, GPS module is waited to obtain correct standard second pulse signal (Pulse
Per Second, PPS) and World clock signal (UTC).
Then, microprocessor control circuit repeatedly obtains the standard second pulse signal and zebra time letter of GPS module offer
Number and according to the standard second pulse signal and zebra time signal that repeatedly obtain be correct signal determine GPS module stablize.Its
In, have in the Serial Port Information that GPS module provides comprising the whether correct identifier of signal, microprocessor control circuit passes through differentiation
Whether the identifier is correctly microprocessor come the standard second pulse signal and zebra time signal for confirming GPS module offer
Control circuit acquisition 10 times or more correct standard second pulse signals and zebra time signals, to guarantee that GPS module is stablized.
Microprocessor control circuit carries out for the first time real-time clock signal according to the zebra time signal that GPS module provides
Time synchronization operation, the operation of first time time synchronization are accurate to a second rank.Wherein, the Serial Port Information packet exported using GPS module
The temporal informations such as the date Hour Minute Second contained synchronize real-time clock signal, to complete the time that accuracy is second rank
It is synchronous.
When microprocessor control circuit is real-time according to the first failing edge of standard second pulse signal arrival moment acquisition first
Clock signal, the first real-time clock signal are accurate to microsecond rank.Wherein, microprocessor control circuit judgment criteria second pulse signal
The first failing edge whether arrive, when microprocessor control circuit captures the first failing edge of standard second pulse signal, then read
First real-time clock signal is accurate to microsecond rank and saved by the first real-time clock signal for taking this moment.
When microprocessor control circuit is real-time according to the second failing edge of standard second pulse signal arrival moment acquisition second
Clock signal, the second real-time clock signal are accurate to microsecond rank；First failing edge and the second failing edge are standard second pulse signal
In adjacent two standard second pulse signal failing edges.Wherein, after obtaining the first real-time clock signal, microprocessor control
Circuit waits the failing edge of next standard second pulse signal to arrive, and the failing edge of next standard second pulse signal is standard second arteries and veins
The second failing edge for rushing signal is then obtained when microprocessor control circuit captures the second failing edge of standard second pulse signal
Second real-time clock signal is accurate to microsecond rank and saved by second real-time clock signal at this moment.
Time difference judgment criteria second pulse signal according to the second real-time clock signal and the first real-time clock signal is
No is continuous impulse signal, and second pulse signal and standard pulse per second (PPS) are calculated when standard second pulse signal is continuous impulse signal
Pulse error between signal.Wherein, if it is continuous that value, which differs the interval PPS illustrated for one second this twice,.Microprocessor
It is poor that control circuit makees the time of the second real-time clock signal and the first real-time clock signal, judges whether difference is one second, if
Microprocessor control circuit judges that the time difference of the second real-time clock signal and the first real-time clock signal is one second, then determines
Standard second pulse signal is continuous impulse signal, and otherwise, standard second pulse signal is not continuous impulse signal, is needed at this time again
The first real-time clock signal is obtained according to the first failing edge of standard second pulse signal arrival moment.If standard second pulse signal is
Continuous impulse signal, at this time second pulse signal and standard second pulse signal second precision error below or Millisecond error below
It is exactly the actual error of submarine seismograph system time and universal time, is calculated by counter counts and calculate second pulse signal
With the pulse error between standard second pulse signal.
Pulse error is added into real-time clock signal.Wherein, pulse error number is increased into real-time clock (RTC)
In pulse counter in, so that the error between the time of real-time clock signal and standard second pulse signal is eliminated, thus complete
Time and universal time Millisecond time synchronization below at real-time clock signal close after the deadline is synchronous
GPS module reduces energy consumption.
The technical solution of the utility model embodiment carries out frequency dividing to master clock signal using the method for frequency dividing and obtains earthquake
Data acquire clock signal and real-time clock signal, when the modules for solving submarine seismograph in the prior art use independent
Caused by clock crystal oscillator the problem of the disorder of intermodule time, so that submarine seismograph time accuracy with higher and lower function
Consumption, and ensure the validity of seismic data.The technical solution of the utility model embodiment also by by real-time clock signal and
Second pulse signal and GPS module provide standard second pulse signal and World clock signal to carry out check and correction synchronous, with realizing seabed
The system time for shaking instrument is synchronous with the Microsecond grade of universal time, and highest is able to achieve system time and the world of submarine seismograph
For the time error of standard time within 30us, guarantee reaches error quasi synchronous design requirement of essence in 1ms, so that seabed
The seismic data of the seismic data and other stations that shake instrument can do comparative analysis, it is ensured that the same different seabeds for launching batch
Data analysis can be more accurately carried out between the seismic detector station.
Conceived based on same utility model, the utility model embodiment additionally provides a kind of submarine seismograph, including upper
Any clock synchronization circuit of embodiment offer is stated, the explanation of same as the previously described embodiments or corresponding structure and term is herein
It repeats no more.
Note that above are only the preferred embodiment and institute's application technology principle of the utility model.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, is able to carry out for a person skilled in the art various bright
Aobvious variation, readjustment and substitution is without departing from the protection scope of the utility model.Therefore, although passing through above embodiments
The utility model is described in further detail, but the utility model is not limited only to above embodiments, is not departing from
It can also include more other equivalent embodiments in the case that the utility model is conceived, and the scope of the utility model is by appended
Scope of the claims determine.
Claims (8)
1. a kind of clock synchronization circuit characterized by comprising
Master clock circuit, at least one earthquake data acquisition circuit, microprocessor control circuit and at least two frequency dividing circuits；
At least two frequency dividing circuits include the first frequency dividing circuit and the second frequency dividing circuit；
The master clock circuit is for generating master clock signal；
First frequency dividing circuit is connect with the master clock circuit, is obtained for carrying out scaling down processing to the master clock signal
Earthquake data acquisition clock signal；
The earthquake data acquisition circuit is connect with first frequency dividing circuit, for obtaining the earthquake data acquisition clock letter
Number；
Second frequency dividing circuit is connect with the master clock circuit, is obtained for carrying out scaling down processing to the master clock signal
Real-time clock signal；
The microprocessor control circuit is connect with second frequency dividing circuit, for obtaining the real-time clock signal.
2. clock synchronization circuit according to claim 1, which is characterized in that second frequency dividing circuit directly with the master
Clock circuit connection or second frequency dividing circuit are connect by first frequency dividing circuit with the master clock circuit.
3. clock synchronization circuit according to claim 1, which is characterized in that at least two frequency dividing circuit further includes
Divide-by-3 circuit；
The third frequency dividing circuit is connect with the master clock circuit, is obtained for carrying out scaling down processing to the master clock signal
Second pulse signal；
The microprocessor control circuit is connect with the third frequency dividing circuit, for obtaining the second pulse signal.
4. clock synchronization circuit according to claim 3, which is characterized in that the third frequency dividing circuit directly with the master
Clock circuit connection or the third frequency dividing circuit by first frequency dividing circuit and/or second frequency dividing circuit with
The master clock circuit connection.
5. clock synchronization circuit according to claim 1, which is characterized in that the microprocessor control circuit is with described
Data acquisition circuit connection is shaken, for obtaining seismic data and handling the seismic data.
6. clock synchronization circuit according to claim 1, which is characterized in that further include GPS module, the GPS module with
The microprocessor control circuit connection, for providing standard second pulse signal and universal time to the microprocessor control circuit
Clock signal.
7. clock synchronization circuit according to claim 6, which is characterized in that further include power supply, the power supply respectively with institute
State master clock circuit, the earthquake data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit and the GPS
Module electrical connection, for respectively to the master clock circuit, the earthquake data acquisition circuit, microprocessor control electricity
Road, the frequency dividing circuit and GPS module power supply.
8. a kind of submarine seismograph, which is characterized in that including the described in any item clock synchronization circuits of claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920324180.7U CN209433024U (en) | 2019-03-14 | 2019-03-14 | Clock synchronization circuit and ocean bottom seismograph |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920324180.7U CN209433024U (en) | 2019-03-14 | 2019-03-14 | Clock synchronization circuit and ocean bottom seismograph |
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| Publication Number | Publication Date |
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| CN209433024U true CN209433024U (en) | 2019-09-24 |
Family
ID=67978624
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| CN201920324180.7U Active CN209433024U (en) | 2019-03-14 | 2019-03-14 | Clock synchronization circuit and ocean bottom seismograph |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109738954A (en) * | 2019-03-14 | 2019-05-10 | 南方科技大学 | Clock synchronization circuit, clock synchronization method and ocean bottom seismograph |
| WO2024082643A1 (en) * | 2022-10-19 | 2024-04-25 | 扬力集团股份有限公司 | Press machine edge control device and control method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109738954A (en) * | 2019-03-14 | 2019-05-10 | 南方科技大学 | Clock synchronization circuit, clock synchronization method and ocean bottom seismograph |
| WO2020181852A1 (en) * | 2019-03-14 | 2020-09-17 | 南方科技大学 | Clock synchronization circuit, clock synchronization method and seabed seismograph |
| CN109738954B (en) * | 2019-03-14 | 2024-03-15 | 南方科技大学 | Clock synchronization circuit, clock synchronization method and submarine seismograph |
| WO2024082643A1 (en) * | 2022-10-19 | 2024-04-25 | 扬力集团股份有限公司 | Press machine edge control device and control method |
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