CN103457716A - Optimizing time synchronizing device for multi-channel clock sources - Google Patents
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Abstract
The invention relates to an optimizing time synchronizing device for multi-channel clock sources. The optimizing time synchronizing device comprises at least two units identical in structure. In every unit, a global positioning system ground receiver (8) is connected with a counter (7), the counter (7) is further connected with a comparator (6) in the unit, a high-stability crystal oscillator (1) is directly connected with the counter (7) in every unit or connected with the counter (7) in every unit through a phase-locking frequency multiplier (2), and the comparator (6) in every unit is respectively connected with one input end of a multiplexer (4). The counter (7), the comparator (6) and a register (5) in every unit are respectively connected with a single chip microcomputer (3), and the output end of the single chip microcomputer (3) is further connected with the multiplexer (4). The optimizing time synchronizing device has the advantages that the comprehensive cost is low, algorithm adaptability is high, optimization of the multi-channel clock sources is supported, various time difference compensation strategies are supported, high-precision punctuality can be achieved, and time signal output is stable and reliable, and the like.
Description
Technical field
The present invention relates to a kind of time synchronism apparatus, be specifically related to a kind of source optimizing of many times time synchronism apparatus that is mainly used in the Power System and its Automation technical field.
Background technology
In the power system operation process; the running status of electrical network is fast changing; for guaranteeing power grid security and economical operation; variously take computer technology and the communication technology and be widely used as basic automation equipment; as dispatch automated system, fault wave recording device, microcomputer protective relay device, sequence of events recording device, computer monitoring system of transformer substation, calculating fee of electric energy system, thermal power plant turbine unit automatic control system, lightning location system etc., the normal operation of these systems all needs unified time reference support.
Global position system GPS, as the widest time dissemination system of the scope of application in the world, is used widely at Power time synchronization system.Because gps system is controlled by US military, the reason and US military does not guarantee service quality etc., the clock synchronization system that the GPS of take is standard exists haggles over large potential safety hazard.Construction along with China's Big Dipper navigation positioning system, thoroughly changed the situation of GPS as the unique clock source of clock synchronization system, current high-grade transformer station generally adopts the clock synchronization system in GPS and dipper system doubleclocking source, in such selective problems in source will solve in the system in source when two the time, the lock condition in source when current common solution is two of comparisons, if a locking, a losing lock, system is by the time source operation of locking; If source losing lock all in the time of two, the punctual operation of system; In the time of two, source all locks, source operation while pressing that gives tacit consent to.
No matter be gps system or dipper system, its ground receiver is due to the impact that is subject to the factors such as ephemeris error, ionospheric error, tropospheric error, multipath error, receiver error, tracking satellite number be very few, its directly time signal of output all contain a random error that is normal distribution.The GPS receiver that the pulse per second (PPS) standard deviation of take is 0.1 μ s is example, the pps pulse per second signal of its output also can be observed the gross error that approaches 0.4 μ s in the observation of hour level, in the situation that the satellite experiment saltus step has test more to be recorded to the time saltus step of 10ms magnitude.In power system automatic field, wish that time device can provide time precision to be better than 1 μ s, digital transformer substation will guarantee that in 1 hour, time keeping error is less than 1 μ s, obviously, directly uses the time signal of global positioning system ground receiver output to be difficult to meet the demands.
Along with popularizing of digital transformer substation, digital transformer substation has proposed new requirements at the higher level to Power time synchronization system.In digital transformer substation, the high-precision sampled value that merge cells provides is the normal guarantee moved of various functions of entirely standing, and the sample-synchronous precision of electronic mutual inductor is the key factor that affects the sampled value precision.For realizing the synchronous of the interior different merge cells sampling pulses in full station, merge cells in digital transformer substation generally adopts the technical scheme that sampling pulse is synchronizeed with the clock synchronization system pulse per second (PPS), utilizes the pulse per second (PPS) of clock synchronization system to guarantee the synchronism that merge cells is sampled.Such system has proposed new higher specification requirement to clock synchronization system: because the merge cells sampling pulse is synchronized with the pulse per second (PPS) of clock synchronization system, the generation that the fluctuation at pulse per second (PPS) interval will be combined the unit sampling pulse impacts, particularly when clock synchronization system proceeds to synchronous regime by punctual state, traditional clock synchronization system completes the punctual error disposable compensation caused, cause the fluctuation in the pulse per second (PPS) time interval, the stable operation that is combined unit causes adverse effect.
The Power time synchronization system of current main flow, generally adopt and take the structure that single-chip microcomputer+FPGA is core, by to the time source signal analytical calculation, rebuild local clock and output to the time signal, this process has strong dependence to single-chip microcomputer, when monolithic processor resetting or dog sting, the temporarily output of dwell time signal, the stability of influence time synchro system operation.
Summary of the invention
The present invention aims to provide source optimizing of a kind of many times time synchronism apparatus, and integrated cost is lower, and the algorithm strong adaptability is supported the mutually standby optimizing in multipath clock source, supports multiple time difference compensation strategy, can realize high-precision keeping time, and the time signal stable output is reliable.
In order to solve the problems of the technologies described above, the present invention has adopted following technical scheme:
Source optimizing of many times time synchronism apparatus, it is characterized in that: this device comprises high stability crystal oscillator, single-chip microcomputer and MUX; Also comprise at least two unit that structure is identical, each unit comprises global positioning system ground receiver, counter, comparator and register, in each unit, the pulse per second (PPS) output of global positioning system ground receiver is connected with the Event triggered input of counter, and the count value output of counter connects the input of the comparator in this unit; Directly be connected or connect by phaselocking frequency multiplier between the input end of clock of the output terminal of clock of high stability crystal oscillator and counter in each unit; In each unit, the pulse output end of comparator accesses respectively an input of MUX; Counter in each unit, comparator and register are connected with single-chip microcomputer respectively; The output of single-chip microcomputer also is connected with the control end of MUX.
Preferably, each unit also comprises state machine and adder; The input of state machine is connected to the output of comparator, and comparator is for the cycle of states of starting state machine; An output of state machine is connected with the control end of adder for starting the operation of adder; Another output of state machine is connected with the control end that writes of comparator; Two inputs of adder are connected with the output port of comparator and register respectively, and adder is used for the interior setting value of comparator and register value addition; The output port of adder is connected with the data-in port of comparator; Another output of state machine is connected with the control end that writes of comparator, is used for controlling the output of adder is write to comparator.
Good effect of the present invention is:
When the device in the present invention can be to two, the standard deviation in source is calculated and is provided support, thereby can allow the poor source as benchmark when little of system preferred standard, source optimizing while namely supporting.
Device of the present invention, can be supported multi-frequency measurement and Error Compensation Algorithm, thereby make the time signal standard deviation of output less, and realize high-precision punctual.
The device that the present invention proposes had both been supported the disposable leapfrog time difference compensation of error, the linearity of also supporting error progressively to compensate pursue and attack correction technique (such as, per second compensates 0.2 μ s, until the error zero clearing).
The device that the present invention proposes, although also used single-chip microcomputer, system has immunity to monolithic processor resetting, during monolithic processor resetting, system proceeds to punctual state automatically, maintains the punctual output under certain precision, has improved the system reliability of operation.
This device integrated cost is lower, and the algorithm strong adaptability can be supported the mutually standby optimizing in multipath clock source, supports multiple time difference compensation strategy, can realize high-precision keeping time, and the generation of time signal is not strong to the single-chip microcomputer dependence, and the time signal stable output is reliable.Use this design, use 10M constant-temperature crystal oscillator phase locking frequency multiplying to 100MHz, the GPS of quality of fit 50ns and Big Dipper generation ground receiver, successfully realized that the pulse per second (PPS) precision is better than 0.1 μ s, and punctual precision is better than the highly reliable digital transformer substation time synchronism apparatus of 1 μ s/h.
The accompanying drawing explanation
Fig. 1 is structure and the operation principle schematic diagram of the embodiment of the present invention one.
Fig. 2 is structure and the operation principle schematic diagram of the embodiment of the present invention two.
Wherein phaselocking frequency multiplier 2 can also be built in FPGA.
In accompanying drawing, wherein phaselocking frequency multiplier 2 can also be built in FPGA.
Embodiment
Further illustrate the present invention below in conjunction with drawings and Examples.
Embodiment mono-
The present embodiment is basic structure of the present invention.
As Fig. 1, comprise high stability crystal oscillator 1, single-chip microcomputer 3 and MUX 4; Also comprise at least two unit that structure is identical, each unit comprises global positioning system ground receiver 8, counter 7, comparator 6 and register 5, in each unit, the pulse per second (PPS) output of global positioning system ground receiver 8 is connected with the Event triggered input of counter 7, the count value output of counter 7 connects the input of the comparator 6 in this unit, the numerical value built-in with comparator 6 compares, when numerical value is identical, comparator 6 output pulse signals are to multichannel selector 4.Directly be connected or connect by phaselocking frequency multiplier 2 between the input end of clock of the output terminal of clock of high stability crystal oscillator 1 and counter 9 in each unit.Counter 7 in each unit, comparator 6 and register 5 are connected with single-chip microcomputer 3 respectively, and single-chip microcomputer 3 reads the count value of each unit inside counting device 7, and single-chip microcomputer 3 also arranges comparison value to counter 6, and single-chip microcomputer 3 is also for changing the numerical value of register 5.The output of single-chip microcomputer 3 also is connected with the control end of MUX 4, and single-chip microcomputer 3 is controlled road input and output of MUX 4 to output.
Embodiment bis-
The present embodiment is of the present invention a kind ofly specifically optimizes structure.As Fig. 2, on the basis of embodiment mono-, each unit also comprises state machine 10 and adder 9 further.The input of state machine 10 is connected to the output of comparator 6, and comparator 6 is for the cycle of states of starting state machine 10; An output of state machine 10 is connected with the control end of adder 9, and for starting the operation of adder 9, another output of state machine 10 is connected with the control end that writes of comparator 6, is used for controlling the output of adder 9 is write to comparator 6.
Two inputs of adder 9 are connected with the output port of register 5 with comparator 6 respectively, be used for the interior setting value of comparator 6 and register 5 numerical value additions, the output port of adder 9 is connected with the data-in port of comparator 6, and the output valve of adder 9 is updated to comparator 6.
Global positioning system ground receiver 8 wherein can be the GPS ground receiver, it can be also Big Dipper ground receiver, it can be also the GLONASS ground receiver, the limited amount of the ground receiver that device is supported is in the operational capability of single-chip microcomputer 3 and the size of FPGA resource, from not restriction of principle, in the accompanying drawing of above-mentioned two embodiment example access respectively the situation of GPS and Big Dipper ground receiver.
High stability crystal oscillator 1 in device provides stable frequency signal for whole system, in actual design, and the general constant-temperature crystal oscillator that adopts of high stability crystal oscillator 1.The effect of phaselocking frequency multiplier 2 is that the frequency values of the frequency signal of constant-temperature crystal oscillator 1 output is improved, and higher frequency values is conducive to improve the temporal resolution of counter, improves the precision to the constant-temperature crystal oscillator frequency measurement, reduces the shake of output pps pulse per second signal.
From figure Fig. 2, can see, contain the identical several function groups of logic function group (being described unit) in FPGA, each function group comprises a counter 7, a comparator 6, a register 5, an adder 9, also having a state machine 10, counter 7 wherein to take the high-frequency signal of phaselocking frequency multiplier output 2 is clock.FPGA also contains a MUX 4, the time signal output selectively selected function group produced by this MUX 4.Such system configuration is specially adapted to produce the time synchronizing signal that meets the electric power system special use.Below to the function of this system and advantage, divide several aspects to set forth:
1. device of the present invention can provide support to multiple time recovery algorithms, can realize the source optimizing of many times and complete the output of preferred time signal.
After the locking of global positioning system ground receiver, the pps pulse per second signal of output is introduced in counter, it is clock that counter be take the high-frequency signal of phaselocking frequency multiplier output, record count value corresponding to each pulse per second (PPS), single-chip microcomputer reads in rear preservation by these count values, form a count value sequence, this count value sequence had both comprised the information of the current frequency of oscillation of constant-temperature crystal oscillator, the information that has also comprised the pulse per second (PPS) random error distribution of global positioning system ground receiver output, take this count value as basis, by certain algorithm, just can calculate accurately the frequency Z after the current frequency multiplication of constant temperature crystal, and can complete the count value corresponding to next pulse per second (PPS) best estimate X(each the time corresponding one of source), can also estimate simultaneously each ground receiver output pulse per second (PPS) standard deviation W(each the time corresponding one of source).
The single-chip microcomputer per second calculates and refreshes once above-mentioned parameter, after completing the calculating of above-mentioned parameter, the standard deviation of the pulse per second (PPS) that all global positioning system ground receivers are exported compares, choose a wherein road of standard deviation minimum, by this Lu Shiyuan, corresponding parameter X writes corresponding comparator, and MUX is set to should the road gating simultaneously.When rolling counters forward arrives X, comparator will be rebuild and produce pps pulse per second signal, and this signal will be exported by MUX, as the pps pulse per second signal of the final output of device.
Above process is the situation that has multichannel global positioning system ground receiver simultaneously to lock, when for a certain reason, a certain road receiver losing lock, searching process is exited on the Ze Gai road automatically, single-chip microcomputer only carries out optimizing to the time source of locking, when only having a road ground receiver locking, the ground receiver of system Jiang Gai road locking as the time source.If all global positioning system ground receivers are losing lock all, device enters punctual state.
2. the present invention can give security to high accuracy is punctual.
At device, the frequency Z after global positioning system ground receiver when locking, single-chip microcomputer continue to calculate the constant temperature crystal frequency multiplication is arranged, estimates next pulse per second (PPS) count value X, and to the time source carry out optimizing.When institute source all after losing lock sometimes, device keep before losing lock last effectively the time source be effectively output, the counter that maintains this group continues stored counts, use losing lock before the last frequency Z calculated carry out keeping time of device.
3. the present invention can guarantee stability and the continuity of single-chip microcomputer reseting period clock output signal.
As shown in Figure 2, a state machine, a register and an adder are arranged in each function group of this device, these 3 modules can maintain the output of clock signal by assurance device when the single-chip microcomputer unexpected reset.Method is: after the frequency values that the each clearing of the single-chip microcomputer in device make new advances, all its integer part is write in register corresponding to this road, after each pulse per second (PPS) output, capital causes state machine commander adder after the data addition in comparator and register, result to be updated in comparator, if single-chip microcomputer is working properly, single-chip microcomputer can replace this value with the numerical value that oneself generates pulse per second (PPS) in next second subsequently, accuracy when assurance device is walked.If single chip microcomputer halt at this moment, the numerical value that writes comparator will can not be modified, and device can be used this value to generate the pulse per second (PPS) of next second, at single-chip microcomputer, restart during this period of time in, when state machine is used the integer value of system frequency to maintain away command system, until the single-chip microcomputer adapter system.
The integer part of a proportion while keeping time due to the state machine command device, the system that is the 100MHz left and right for frequency after above-mentioned frequency multiplication, the error per second caused blocked after decimal is no more than 10ns, punctual precision is equivalent to 36 μ s/h, be better than the requirement of the punctual precision 55 μ s/h of electric power system industry standard, but the precision of 1 μ s/h when normally punctual far below system.Consider that when device normally moves, monolithic processor resetting is the event of minimum probability and is generally a second level resetting time, so, by this technology, can walk the magnitude of time error in tens nanoseconds by assurance device during monolithic processor resetting, the standard deviation of the time signal of this precision level and most global positioning system ground receiver output, at an order of magnitude, can say that the error caused thus can perceive hardly.
4. the present invention provides support means flexibly for TEC time error correction.
Due to the pulse per second (PPS) of this device output by counter values with the comparator numeric ratio to generation, can support neatly the TEC time error correction strategy of multiple strategy.Here only with leapfrog compensation and linearity, pursuing and attacking two kinds of methods of compensation is illustrated.
For leapfrog, compensate, suppose device is because punctual operation causes system time and standard time to fall behind 7.9 μ s, after device relocks, device can calculate the best estimate of next second that generates the corresponding standard time, this timer is the difference with the corresponding comparator numerical value of previous punctual pulse per second (PPS) regardless of this estimated value, directly by this estimated value, generate follow-up pps pulse per second signal, system will disposablely will be installed due to punctual and be caused the clocking error compensation complete, the method compensation speed is fast, but all errors are complete interval compensation second, can cause the time interval fluctuation in this second in the compensation moment large, be unsuitable for using in the digital transformer substation occasion.
Pursue and attack compensation for linearity, after the device locking, when the best estimate of next second that discovery calculates and the difference of upper one second are excessive (such as threshold value is made as 0.2 μ s), at this moment, device is not directly to use this estimated value to generate next pulse per second (PPS), but limit the excursion of next pulse per second (PPS) estimated value, make per second be no more than a limit value (such as 0.2 μ s) to compensation of error, pursue and attack by follow-up continuous error compensation like this, the device clock was progressively adjusted to the standard time and synchronizeed.The method is longer lock in time, but the pulse per second (PPS) interval of output is more even, is conducive to the stable operation of digital transformer substation.
Claims (2)
1. source optimizing of many times time synchronism apparatus, it is characterized in that: this device comprises high stability crystal oscillator (1), single-chip microcomputer (3) and MUX (4); Also comprise at least two unit that structure is identical, each unit comprises global positioning system ground receiver (8), counter (7), comparator (6) and register (5), in each unit, the pulse per second (PPS) output of global positioning system ground receiver (8) is connected with the Event triggered input of counter (7), and the count value output of counter (7) connects the input of the comparator (6) in this unit; Directly be connected or connect by phaselocking frequency multiplier (2) between the input end of clock of the output terminal of clock of high stability crystal oscillator (1) and counter (9) in each unit; The pulse output end of comparator in each unit (6) accesses respectively an input of MUX (4); Counter in each unit (7), comparator (6) and register (5) are connected with single-chip microcomputer (3) respectively; The output of single-chip microcomputer (3) also is connected with the control end of MUX (4).
2. source optimizing of many times as claimed in claim 1 time synchronism apparatus is characterized in that: each unit also comprises state machine (10) and adder (9); The input of state machine (10) is connected to the output of comparator (6), and comparator (6) is for the cycle of states of starting state machine (10); An output of state machine (10) is connected for starting the operation of adder (9) with the control end of adder (9); Another output of state machine (10) is connected with the control end that writes of comparator (6); Two inputs of adder (9) are connected with the output port of register (5) with comparator (6) respectively, and adder (9) is for the interior setting value by comparator (6) and register (5) numerical value addition; The output port of adder (9) is connected with the data-in port of comparator (6); Another output of state machine (10) is connected with the control end that writes of comparator (6), is used for controlling the output of adder (9) is write to comparator (6).
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| CN103913987A (en) * | 2014-04-26 | 2014-07-09 | 广西电网公司电力科学研究院 | GPS timing system and method for obtaining precise time reference through GPS timing system |
| CN108259108A (en) * | 2018-01-26 | 2018-07-06 | 郑州云海信息技术有限公司 | A kind of homologous clock system of multi node server redundancy and clock selection method |
| CN109991838A (en) * | 2019-03-29 | 2019-07-09 | 南京华苏科技有限公司 | Based on Big Dipper short message master control time service device, system and method |
| CN110198211A (en) * | 2019-04-19 | 2019-09-03 | 中国计量科学研究院 | Frequency time signal integration unit based on the fusion of multi-source frequency time signal |
| CN111399366A (en) * | 2020-03-30 | 2020-07-10 | 中国电子科技集团公司第五十四研究所 | Multi-clock comprehensive time keeping method and multi-rubidium clock time keeping device |
| CN115296769A (en) * | 2022-10-08 | 2022-11-04 | 中国电子科技集团公司第五十四研究所 | High-reliability timing method and device for satellite communication system of TDMA system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103913987A (en) * | 2014-04-26 | 2014-07-09 | 广西电网公司电力科学研究院 | GPS timing system and method for obtaining precise time reference through GPS timing system |
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| CN108259108B (en) * | 2018-01-26 | 2019-09-27 | 郑州云海信息技术有限公司 | A kind of homologous clock system of multi node server redundancy and clock selection method |
| CN109991838A (en) * | 2019-03-29 | 2019-07-09 | 南京华苏科技有限公司 | Based on Big Dipper short message master control time service device, system and method |
| CN109991838B (en) * | 2019-03-29 | 2021-05-04 | 南京华苏科技有限公司 | Beidou short message based master control time service device, system and method |
| CN110198211A (en) * | 2019-04-19 | 2019-09-03 | 中国计量科学研究院 | Frequency time signal integration unit based on the fusion of multi-source frequency time signal |
| CN110198211B (en) * | 2019-04-19 | 2021-12-03 | 中国计量科学研究院 | Time frequency signal synthesis device based on multi-source time frequency signal fusion |
| CN111399366A (en) * | 2020-03-30 | 2020-07-10 | 中国电子科技集团公司第五十四研究所 | Multi-clock comprehensive time keeping method and multi-rubidium clock time keeping device |
| CN111399366B (en) * | 2020-03-30 | 2021-06-22 | 中国电子科技集团公司第五十四研究所 | Multi-clock comprehensive time keeping method and multi-rubidium clock time keeping device |
| CN115296769A (en) * | 2022-10-08 | 2022-11-04 | 中国电子科技集团公司第五十四研究所 | High-reliability timing method and device for satellite communication system of TDMA system |
| CN115296769B (en) * | 2022-10-08 | 2022-12-27 | 中国电子科技集团公司第五十四研究所 | High-reliability timing method and device for satellite communication system of TDMA system |
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