CN104599980A - 晶圆级封装的制造方法 - Google Patents
晶圆级封装的制造方法 Download PDFInfo
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
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- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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Abstract
本发明公开了一种晶圆级封装的制造方法,包括以下步骤:在第一芯片上形成光刻胶;在光刻胶上形成多个开口部,露出第一芯片的功能面;在多个第一芯片的功能面上形成凸点下金属层;去除第一芯片上的光刻胶;将第二芯片的功能凸点与第一芯片上的一部分所述凸点下金属层连接;在第一芯片和所述第二芯片之间形成填充层;在第一芯片上的另一部分的凸点下金属层上植焊球,焊球的顶部高于第二芯片的顶部。本发明在第一芯片上形成凸点下金属层,一部分凸点下金属层上植焊球,另一部分上设置第二芯片,由此组成的芯片结构在后续倒装工艺中,利用了第一芯片上的焊球与第二芯片形成的高度差,在倒装时不会损坏第二芯片,降低了加工过程中的风险。
Description
技术领域
本发明涉及半导体制造方法,尤其涉及一种晶圆级封装的制造方法。
背景技术
随着芯片功能越来越多,对于封装的要求也越来越高,倒装、叠层已经成为趋势。在倒装、叠层的同时,还要求封装厚度尽量薄,这样就一定程度上要求芯片封装时尽量薄,从而造成加工过程的风险。
发明内容
在下文中给出关于本发明的简要概述,以便提供关于本发明的某些方面的基本理解。应当理解,这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分,也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
本发明实施例的目的是针对上述现有技术的缺陷,提供一种在满足芯片封装厚度尽量薄的同时降低加工过程风险的晶圆级封装的制造方法。
为了实现上述目的,本发明采取的技术方案是:
一种晶圆级封装的制造方法,包括以下步骤:
在第一芯片上形成光刻胶;
在所述光刻胶上形成多个开口部,露出所述第一芯片的功能面;
在多个第一芯片的功能面上形成凸点下金属层;
去除第一芯片上的光刻胶;
将所述第二芯片的功能凸点与第一芯片上的一部分所述凸点下金属层连接;
在所述第一芯片和所述第二芯片之间形成填充层;
在所述第一芯片上的另一部分的所述凸点下金属层上植焊球,所述焊球的顶部高于所述第二芯片的顶部。
相比于现有技术,本发明的有益效果至少包括:
在第一芯片上形成凸点下金属层,一部分凸点下金属层上植焊球,再将第一芯片和第二芯片面对面设置,由此组成的芯片结构在后续倒装工艺中,利用了第一芯片上的焊球与第二芯片形成的高度差,就可以将芯片结构倒装,而不破坏芯片结构,即倒装时不会损坏第二芯片,降低了加工过程中的风险。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的晶圆级封装的制造方法的流程图;
图2为本发明实施例提供的第一步在第一芯片上涂光刻胶的结构示意图;
图3为本发明实施例提供的第二步涂层曝光和显影后的结构示意图;
图4为本发明实施例提供的第三步形成凸点下金属层的结构示意图;
图5为本发明实施例提供的第四步去除光刻胶后的的结构示意图;
图6为本发明实施例提供的第五步倒装芯片回流后的结构示意图;
图7为本发明实施例提供的第六步形成填充层的结构示意图;
图8为采用本发明晶圆级芯片制作方法制造的晶圆级芯片结构的一种结构示意图;
图9为采用本发明晶圆级芯片制作方法制造的晶圆级芯片结构的另一种结构示意图。
附图标记:
1-第一芯片;2-第二芯片,21-功能凸点;3-凸点下金属层;4-焊球;5-填充层;6-光刻胶;61-开口部。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
在本发明以下各实施例中,实施例的序号和/或先后顺序仅仅便于描述,不代表实施例的优劣。对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。
参见图1,一种晶圆级封装的制造方法,包括以下步骤:
S101:在第一芯片1上形成光刻胶6(参见图2);
S102:在光刻胶2上形成多个开口部61,露出第一芯片1的功能面(参见图3);
S103:在多个第一芯片1的功能面上形成凸点下金属层3(参见图4);
S104:去除第一芯片1上的光刻胶6(参见图5);
S105:将第二芯片2的功能凸点21与第一芯片1上的一部分凸点下金属层3连接(参见图6);
S106:在第一芯片1和所述第二芯片2之间形成填充层5(参见图7);
S107:在第一芯片1上的另一部分的凸点下金属层5上植焊球4,焊球4的顶部高于第二芯片2的顶部(参见图8和图9)。
参见图8和图9,优选地,第一芯片1上的一部分凸点下金属层3位于第一芯片1的中间部位,第一芯片1上的另一部分的凸点下金属层3位于第二芯片2的四周。位于第二芯片2的四周的焊球4可以是一层,也可以是如图9所示的两层。
在一种可选的实施方式中,以第一芯片1的上表面为基准面,焊球4顶部与所述基准面之间的高度为180-220微米;第二芯片2顶部距所述基准面的高度小于150微米。
在一种可选的实施方式中,焊球4顶部与所述基准面之间的高度为200微米,第二芯片2顶部与焊球4的顶部的距离为50微米。
在一种可选的实施方式中,在第一芯片1上形成光刻胶6之前,先在第一芯片1上形成保护层,之后在保护层上表面形成所述光刻胶6(图中未示出);开口部61露出所述功能面上的保护层;凸点下金属层3形成于从开口部61露出的保护层的上表面;这里应该知晓,既然凸点下金属层3形成在了保护层的上表面,那么该保护面应该是能够导通凸点下金属层3与第一芯片1的。保护层上表面中,形成有凸点下金属层3的部分为第一部分,未形成所述凸点下金属层3的为第二部分,去除光刻胶6后,再去除第二部分。
本发明的保护层采用PVD(Physical Vapor Deposition,物理气相沉积)的方法形成镀膜层,其工作原理是在真空条件下,利用气体放电使气体或被蒸发物质部分离化,在气体离子或被蒸发物质离子轰击作用的同时把蒸发物或其反应物沉积在基底上。具有沉积速度快和表面清洁的特点,特别具有膜层附着力强、绕射性好、可镀材料广泛等优点。
本实施例中,开口部61是经曝光和显影后形成的。
优选地,焊球4可为锡球。
上述填充层5为树脂层,即用树脂材料进行填充。
本发明通过控制第二芯片倒装后的总体高度小于150微米,与焊球形成50微米的高度差,可以在进行芯片以WLCSP(Wafer Level ChipScale Packaging,晶圆级芯片封装方式)方式的倒装时,不损坏第二芯片,降低了加工过程中的风险。
另外,本发明的制作工艺是以圆片为基础进行的,对位的精度和生产的效率也会得到提高。
最后应说明的是:虽然以上已经详细说明了本发明及其优点,但是应当理解在不超出由所附的权利要求所限定的本发明的精神和范围的情况下可以进行各种改变、替代和变换。而且,本发明的范围不仅限于说明书所描述的过程、设备、手段、方法和步骤的具体实施例。本领域内的普通技术人员从本发明的公开内容将容易理解,根据本发明可以使用执行与在此所述的相应实施例基本相同的功能或者获得与其基本相同的结果的、现有和将来要被开发的过程、设备、手段、方法或者步骤。因此,所附的权利要求旨在在它们的范围内包括这样的过程、设备、手段、方法或者步骤。
Claims (8)
1.一种晶圆级封装的制造方法,其特征在于,包括以下步骤:
在第一芯片上形成光刻胶;
在所述光刻胶上形成多个开口部,露出所述第一芯片的功能面;
在多个第一芯片的功能面上形成凸点下金属层;
去除第一芯片上的光刻胶;
将所述第二芯片的功能凸点与第一芯片上的一部分所述凸点下金属层连接;
在所述第一芯片和所述第二芯片之间形成填充层;
在所述第一芯片上的另一部分的所述凸点下金属层上植焊球,所述焊球的顶部高于所述第二芯片的顶部。
2.根据权利要求1所述的晶圆级封装的制造方法,其特征在于:所述第一芯片上的一部分所述凸点下金属层位于所述第一芯片的中间部位,所述第一芯片上的另一部分的所述凸点下金属层位于所述第二芯片的四周。
3.根据权利要求1所述的晶圆级封装的制造方法,其特征在于:
以所述第一芯片的上表面为基准面,所述焊球顶部与所述基准面之间的高度为180-220微米;
所述第二芯片顶部距所述基准面的高度小于150微米。
4.根据权利要求3所述的晶圆级封装的制造方法,其特征在于:
所述焊球顶部与所述基准面之间的高度为200微米,所述第二芯片顶部与所述焊球的顶部的距离为50微米。
5.根据权利要求1所述的晶圆级封装的制造方法,其特征在于:
在第一芯片上形成光刻胶之前,先在所述第一芯片上形成保护层,之后在保护层上表面形成所述光刻胶;
所述开口部露出所述功能面上的保护层;
所述凸点下金属层形成于从所述开口部露出的保护层的上表面;
所述保护层上表面中,形成有所述凸点下金属层的部分为第一部分,未形成所述凸点下金属层的为第二部分,去除所述光刻胶后,再去除所述第二部分。
6.根据权利要求1-5任一项所述的晶圆级封装的制造方法,其特征在于:所述开口部是经曝光和显影后形成的。
7.根据权利要求1-5任一项所述的晶圆级封装的制造方法,其特征在于:
所述焊球为锡球。
8.根据权利要求1-5任一项所述的晶圆级封装的制造方法,其特征在于:
所述填充层为树脂层。
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