CN103123917B - 导电结构及其形成方法 - Google Patents

导电结构及其形成方法 Download PDF

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Publication number
CN103123917B
CN103123917B CN201210052495.3A CN201210052495A CN103123917B CN 103123917 B CN103123917 B CN 103123917B CN 201210052495 A CN201210052495 A CN 201210052495A CN 103123917 B CN103123917 B CN 103123917B
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layer
opening
liner
underbump metallization
conductive
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CN103123917A (zh
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沈更新
齐中邦
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Abstract

本发明关于一种用于一半导体芯片的导电结构及其形成方法，半导体芯片包含一半导体基材、一衬垫、一保护层及一图案化绝缘层，图案化绝缘层设置于保护层上并局部且直接覆盖于衬垫的一第一开口上以使衬垫暴露出一第二开口，其中第一开口大于第二开口。导电结构包含一凸块下金属层及一导电凸块，凸块下金属层设置于图案化绝缘层所形成的第二开口内并与衬垫电性连接，导电凸块设置于凸块下金属层上并与凸块下金属层电性连接。其中，导电凸块的一上表面高于图案化绝缘层的一上表面，并且导电凸块位于第二开口内的区域是被凸块下金属层所包覆。

Description

导电结构及其形成方法
技术领域
本发明是关于一种导电结构及其形成方法，特别是关于一种用于一半导体芯片的导电结构及其形成方法。
背景技术
倒装芯片(Flip Chip)封装已逐渐成为半导体封装的主流制程，而倒装焊技术，即是将芯片(Chip)的正面倒置(Flip)后，再利用芯片上所形成的凸块(Bump)作为芯片与对向基板(Substrate)上的电路电性连结的桥梁，因此作为导电结构的凸块，其品质良莠便为半导体封装产品整体效能的重要关键。
图1A至1F所示为已知凸块结构及其形成步骤。首先如图1A所示，芯片11由基材111、衬垫112及保护层113所组成，而保护层113会形成一第一开口113a，以局部曝露出衬垫112。
为使凸块能顺利附着于衬垫112上，如图1B所示，需要先行形成凸块下金属层(Under Bump Metal，UBM)121于保护层113上，并且凸块下金属层121透过保护层113所形成的第一开口113a与衬垫112电性相接，借此凸块下金属层121不但具有接合凸块与衬垫112的功用外，亦作为凸块与衬垫112间的导电媒介。
随后，请参阅图1C，形成绝缘层122于凸块下金属层121上，再视设计需求，使用光阻剂，以于衬垫112上方位置图案化形成适当的第二开口122a，以便后续进行凸块植入步骤。
因此，如图1D所示，可视设计需求，使用电镀或蒸镀或其他制程，形成凸块123于绝缘层122的第二开口122a内，并且凸块123透过凸块下金属层121与衬垫112构成电性相接。
由于凸块123植入步骤完成后，绝缘层122阶段性任务已完成，如图1E所示，即可去除不需要的绝缘层122。
最后，为了阻断基材111内的晶片元件透过凸块下金属层121与外部元件产生电性传导的机会，如图1F所示，将以一蚀刻(UBM Etching)制程去除凸块123底部以外的凸块下金属层121，便完成已知芯片11的凸块结构。
然而上述制程中，绝缘层122及其所定义的第二开口122a仅是作为后续植入凸块123的前置步骤，是故于形成凸块123后，绝缘层122便无存在的必要，造成绝缘层122无法妥善运用外，还必须花费多道程序及成本，以光阻剂去除(PR Stripper)绝缘层122，然后再清洗芯片11表面残留的光阻剂或异物后，才能继续进行去除凸块下金属层121的步骤。
此外，凸块下金属层121通常由二层金属所组成，已知技术是借由此等金属的导电性及各金属层的不同元素特性，作为接合衬垫112与凸块123之间的粘着层。然而，已知凸块下金属层121仅经由二金属层的表面与衬垫112及凸块123进行接合，倘若遇到二金属层的制程控制品质不佳时，便容易造成凸块下金属层121与凸块123之间或是凸块下金属层121与衬垫112之间产生裂缝，造成凸块123的导电效果不稳定，进而影响整体芯片11的工作效能。
有鉴于此，如何提高凸块品质及降低整体制程的成本，乃为此一业界日益重视的问题。
发明内容
本发明的一目的在于提供一种使用于半导体芯片的导电结构，半导体芯片包含一半导体基材、一衬垫、一保护层及一图案化绝缘层，衬垫设置于半导体基材上，保护层设置于半导体基材及衬垫上以使衬垫暴露出一第一开口，图案化绝缘层设置于保护层上并局部且直接覆盖于衬垫的第一开口上以使衬垫暴露出一第二开口，其中第一开口大于第二开口。而导电结构包含一凸块下金属层及一导电凸块，凸块下金属层设置于图案化绝缘层所形成的第二开口内并与衬垫电性连接，导电凸块设置于凸块下金属层上并与凸块下金属层电性连接；其中，导电凸块的一上表面高于图案化绝缘层的一上表面，由于本发明的导电凸块位于图案化绝缘层所形成的第二开口内的区域被凸块下金属层所包覆，因此导电凸块、凸块下金属层及衬垫三者间不但可稳定的结合，亦具有良好的导电传导效果。
本发明的另一目的在于提供一种导电结构的制造方法，特别是一种可降低整体制程成本的导电结构。为达此前述目的，本发明的导电结构的制造方法包含：形成一图案化绝缘层于一半导体芯片的一保护层上并局部且直接覆盖于一衬垫的一第一开口上，以使衬垫暴露出一第二开口，第一开口大于第二开口，其中半导体芯片包含一半导体基材、一衬垫及一保护层，衬垫设置于半导体基材上，保护层设置于半导体基材及衬垫上以使衬垫暴露出第一开口；形成一凸块下金属层，覆盖图案化绝缘层及其所形成的第二开口内，以与衬垫电性连接；形成一导电凸块于第二开口中以与凸块下金属层电性连接，其中凸块下金属层包覆导电凸块的一周围；去除凸块下金属层的一外部区域层，使导电凸块的一上表面高于凸块下金属层的一上表面，并且导电凸块位于第二开口内的区域系被凸块下金属层所包覆；换言之，导电凸块在不高于图案化绝缘层的区域系被凸块下金属层所包覆。其中外部区域层系指位于第二开口的外的区域。
本发明借由改变已知导电结构的制程顺序，并保留已知技术中会被去除的绝缘层，借以作为导电结构的固定辅助元件以及半导体芯片的绝缘阻隔层，借此不但可增加导电结构的导电稳定性，并可减少不必要的制程步骤，以达节省成本的功效。
附图说明
为让本发明的上述目的、特征和优点能更明显易懂，以下结合附图对本发明的具体实施方式作详细说明，其中：
图1A至1F是已知导电结构及其制造方法的示意图；
图2A至2D是本发明的导电结构及其制造方法的示意图；以及
图3为应用本发明的导电结构的半导体芯片与基板的连接示意图。
主要元件符号说明：
111   基材
112   衬垫
113   保护层
113a  第一开口
121   凸块下金属层
122   绝缘层
122a  第二开口
123   凸块
21    半导体芯片
211   半导体基材
212   衬垫
213   保护层
213a  第一开口
214   图案化绝缘层
214a  第二开口
214s  上表面
22    导电结构
23    凸块下金属层
23s   上表面
231   第一导体层
232   第二导体层
233   外部区域层
24    导电凸块
24s   上表面
31    对向基板
具体实施方式
以下将透过实施例来解释本发明内容，然而，关于实施例中的说明仅为阐释本发明的技术内容及其目的功效，而非用以直接限制本发明。须说明的是，以下实施例以及图示中，与本发明非直接相关的元件已省略而未绘示；且图示中各元件的尺寸及相对位置关系仅用以示意以便了解，非用以限制实施比例及尺寸大小。
图2A至2D是本发明较佳实施例的导电结构22的制造流程示意图，其中图2D为制造完成后的导电结构22示意图。如图2D所示，本实施例的导电结构22包含凸块下金属层23及导电凸块24，凸块下金属层23设置于图案化绝缘层214所形成的第二开口214a内并与衬垫212电性连接，导电凸块24设置于凸块下金属层23上并与凸块下金属层23电性连接。其中，导电凸块24的上表面24s高于图案化绝缘层214的上表面214s，且导电凸块24位于第二开口214a内的区域是被凸块下金属层23所包覆，亦即凸块下金属层23包覆了导电凸块24的上表面214s以外的区域。
于本实施例中，导电凸块24的上表面24s高于图案化绝缘层214的上表面214s约2至5微米(micrometer)。而凸块下金属层23包含第一导体层231及第二导体层232，第一导体层231设置于第二开口214a内并与衬垫212电性连接；第二导体层232设置于第一导体层231上并与第一导体层231电性连接。
图2A至图2D所示为前述实施例的导电结构的制造方法流程示意图，以下将依照制程顺序配合图式依序说明。
首先，请参阅图2A，半导体芯片21包含一半导体基材211、一衬垫212、一保护层213及一图案化绝缘层214，衬垫212是设置于半导体基材211上，保护层213是设置于半导体基材211及衬垫212上，并暴露出衬垫212的一部分以定义出一第一开口213a。如同所属技术领域技术人员所了解，衬垫212的材质较佳可由金、铜或其他金属所制成，以作为半导体芯片21与外界电性传导的接点。
在此特别说明的是，有别于已知导电结构制程是依序先形成凸块下金属层、图案化绝缘层后，再形成导电凸块；本发明制程的一特点即在于，先将图案化绝缘层214形成于保护层213上并局部且直接覆盖于衬垫212的第一开口213a上，并暴露出衬垫212而于衬垫212上形成另一开口，即前述的第二开口214a，其中第一开口213a大于第二开口214a。于本实施态样中，图案化绝缘层214的材料较佳选自聚酰亚胺(Polyimide，PI)、阻焊层(Solder Resist，SR)、苯环丁烯(Benzocyclobutene，BCB)或硅氧烷聚合物(siloxane polymers，SINR)，然后视实际需求，可利用一掩模光刻制程或一蚀刻制程，以图案化形成第二开口214a，再进一步固化(cured)前述图案化绝缘层214。在此补充说明，于本实施例中所使用的硅氧烷聚合物(siloxane polymer)为Shin-Etsu化学有限公司所制造的SINR系列材料。
请进一步参考图2B，完成图案化绝缘层214的步骤后，便可形成凸块下金属层23以覆盖于图案化绝缘层214上以及图案化绝缘层214所形成的第二开口214a内；借此凸块下金属层23可透过图案化绝缘层214所形成的第二开口214a，以与衬垫212电性连接。
更明确而言，凸块下金属层23分别由第一导体层231及第二导体层232所组成。先形成第一导体层231以覆盖于图案化绝缘层214上及第二开口214a内，并与衬垫212电性连接；再形成第二导体层232以覆盖于第一导体层231上，并与第一导体层231电性相接。如同所属技术领域具有通常知识者所了解，第一导体层231较佳选自一钛、钨、钒或其合金所制成，除了可防止第二导体层232与衬垫212的金属扩散，同时更强化彼此间的附着力；而第二导体层232较佳选自金、铜、银或其合金所制成，以增加衬垫212与导电凸块间的电性传导；然而本发明的第一导体层及第二导体层所选用的材料并不以上述为限，凡具有导电特性的材料均可作为本发明的应用。
请进一步参考图2C，形成导电凸块24于第二开口214a中以与凸块下金属层23电性连接，而导电凸块24被凸块下金属层23所包覆。更明确而言，形成导电凸块24的方式，较佳系以电镀方式所制成，其中导电凸块24系可为金、铜、银、镍或其合金所制成；于其他实施态样中，导电凸块可为具导电性的高分子凸块，其中具导电性的高分子凸块为印刷(Printing)或点胶方式所形成。
为了方便说明，如图2C所示，在此将第二开口214a以外的区域界定为一外部区域层233；详言之，外部区域层233系指图案化绝缘层214上方的凸块下金属层23。由于现阶段导电凸块24整体被凸块下金属层23所包覆，尚无法与外界的基板进行接合，因此必须去除外部区域层233。更明确而言，由于导电凸块24的硬度高于凸块下金属层23，故凸块下金属层23的外部区域层233内更容易被去除；因此，接下来将借由一研磨法(Lapping)、一等离子蚀刻法(Plasma Etching)或一化学机械研磨法(Chemical Mechanical Polishing，CMP)来去除凸块下金属层23的外部区域层233。去除外部区域层233后，如第2D图所示，导电凸块24的上表面24s便高于凸块下金属层23的上表面23s，并且导电凸块24位于第二开口214a内的区域系被凸块下金属层23所包覆。更明确而言，图案化绝缘层214上方的凸块下金属层23已经移除，只剩下第二开口214a内的凸块下金属层23包覆着导电凸块24，而凸块下金属层23的上表面23s则与图案化绝缘层214的上表面214s齐平。因此，完成后的导电结构22，图案化绝缘层214的厚度约2至20微米，而导电凸块24的上表面24s高于图案化绝缘层214的上表面214s约2至5微米。最后，如图3所示，导电结构22的导电凸块24便可与对向基板31的电路(图未示出)进行接合。
相较于已知的导电结构制程，移除不必要的图案化绝缘层，本发明的导电结构特别保留图案化绝缘层并进一步固化后，以作为半导体芯片与外部基板之间的阻隔层，具有减少制程并妥善运用图案化绝缘层的使用功能。
此外，由于凸块下金属层包覆着导电凸块的下半部，再由固化后的图案化绝缘层支撑着凸块下金属层及导电凸块，除了增加导电凸块与凸块下金属层之间的导电面积外，也加强凸块下金属层的接合结构，避免导电凸块与凸块下金属层间或者衬垫与凸块下金属层间产生裂缝，因此本发明的半导体芯片及导电结构具有较高的良率及良好导电效果。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的修改和完善，因此本发明的保护范围当以权利要求书所界定的为准。

Claims (16)

1.一种用于一半导体芯片的导电结构，半导体芯片包含一半导体基材、一衬垫、一保护层及一图案化绝缘层，衬垫设置于半导体基材上，保护层设置于半导体基材上并局部覆盖衬垫而形成一第一开口，并使第一开口暴露出衬垫，图案化绝缘层设置于保护层上并局部且直接覆盖于衬垫的第一开口上而形成一第二开口，并使第二开口暴露出衬垫，第一开口大于第二开口，导电结构包含：
一凸块下金属层，设置于图案化绝缘层所形成的第二开口内并与衬垫电性连接，其中凸块下金属层的一第一上表面与图案化绝缘层的一第二上表面齐平；以及
一导电凸块，设置于凸块下金属层上并与凸块下金属层电性连接，
其中，导电凸块的一第三上表面高于图案化绝缘层的该第二上表面，其中导电凸块位于第二开口内的区域是被凸块下金属层所包覆。
2.如权利要求1所述的导电结构，其特征在于，导电凸块的该第三上表面高于图案化绝缘层的该第二上表面2至5微米。
3.如权利要求1所述的导电结构，其特征在于，图案化绝缘层为聚酰亚胺、阻焊层、苯环丁烯或硅氧烷聚合物。
4.如权利要求1所述的导电结构，其特征在于，图案化绝缘层的厚度2至20微米。
5.如权利要求1所述的导电结构，其特征在于，导电凸块为金、铜、银、镍或其合金所制成。
6.如权利要求1所述的导电结构，其特征在于，导电凸块为一导电高分子凸块。
7.如权利要求6所述的导电结构，其特征在于，导电高分子凸块为印刷(Printing)或点胶方式所形成。
8.如权利要求1所述的导电结构，其特征在于，凸块下金属层包含：
一第一导体层，设置于第二开口内并与衬垫电性连接；以及
一第二导体层，设置于第一导体层上并与第一导体层电性连接。
9.如权利要求8所述的导电结构，其特征在于，第一导体层为一钛、钨、钒或其合金所制成。
10.如权利要求8所述的导电结构，其特征在于，第二导体层为金、铜、银或其合金所制成。
11.一种导电结构的形成方法，包含：
形成一图案化绝缘层于一半导体芯片的一保护层上并局部且直接覆盖于一衬垫的一第一开口上而形成一第二开口，并使第二开口暴露出衬垫，第一开口大于第二开口，其中半导体芯片包含一半导体基材、一衬垫及一保护层，衬垫设置于半导体基材上，保护层设置于半导体基材上並局部覆蓋衬垫而形成第一开口，并使第一开口暴露出衬垫；
形成一凸块下金属层，覆盖图案化绝缘层及第二开口以与衬垫电性连接，其中凸块下金属层的一第一上表面与图案化绝缘层的一第二上表面齐平；
形成一导电凸块于第二开口中以与凸块下金属层电性连接，其中凸块下金属层包覆导电凸块的一周围；以及
去除凸块下金属层位于第二开口外的一外部区域层，使导电凸块的一第三上表面高于凸块下金属层的该第一上表面，且导电凸块位于第二开口内的区域被凸块下金属层所包覆。
12.如权利要求11所述的形成方法，其特征在于，形成一图案化绝缘层的步骤更包含固化图案化绝缘层的步骤。
13.如权利要求11所述的形成方法，其特征在于，导电凸块的该第三上表面高于图案化绝缘层的该第二上表面2至5微米。
14.如权利要求11所述的形成方法，其特征在于，导电凸块为电镀方式所制成。
15.如权利要求11所述的形成方法，其特征在于，形成一凸块下金属层的步骤包含：
形成一第一导体层以覆盖图案化绝缘层及第二开口并与衬垫电性连接；以及
形成一第二导体层以覆盖第一导体层并与第一导体层电性连接。
16.如权利要求11所述的形成方法，其特征在于，去除凸块下金属层的一外部区域层的步骤是借由一研磨法、一等离子蚀刻法以及一化学机械研磨法其中之一。
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