CN104599971A - 用于制造竖直半导体器件的方法和竖直半导体器件 - Google Patents

用于制造竖直半导体器件的方法和竖直半导体器件 Download PDF

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CN104599971A
CN104599971A CN201410588799.0A CN201410588799A CN104599971A CN 104599971 A CN104599971 A CN 104599971A CN 201410588799 A CN201410588799 A CN 201410588799A CN 104599971 A CN104599971 A CN 104599971A
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hard mask
semiconductor
mask layer
type surface
mesa
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CN104599971B (zh
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P·布兰德尔
M·H·佩里
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

生产竖直半导体器件，包括：提供半导体晶片，其包括第一导电类型的第一半导体层、与第一半导体层形成第一pn结的第二导电类型的第二半导体层以及与第二半导体层形成第二pn结并且延伸到晶片的主表面的第一导电类型的第三半导体层；在主表面上形成硬掩模，该硬掩模包括通过第一开口彼此间隔开的硬掩模部分；使用硬掩模蚀刻从主表面到第一层中的深沟槽，使得在主表面处由相应硬掩模部分覆盖的台面区域被形成在毗邻沟槽之间；填充沟槽和硬掩模的第一开口；以及蚀刻硬掩模以在台面的主表面处的硬掩模中形成第二开口。

Description

用于制造竖直半导体器件的方法和竖直半导体器件
技术领域
本发明的实施例涉及用于制造竖直半导体器件的方法，具体地涉及竖直场效应半导体器件。
背景技术
半导体器件，尤其是诸如金属氧化物半导体场效应晶体管(MOSFET)和绝缘栅双极型晶体管(IGBT)之类的场效应控制的开关器件已经用于各种应用中，包括(但不限于)用作电源供应和电源转换器、电动汽车、空调以及甚至立体声***中的开关。
具体关于电源应用而言，常常就在低芯片面积A下的低导通电阻Ron(具体地Ron乘以A的低乘积)、快速开关和/或低开关损耗来优化半导体器件。此外，常常要保护半导体器件免受可以出现在开关例如电感负载期间的高电压峰。
使用用于形成本体区域和相反掺杂类型的源极区域的双扩散过程制造的具有沟道结构的DMOSFET(双扩散金属氧化物半导体场效应晶体管)常常被使用，尤其是在大电流和/或高电压下操作的电源电路中。到目前为止，DMOSFET被实现为平面DMOSFET(即具有平面栅极电极结构的DMOSFET)或者其中绝缘栅极电极形成在延伸到半导体衬底中的沟槽中的沟槽DMOSFET。平面DMOSFET在给定的Ron下要求相对大的芯片面积A，并且从而是相对昂贵的。这尤其适用于具有高于30V的额定击穿电压的平面MOSFET。由于沟槽MOSFET(T-MOSFET)的MOS沟道被设计成沿着沟槽的通常竖直的壁，沟槽DMOSFET的单元节距可以被做成小的，从而导致在给定Ron下的相对小的芯片面积A。然而，对于T-MOSFET通常比对于平面MOSFET的制造更加复杂。通常，T-MOSFET降低的芯片面积比较高的处理成本重要。然而，例如汽车应用中的能量有限的产品和/或要求进一步的信号焊盘和布线的所谓的多芯片产品可能不完全受益于T-MOSFET结构的降低的需求芯片面积，因为需求特定的芯片面积以用于在换向期间的能量耗散和/或以用于信号焊盘和/或以用于进一步的布线。这增加了产品的成本。
出于这些以及其他原因，存在对本发明的需要。
发明内容
根据用于生产竖直半导体器件的方法的一个实施例，该方法包括：提供半导体晶片，具有主表面并且包括第一导电类型的第一半导体层、与第一半导体层形成第一pn结的第二导电类型的第二半导体层以及与第二半导体层形成第二pn结并且延伸到半导体晶片的主表面的第一导电类型的第三半导体层；在主表面上形成硬掩模，该硬掩模包括通过第一开口彼此间隔开的硬掩模部分；使用硬掩模从主表面向第一半导体层中蚀刻深沟槽，使得在主表面处由硬掩模部分的相应部分覆盖的半导体台面被形成在深沟槽的毗邻沟槽之间；填充深沟槽和硬掩模的第一开口；以及蚀刻硬掩模以在半导体台面的主表面处的硬掩模中形成第二开口。
根据用于生产竖直半导体器件的方法的一个实施例，该方法包括：提供晶片，包括主表面、基本上平行于主表面的第一pn结以及基本上平行于主表面并且被布置在第一pn结与主表面之间的第二pn结；在主表面处形成第一材料的第一硬掩模层；在第一硬掩模层上形成第二材料的第二硬掩模层；在第二硬掩模层上形成包括开口的台面掩模，台面掩模限定半导体衬底中的半导体台面；使用台面掩模蚀刻第一硬掩模层和第二硬掩模层以形成硬掩模，使得在第一区域中暴露主表面并且形成硬掩模部分，每个硬掩模部分包括第二硬掩模层的剩余部分和第一硬掩模层的剩余部分，第一硬掩模层的剩余部分在基本上平行于主表面的方向上具有比第二硬掩模层的剩余部分更大的延伸；使用硬掩模至少从第一区域向第一pn结蚀刻深沟槽以形成半导体台面；以及从主表面的第二区域向半导体台面中蚀刻浅沟槽，主表面的第二区域基本上对应于第二硬掩模层的剩余部分到主表面上的投影。
根据竖直半导体器件的一个实施例，竖直半导体器件包括具有后侧并且在***区域中且在基本上垂直于后侧的竖直方向上从后侧延伸到半导体本体的第一表面的半导体本体、与半导体本体绝缘的多个栅极电极以及被布置在后侧上的后侧金属化结构。在有源区域中半导体本体包括在竖直方向上从第一表面延伸到半导体本体的布置在第一表面上方的主表面的多个间隔开的半导体台面。在竖直截面中，***区域延伸在有源区域与边缘之间，该边缘延伸在后侧与第一表面之间。在竖直截面中，每个半导体台面包括第一侧壁、第二侧壁、延伸在第一侧壁与第二侧壁之间的第一pn结以及与半导体台面欧姆接触并且从主表面延伸到半导体台面中的导电区域。每个栅极电极被布置在成对毗邻的半导体台面之间并且在竖直方向上跨毗邻的半导体台面的第一pn结延伸。
在阅读以下详细描述并且查看附图时，本领域技术人员会意识到另外的特征和优点。
附图说明
图中的部件未必是按比例的，反而把重点放在说明本发明的原理上。而且，在图中，同样的附图标记指定对应的部分。在附图中：
图1至图7图示了在根据一些实施例的方法的方法步骤期间通过半导体本体的竖直截面；并且
图8A至图8D图示了在根据一些实施例的方法的方法步骤期间通过半导体本体的竖直截面。
具体实施方式
在以下详细描述中，参照形成其一部分并且通过图示的方式在其中示出了发明可以被实践在其中的具体实施例的附图。在这点上，诸如“顶”、“底”、“前”、“后”、“引向”、“后面”等之类的方向性术语参照所描述的图的取向定向来使用。因为本发明实施例的部件可以以许多不同定向被定位，所以使用方向性术语以用于图示的目的并且决不是限制性的。要理解的是，可以利用其它实施例并且可以做出结构或逻辑改变而不脱离本发明的范围。因此，以下详细描述不以限制性意义被考虑，并且本发明的范围由所附权利要求来限定。
现在将详细地参照其一个或多个示例被图示在图中的各种实施例。每个示例通过说明的方式提供，并且不意在作为本发明的限制。例如，图示或描述为一个实施例的一部分的特征可以关于或连同其它实施例使用以产生又一实施例。旨在本发明包括这样的修改和变化。使用特定语言描述了示例，这不应被解释为限制所附权利要求的范围。附图不是按比例的，并且仅为了说明性目的。为了清楚起见，如果不另外声明，在不同附图中相同的单元或制造步骤已经由相同的附图标记指定。
如在本说明书中使用的术语“水平”旨在描述大致平行于半导体衬底或本体的主表面的定向。例如，这可以是上表面或前表面，但是还可以是晶片或裸片的较低或后侧表面。
如在本说明书中使用的术语“竖直”旨在描述大致布置为垂直于主表面的定向，即平行于半导体衬底或本体的主表面的法线方向。
如在本说明书中使用的术语“在…上方”和“在…下方”旨在描述在考虑该定向的情况下结构特征到另一结构特征的相对定位。
在本说明书中，n掺杂被称为第一导电类型，而p掺杂被称为第二导电类型。备选地，可以形成具有相反掺杂关系的半导体器件，使得可以p掺杂第一导电类型并且可以n掺杂第二导电类型。此外，一些图通过紧挨掺杂类型地指示“-”或“+”说明了相对掺杂浓度。例如，“n-”意指比“n”掺杂区域的掺杂浓度更小的掺杂浓度，而“n+”掺杂区域具有比“n”掺杂区域更大的掺杂浓度。然而，指示相对掺杂浓度并不意指，相同的相对掺杂浓度的掺杂区域必须具有相同的绝对掺杂浓度，除非另外声明。例如，两个不同的n+掺杂区域可以具有不同的绝对掺杂浓度。相同的情况适用于例如n+掺杂和p+掺杂区域。
本说明书中描述的特定实施例涉及(但不限于)诸如竖直n沟道或p沟道MOSFET或IGBT之类的竖直半导体器件，具体地涉及竖直功率MOSFET和竖直功率IGBT，并且涉及用于制造它们的方法。
在本说明书的上下文中，术语“MOS”(金属氧化物半导体)应当被理解为包括更通用的术语“MIS”(金属绝缘体半导体)。例如，术语MOSFET(金属氧化物半导体场效应晶体管)应当被理解为包括具有非氧化物的栅极绝缘体的FET(场效应晶体管)，即术语MOSFET分别用在IGFET(绝缘栅场效应晶体管)和MISFET(金属绝缘体半导体场效应晶体管)的更通用的术语含义中。
如在本说明书中使用的术语“场效应”旨在描述电场居中的第一导电类型的导电“沟道”的形成和/或第二导电类型的半导体区域(通常第二导电类型的本体区域)中的沟道的导电性和/或形状的控制。由于场效应，通过沟道区域的单极性电流路径形成，和/或被控制在第一导电类型的源极区域与第一导电类型的漂移区域之间。漂移区域可以与漏极区域接触。
在本说明书的上下文中，术语“栅极电极”旨在描述位于沟道区域旁边、并且配置用于形成和/或控制沟道区域的电极。术语“栅极电极”应包含位于本体区域旁边并且通过绝缘区域与本体区域绝缘的电极或导电区域，该绝缘区域形成栅极电介质区域并且配置用于形成和/或通过充电至适当的电压来控制通过本体区域的沟道区域。
通常，栅极电极被实现作为沟槽栅极电极，即作为布置在从主表面延伸到半导体衬底或本体中的沟槽中的栅极电极。
通常，半导体器件是具有用于控制两个负载金属化结构之间的负载电流的多个FET单元(诸如MOSFET单元、IGBT单元和反向导电IGBT单元之类的场效应晶体管单元)的有源区域的功率半导体器件。此外，功率半导体器件可以具有***区域，该***区域具有在从上方看时至少部分地围绕FET单元的有源区域的至少一个边缘端接结构。
在本说明书的上下文中，术语“金属化结构”旨在描述具有相对于导电性的金属或近金属性质的区域或层。金属化结构可以与半导体区域接触，以形成电极、焊盘和/或半导体器件的端子。金属化结构可以由诸如Al、Ti、W、Cu和Mo之类的金属或者诸如NiAl之类的金属合金制成和/或包括这些金属或金属合金，但是金属化结构还可以由具有相对于导电性的金属或近金属性质的材料制成，诸如高掺杂的n型或p型多晶硅、TiN、诸如TaSi2、TiSi2、PtSi、WSi2、MoSi之类的导电硅化物或者诸如AlC、NiC、MoC、TiC、PtC、WC之类的导电碳化物等。金属化结构还可以包括例如那些材料的堆叠的不同导电材料。
在本说明书的上下文中，术语“欧姆接触”、“电阻性电接触”和“电阻性电连接”旨在描述：至少在没有电压或者只有低的测试电压被施加到和/或穿过半导体器件时，在半导体器件的相应单元或部分之间存在欧姆电流路径。同样地，术语“低欧姆接触”、“低电阻性电接触”和“低电阻性电连接”旨在描述：至少在没有电压被施加到和/或穿过半导体器件时，在半导体器件的相应单元或部分之间存在低电阻性欧姆电流路径。在本说明书内，术语“低欧姆接触”、“低电阻性电接触”、“电耦合”和“低电阻性电连接”作为同义词使用。
在本说明书的上下文中，术语“可耗尽区域”和“可耗尽区”旨在描述如下事实：在通过施加的高于给定阈值的反向电压的半导体部件的断开状态期间，对应半导体区域或对应半导体区基本上完全耗尽(基本上没有自由电荷载流子)。出于这一目的，据此设置可耗尽区域的掺杂电荷，并且在一个或多个实施例中，可耗尽区域是弱掺杂区域。在断开状态中，可耗尽区域形成还被称为空间电荷区域的耗尽区域(通常连续的耗尽区)，借此可以阻止连接到半导体本体的两个电极或金属化结构之间的电流流动。
在本说明书的上下文中，术语“半导体台面(mesa)”旨在描述通常从共同半导体衬底或共同半导体层延伸到(或者至少限定)半导体本体或晶片的主表面并且彼此间隔开的若干半导体部分或区之一。通常，在大致正交于主表面的竖直截面中，半导体台面被布置在从主表面延伸到半导体本体或晶片中的两个毗邻的沟槽之间。沟槽可以是大致竖直(竖直沟槽)的，即在竖直截面中，沟槽和半导体台面的侧壁分别可以大致正交于主表面。在竖直截面中，沟槽和半导体台面的两个侧壁分别还可以是锥形的。术语“半导体台面”、“台面区域”和“台面”在本说明书内作为同义词使用。在以下内容中，沟槽和半导体台面的两个侧壁分别还可以被称为第一侧壁和第二侧壁。
典型地，半导体器件包括通过沟槽彼此间隔开的多个半导体台面，并且包括彼此形成pn结的相反导电类型的至少两个半导体区域。更典型地，每个半导体台面包括布置在彼此下方并且在竖直截面中延伸在(或者至少延伸到)第一侧壁和第二侧壁之间的两个pn结(第一pn结和第二pn结)。沟槽可以至少在有源区域中包括延伸在相应第一和第二壁之间的底壁。沟槽通常还包括通过在侧壁处形成栅极电介质区域的相应电介质层与共同衬底和毗邻的台面区域绝缘的导电栅极电极。据此，形成FET结构，其在以下内容中还被称为MesaFET结构。同样地，具有这样的MesaFET结构的竖直半导体器件还被称为MesaFET，分别例如MesaMOSFET和MesaIGBT。
在从上方观察时，功率MesaFET的有源区域的单位单元在水平截面中可以包括沟槽栅极电极和两个邻接台面的相应部分。在这些实施例中，沟槽栅极电极、台面和单位单元可以形成相应的一维栅格(lattice)。
备选地，在沟槽栅极电极形成二维栅格(例如以棋盘的形式)时，在从上方观察时，MesaFET的有源区域的单位单元在水平截面中可以包括沟槽栅极电极和台面的周围部分。
如在本说明书中使用的术语“功率半导体器件”旨在描述在单个芯片上的具有高电压和/或高电流开关能力的半导体器件。换言之，功率半导体器件旨在用于典型地在安培范围内的高电流和/或典型地高于约30°V、更典型地高于约100V、甚至更典型地高于约400V的高电压。
如在本说明书中使用的术语“边缘端接结构”旨在描述提供过渡区域的结构，在过渡区域中半导体器件的有源区域周围的高电场逐渐变成在器件边缘处或靠近器件边缘的电势，和/或在诸如地线之类的参考电势与例如在半导体器件的边缘和/或后侧处的高电压之间。例如，通过跨端接区域散布电场线，边缘端接结构可以降低整流结的端接区域周围的场强度。
在以下内容中，主要参照具有单晶硅(Si)半导体本体的Si半导体器件来说明涉及半导体器件和用于形成半导体器件的制造方法的实施例。据此，如果不另外声明，半导体区域或层通常是单晶Si区域或Si层。
然而，应当理解的是，半导体本体可以由适合用于制造半导体器件的任何半导体材料制成。仅举几例，这些材料的示例包括(但不限于)诸如硅(Si)或锗(Ge)之类的元素半导体材料，诸如碳化硅(SiC)或硅锗(SiGe)之类的IV族化合物半导体材料，诸如氮化镓(GaN)、砷化镓(GaAs)、磷化镓(GAP)、磷化铟(InP)、磷化铟镓(InGaP)、氮化铝镓(AlGaN)、氮化铝铟(AlInN)、氮化铟镓(InGaN)、氮化铝镓铟(AlGaInN)或磷化铟镓砷(InGaAsP)之类的二元、三元或四元III-V族半导体材料，以及诸如碲化镉(CdTe)和碲化汞镉(HgCdTe)之类的二元或三元的II-VI族半导体材料。上面提到的半导体材料还被称为同质结半导体材料。在将两种不同的半导体材料结合时，形成异质结半导体材料。异质结半导体材料的示例包括(但不限于)氮化铝镓(AlGaN)-氮化铝镓铟(AlGaInN)、氮化铟镓(InGaN)-氮化铝镓铟(AlGaInN)、氮化铟镓(InGaN)-氮化镓(GaN)、氮化铝镓(AlGaN)-氮化镓(GaN)、氮化铟镓(InGaN)-氮化铝镓(AlGaN)、硅-碳化硅(SixC1-x)以及硅-SiGe异质结半导体材料。对于功率半导体应用，目前主要使用Si、SiC、GaAs和GaN材料。如果半导体本体由宽带隙材料制成，即由诸如SiC或GaN之类的具有至少约两个电子伏特的带隙并且分别具有高击穿场强度和高临界雪崩场强度的半导体材料制成，可以选择更高的相应半导体区域掺杂，降低导通电阻Ron。
关于图1至图7，在通过半导体本体40的相应竖直截面中图示了用于形成竖直半导体晶体管100的方法的方法步骤。为了清楚起见，每个附图仅图示了通常并行制造在晶片级上的多个半导体器件100之一。出于相同的原因，仅图示了半导体器件100的数个单位单元。
在第一步骤中，提供例如Si晶片之类的在主表面或上表面103与布置成相对于主表面103的后表面102之间延伸的半导体衬底或晶片40。通常，晶片40包括第一导电类型(n型)的第一半导体层1，布置在上方并且与第一半导体层1形成第一pn结14的(p型)第二半导体层2，以及布置在第二半导体层2上方与第二半导体层2形成第二pn结15并且延伸到半导体晶片40的主表面103的(n型)第三半导体层3。
在随后的工艺步骤中，待形成栅极电极，其在竖直方向上跨第一pn结14和第二pn结15延伸，并且通过相应栅极电介质区域与半导体本体40绝缘，使得在器件操作期间可以沿着绝缘的栅极电极并且跨第一pn结14和第二pn结15形成沟道区域。由于在分别形成任何台面和沟槽之前形成第一pn结14和第二pn结15，因此相比于其中在蚀刻沟槽以形成台面之后通过注入形成第一pn结和第二pn结(源极和本体区域)的工艺，通常减少了工艺变化。这是由于如下事实：在分别形成沟槽和台面之前执行时，避免了在注入期间在边缘和步骤处的散射。由于减少的工艺变化，可以减小节距。因此，可以节省芯片面积。
晶片40可以包括延伸到后表面102并且布置在第一半导体层1下方的高掺杂的衬底4(在示例性实施例中n掺杂)。在待制造的半导体器件100中，衬底4及其部分通常分别形成接触层或接触部分4(在制造IGBT时的漏极区域或p掺杂集电极区域)。
根据一个实施例，提供晶片40的步骤包括提供具有高掺杂的衬底4的晶片，在衬底4上形成相同或相反导电类型的一个或多个较低掺杂的外延层，外延层的最上面的表面形成主(水平)表面103，通常从上方不掩蔽地注入p型和n型掺杂剂，以及可选的例如快速热工艺(RTP)的热退火以在一个或多个外延层中形成两个大致水平定向的pn结14、15。通过选择外延层的厚度和/或掺杂浓度，可以设置待制造的半导体器件的类型和电压等级(逻辑电平、正常电平、功率电平)。
此后，可以在主表面103上形成硬掩模层31a、31b、31c的堆叠。
此后，可以在硬掩模层31a、31b、31c上形成台面掩模7。通常台面掩模7限定晶片40中的台面区域。在图1中图示的示例性实施例中，示出了台面掩模7的三个掩模部分7，它们通过第一宽度w1的开口彼此间隔开并且在水平方向上限定了待形成的三个台面区域。也就是说，掩模部分7覆盖待形成的台面。可以依据在有源芯片区域中所设计的台面间距来设置第一宽度w1。在图1中图示所得到的结构100。
在示例性实施例中，针对制造n沟道MOSFET器件来选择掺杂关系。在其中要制造p沟道MOSFET器件的其它实施例中，颠倒掺杂关系。
图1通常仅对应于通过晶片40的小的区段。虚线41分别指示待制造的半导体器件100的竖直定向的侧面边缘和晶片40的锯切边缘。
待制造的不同半导体器件100的两个毗邻掩模部分7之间的间距(通过在竖直截面中的开口)w3通常大于第一宽度w1，以计入锯切的面积损耗和/或布置在有源区域与侧面边缘41之间的***区域，在***区域中可以制造可能使用比有源区域的晶体管单元更大的芯片面积的边缘端接。
通常，第一pn结14和第二pn结15分别大致平行于主表面103和后表面102。在待制造的场效应半导体器件100中，第二半导体层2和第三半导体层3的一些部分可以形成MOSFET单元的本体区域和源极区域。
在图1中图示的示例性实施例中，硬掩模层31被形成为三个层31a、31b、31c的堆叠，通常为ONO堆叠(氧化物-氮化物-氧化物，SiO2-Si3N4-SiO2)。
可以通过用于硅晶片40的热氧化或者通过沉积在主表面103处形成第一硬掩模层31a。
可以通过分别在第一硬掩模层31a和第二硬掩模层31b上的沉积形成第二硬掩模层31b和第三硬掩模层31c。
根据一个实施例，选择硬掩模层的材料，使得对于第一掩模层31a和/或可选的第三掩模层31c而言，第二掩模层31b是选择性可蚀刻的。这使得能够利用仅一种光技术(以形成台面掩模7)形成台面和台面接触。由此可以降低处理成本并且通常进一步减少工艺变化。
此后，使用台面掩模7蚀刻硬掩模层31a、31b、31c。据此，第三半导体层3和晶片40分别暴露在主表面103。
如在图2中图示的那样，第三半导体层3的暴露区域(第一区域)通常大致对应于台面掩模7的开口分别到第三半导体层3和主表面103上的投影。
此外，通常执行蚀刻硬掩模层31a、31b、31c以形成硬掩模31，使得每个硬掩模部分31具有第一部分31a(在以下内容中还被称为较低部分31a)和布置在较低部分31a上的第二部分31b。第一部分31a被布置在主表面103并且具有比第二部分31b的水平延伸p-w2大的水平延伸p-w1，其中p是待形成的单位单元的节距。
根据一个实施例，每个硬掩模部分31进一步具有布置在相应第二部分31b上并且还具有比第二部分31b的水平延伸p-w2小的水平延伸w1的第三部分31c。
在示例性实施例中，硬掩模部分31的第一部分31a和第三部分31c的水平延伸基本上匹配。
可以采用选择性蚀刻来实现形成硬掩模31。例如，三个选择性蚀刻可以用来构造ONO硬掩模层31：对氮化物有选择性的第一缓冲氧化蚀刻(HF蚀刻)，接着是对氧化物有选择性的氮化蚀刻(硝酸蚀刻)和随后的对氮化物有选择性的第二缓冲氧化蚀刻(HF蚀刻)。
由于选择性蚀刻，因此在从上方观察时第二部分31b大致在第一部分31a的中心。这便于随后的台面和台面接触的自调整形成。
通常，形成硬掩模31，使得硬掩模31在边缘区域中的开口在主表面103处具有比有源器件区域中的主表面103处的其它开口38的第一宽度w1大的第三宽度w3。
此后，硬掩模31被用于从主表面103向第一半导体层1中蚀刻深沟槽50、50a。据此，在主表面103处由相应硬掩模部分31覆盖的台面区域20被形成在毗邻的深沟槽50、50a之间。
图3图示了在例如通过热氧化在深沟槽50、50a的侧壁21和底壁22处进一步形成电介质区域33之后所得到的半导体结构100。进一步地，第一pn结14和第二pn结15的剩余部分在台面20的侧壁21之间延伸。
依赖于电压等级，台面20和深沟槽50、50a的竖直延伸hM分别可以在从约500nm到约5μm的范围内，更典型地在从约500nm到约2μm的范围内。
由此可以在限定有源器件区域110的台面区域20中形成源极区域3和本体区域2。
通常，第一半导体层1的通常形成待制造的半导体器件中的共同漂移区域的上部延伸到台面区域20中。
在由较宽的深沟槽50a限定的***区域120中，半导体本体40仅延伸到布置在后表面102与主表面103之间的第一表面101。
***区域120可以围绕有源区域110，并且可以具有在从约30μm至约50μm、至约100μm、或者甚至至约200μm的范围内的水平延伸。
此后可以在深沟槽50、50a中且在电介质区域33上形成栅极电极12、12a。这通常包括沉积诸如掺杂的多晶硅之类的导电材料和局部背蚀刻。在图4中图示所得到的半导体结构100。
相比有源区域110中的栅极电极12，***区域120中的栅极电极12a可以被不同地成形。在阻塞模式期间，栅极电极12a还可以充当场电极。
由于***区域120中降低的上表面101，因此可以不要求另外的边缘端接结构。据此，制造可被简化，并且从而降低成本。
此后，可以沉积诸如TEOS(正硅酸乙酯)之类的对第二掩模层31b(第二部分31b，Si3N4)的材料而言选择性可蚀刻的电介质材料9，并且可以执行在硬掩模31的第二部分31b处停止的CMP处理。在图5中图示所得到的具有完全填充的深沟槽50、50a和硬掩模开口的半导体结构100。可选地，在沉积电介质材料9之前，可以典型地通过热氧化在栅极电极12、12a上形成氧化物层34。
此后，蚀刻剩余的硬掩模31，以使半导体台面20在主表面103处凹进。这通常包括通过选择性蚀刻和各向异性蚀刻第一掩模层31来移除第二部分31b。
此后，可以从主表面103向(或进入)半导体台面20蚀刻浅沟槽51。所得到的半导体结构100图示在图6中。浅沟槽51通常形成接触沟槽并且可以延伸通过第二pn结15。通常，浅沟槽51并不延伸到第一pn结14。
此后，可以在浅沟槽51中形成导电区域或插塞10a。这可以包括在浅沟槽51的侧壁和/或底壁处形成硅化物、沉积诸如多晶硅或金属之类的导电材料和可选的平面化处理。通常，插塞10a与在主表面103上的第一共同金属化结构10(例如源极金属化结构)接触。
此外，可以在主表面103上形成与栅极电极12、12a接触并且与第一共同金属化结构10绝缘的栅极金属化结构(未示出)。
此后，可以在后侧102上形成第二共同金属化结构(后侧金属化结构，漏极金属化结构)11。
此后，通过沿竖直线锯切，可以使形成在晶片40中的若干器件100分离。在图7中图示所得到的三端竖直半导体器件100，并且端子竖直半导体器件100可以作为MOSFET进行操作。
在示例性实施例中，在所制造的半导体器件100中保留硬掩模31的部分31a。
根据一个实施例，所制造的竖直半导体器件100包括具有后侧102并且在***区域120中且在竖直方向上从后侧102延伸到第一表面101的半导体本体40。在有源区域110中，半导体本体40包括在竖直方向上从第一表面101延伸到主表面103的多个间隔开的半导体台面20。在竖直截面中，***区域120延伸在有源区域110与边缘41之间，边缘41延伸在后侧102与第一表面101之间。在竖直截面中，每个半导体台面20具有第一侧壁21、第二侧壁21、延伸在第一侧壁21与第二侧壁21之间的第一pn结14、布置在第一pn结14上方并且延伸在第一侧壁21与第二侧壁21之间的第二pn结15、以及与半导体台面20欧姆接触并且从主表面103延伸到半导体台面20中的导电区域10a。在毗邻的台面区域20之间，布置有与半导体本体40绝缘并且在竖直方向上跨毗邻台面区域20的第一pn结14和第二pn结15延伸的相应栅极电极12。后侧金属化结构11布置在后侧102上。
通常，半导体器件100进一步包括栅极电极12a，其与最外面的半导体台面20绝缘且毗邻并且延伸到***区域120中。
由于制造，因此在从上面观察时导电区域10a相对于半导体台面20大致被置于中心。
关于图8A至图8D，在通过半导体本体40的相应竖直截面中图示了用于形成竖直半导体晶体管100’的方法的方法步骤。为了清楚起见，每个附图仅图示了通常并行制造在晶片级上的多个半导体晶体管100’之一。待制造的半导体晶体管100’类似于上面关于图7说明的半导体器件100。
在第一步骤中，提供了晶片40，其具有主表面103、大致平行于主表面103的第一pn结14以及大致平行于主表面103并且布置在第一pn结14与主表面103之间的第二pn结15。
此后，例如通过热氧化在主表面103处形成第一材料的第一硬掩模层31a。
此后，在第一硬掩模层31上形成与第一材料不同的第二材料的第二硬掩模层31b。
此后，在第二硬掩模层31b上形成具有开口的台面掩模7，台面掩模7限定半导体衬底40中的台面区域20。
此后，使用台面掩模7蚀刻第一硬掩模层31a和第二硬掩模层31b，以形成具有硬掩模部分31的硬掩模31，硬掩模部分31具有第一开口38，从而暴露大致在第一区域中的主表面103处的半导体本体40。在图8A中图示所得到的半导体结构100’。
形成硬掩模31使得每个硬掩模部分31包括第二硬掩模层31b的一部分31b和第一硬掩模层31a的一部分，在水平方向上，第一硬掩模层31a的一部分具有比邻接的第二硬掩模层31b的部分31b更大的延伸p-w1(w2>w1)。
此后，使用硬掩模31从第一区域38至少向第一pn结14蚀刻深沟槽50，以形成半导体台面20。在图8B中图示所得到的半导体结构100’。
此后，填充深沟槽50和硬掩模31的第一开口38。这通常被实现成与上面关于图4和图5说明的类似。在图8C中图示所得到的半导体结构100’。
此后，从与第二硬掩模层31b的部分31b在主表面103上的投影大致对应的第二区域39向半导体台面20中蚀刻浅沟槽51。这通常被实现成与上面关于图6说明的类似。在图8D中图示所得到的半导体结构100’。
通常，浅沟槽51比深沟槽50竖直较浅地延伸到晶片40中。
此后，可以执行类似于上面关于图7说明的进一步的制造步骤，以形成场效应晶体管100’。
上面关于图1至图8D说明的方法还可以被描述为：提供包括第一导电类型的第一半导体层1、与第一半导体层1形成第一pn结14的第二导电类型的第二半导体层2以及与第二半导体层2形成第二pn结15并且延伸到半导体衬底40的主表面103的第一导电类型的第三半导体层3的晶片40；在主表面103上形成堆叠的硬掩模层31a、31b、31c；在硬掩模层31上形成在大致正交于主表面103的截面中包括掩模部分7的台面掩模7，掩模部分7由开口间隔开并且限定了半导体衬底40中的台面区域20；使用台面掩模7蚀刻通过硬掩模层31并且进入晶片40，使得交替的台面区域20和深沟槽50、50a被形成，深沟槽50、50a从主表面103延伸到第一半导体层1中，每个台面区域20基本上被覆盖有硬掩模层31的剩余部分，该剩余部分包括在截面中且在大致平行于主表面103的方向上具有比相应台面区域20更小的最小延伸的第二部分31b；以及暴露在由第二部分31a到主表面103上的投影限定的区域中的台面区域20。
虽然已经公开了本发明的各种示例性实施例，对于本领域技术人员来说将是显而易见的是，可以做出将实现本发明的一些优点的各种改变和修改，而不脱离本发明的精神和范围。执行相同功能的其它部件可以被适当地替换，这对于本领域合理技术人员来说将是明显的。应当提到的是，参照特定图说明的特征可以与其它图的特征组合，即使在其中没有明确提到这一点的那些情况下。对发明构思的这些修改旨在由所附权利要求涵盖。
为了便于描述，诸如“在…之下”、“在…下方”、“低于”、“在…之上”、“上面的”等之类的空间相关术语被用于说明一个元件相对于第二元件的定位。这些术语旨在包括除了图中描绘的那些之外的器件的不同定向。进一步地，诸如“第一”、“第二”等之类的术语还被用于描述各种元件、区域、区段等，并且同时并不旨在是限制性的。贯穿描述，同样的术语指的是同样的元件。
如本文中使用的，术语“具有”、“含有”、“包含”、“包括”等是开放式术语，其指示所陈述的元件或特征的存在，但是并不排除另外的元件或特征。冠词“一”、“一个”和“该”旨在包括复数以及单数，除非上下文另外明确说明。
在记住上述范围的变化和应用的情况下，应当理解的是，本发明并不受前述描述的限制，也不受附图的限制。代替地，本发明仅由以下权利要求及其法律等同物限定。

Claims (20)

1.一种用于生产竖直半导体器件的方法，所述方法包括：
—提供半导体晶片，所述半导体晶片包括第一导电类型的第一半导体层、与所述第一半导体层形成第一pn结的第二导电类型的第二半导体层、以及与所述第二半导体层形成第二pn结并且延伸到所述半导体晶片的主表面的所述第一导电类型的第三半导体层；
—在所述主表面上形成硬掩模，所述硬掩模包括通过第一开口彼此间隔开的硬掩模部分；
—使用所述硬掩模从所述主表面向所述第一半导体层中蚀刻深沟槽，使得在所述主表面处由所述硬掩模部分的相应部分覆盖的半导体台面被形成在所述深沟槽的毗邻沟槽之间；
—填充所述深沟槽和所述硬掩模的所述第一开口；以及
—蚀刻所述硬掩模以在所述半导体台面的所述主表面处的所述硬掩模中形成第二开口。
2.根据权利要求1所述的方法，进一步包括在蚀刻所述硬掩模之后从所述主表面向所述半导体台面中蚀刻浅沟槽，使得所述浅沟槽不会延伸到所述第一pn结。
3.根据权利要求1所述的方法，其中形成所述硬掩模，使得每个所述硬掩模部分包括第二部分和第一部分，所述第一部分被布置在所述主表面处并且在所述第二部分与所述第一半导体层之间并且在基本上平行于所述主表面的方向上具有比所述第二部分更大的延伸。
4.根据权利要求3所述的方法，其中所述第一部分包括与所述第二部分不同的材料。
5.根据权利要求1所述的方法，其中形成所述硬掩模，使得所述第一开口中的至少两个开口在基本上正交于所述主表面的竖直截面中具有所述主表面处的、比在所述主表面处的其它第一开口的第一宽度更大的第三宽度。
6.根据权利要求5所述的方法，进一步包括沿着基本上竖直的线分割所述晶片，每条基本上竖直的线位于在所述竖直截面中具有所述第三宽度的所述第一开口的一个内。
7.根据权利要求1所述的方法，其中形成所述硬掩模包括以下各项中的至少一项：
—在所述主表面上形成硬掩模层；
—在所述主表面处形成第一掩模层；
—在所述第一掩模层上形成对于所述第一掩模层选择性可蚀刻的第二掩模层；以及
—在所述第二掩模层上形成对于所述第二掩模层选择性可蚀刻的第三掩模层；
—在所述硬掩模层、所述第二掩模层和所述第三掩模层中的至少一个上形成限定所述半导体衬底中的半导体台面的台面掩模，在基本上正交于所述主表面的截面中所述台面掩模包括限定所述第一开口的开口；以及
—蚀刻所述硬掩模层、所述第一掩模层、所述第二掩模层和所述第三掩模层中的至少一个以形成所述硬掩模。
8.根据权利要求7所述的方法，其中填充所述深沟槽和所述硬掩模的所述第一开口包括以下各项中的至少一项：
—至少在所述深沟槽的侧壁处形成电介质区域；以及
—在所述电介质区域上形成导电区域；
—沉积对所述第二掩模层选择性可蚀刻的电介质材料；以及
—CMP处理。
9.根据权利要求8所述的方法，其中所述硬掩模层被形成为ONO堆叠。
10.根据权利要求7所述的方法，其中蚀刻所述硬掩模包括以下各项中的至少一项：
—对于所述电介质材料和所述第一掩模层的所述材料中的至少一个选择性蚀刻所述第二掩模层；以及
—蚀刻所述第一掩模层以暴露所述半导体台面。
11.根据权利要求1所述的方法，其中在生产所述竖直半导体器件期间所述硬掩模不被完全移除。
12.根据权利要求1所述的方法，其中提供所述半导体晶片包括以下各项中的至少一项：
—在衬底上形成所述第一导电类型的一个或多个外延层，使得所述一个或多个外延层的上表面形成所述主表面，所述衬底具有比所述一个或多个外延层更高的掺杂浓度；
—从上方将p型掺杂剂和n型掺杂剂中的至少一个注入到所述一个或多个外延层中；以及
—热退火。
13.一种用于生产竖直半导体器件的方法，所述方法包括：
—提供晶片，所述晶片包括主表面、基本上平行于所述主表面的第一pn结以及基本上平行于所述主表面并且被布置在所述第一pn结与所述主表面之间的第二pn结；
—在所述主表面处形成第一材料的第一硬掩模层；
—在所述第一硬掩模层上形成第二材料的第二硬掩模层；
—在所述第二硬掩模层上形成包括开口的台面掩模，所述台面掩模限定所述半导体衬底中的半导体台面；
—使用所述台面掩模蚀刻所述第一硬掩模层和所述第二硬掩模层以形成硬掩模，使得在第一区域中暴露所述晶片并且形成硬掩模部分，每个硬掩模部分包括所述第二硬掩模层的剩余部分和所述第一硬掩模层的剩余部分，所述第一硬掩模层的所述剩余部分在基本上平行于所述主表面的方向上具有比所述第二硬掩模层的所述剩余部分更大的延伸；
—使用所述硬掩模从所述第一区域至少向所述第一pn结蚀刻深沟槽以形成所述半导体台面；以及
—从所述主表面的第二区域向所述半导体台面中蚀刻浅沟槽，所述第二区域基本上对应于所述第二硬掩模层的所述剩余部分到所述主表面上的投影。
14.根据权利要求13所述的方法，进一步包括在蚀刻浅沟槽之前填充所述深沟槽和所述硬掩模的所述第一开口。
15.根据权利要求13所述的方法，进一步包括在蚀刻浅沟槽之前蚀刻所述硬掩模。
16.根据权利要求13所述的方法，其中在基本上正交于所述主表面的方向上所述浅沟槽比所述深沟槽更浅地延伸到所述晶片中。
17.根据权利要求13所述的方法，进一步包括在所述浅沟槽中形成导电区域。
18.一种竖直半导体器件，包括：
—半导体本体，具有后侧，并且在***区域中且在基本上垂直于所述后侧的竖直方向上从所述后侧延伸到所述半导体本体的第一表面，所述半导体本体在有源区域中包括在所述竖直方向上从所述第一表面延伸到布置在所述第一表面上方的主表面的多个间隔开的半导体台面，在竖直截面中所述***区域延伸在所述有源区域与边缘之间，所述边缘延伸在所述后侧与所述第一表面之间，在所述竖直截面中每个所述半导体台面包括第一侧壁、第二侧壁、延伸在所述第一侧壁与所述第二侧壁之间的第一pn结以及与所述半导体台面欧姆接触并且从所述主表面延伸到所述半导体台面中的导电区域；
—与所述半导体本体绝缘的多个栅极电极，每个所述栅极电极被布置在成对毗邻的半导体台面之间并且在所述竖直方向上跨所述毗邻的半导体台面的所述第一pn结延伸；以及
—被布置在所述后侧上的后侧金属化结构。
19.根据权利要求18所述的竖直半导体器件，其中在从上方观察时所述导电区域相对于所述半导体台面基本上被置于中心。
20.根据权利要求18所述的竖直半导体器件，进一步包括与最外面的半导体台面绝缘且毗邻并且延伸到所述***区域中的栅极电极。
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