CN104576331A - 鳍式场效应晶体管的掺杂方法 - Google Patents

鳍式场效应晶体管的掺杂方法 Download PDF

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CN104576331A
CN104576331A CN201510041108.XA CN201510041108A CN104576331A CN 104576331 A CN104576331 A CN 104576331A CN 201510041108 A CN201510041108 A CN 201510041108A CN 104576331 A CN104576331 A CN 104576331A
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admixture
semiconductor fin
rich
layer
substrate
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CN104576331B (zh
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蔡俊雄
黄玉莲
余德伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例包括鳍式场效应晶体管(fin field-effect transistors,FinFET)的掺杂方法。在该方法中，形成一包含掺质的富掺质层(dopant-rich layer)在基板的半导体鳍板(semiconductor fin)的顶表面及侧壁上。形成盖层以覆盖富掺质层。对基板进行回火以将掺质由富掺质层趋入半导体鳍板中。发明的多种实施例可改善传统LDD工艺的缺点。例如，在不同实施例中形成富掺质层、形成盖层以及将杂质趋入LDD区以达所需厚度却不用顾虑阴影效应及PAI孪晶界缺陷的回火工艺。因此，可改善装置的电性。

Description

鳍式场效应晶体管的掺杂方法
本申请是申请号为201010263807.6、申请日为2010年8月25日、发明名称为“鳍式场效应晶体管的掺杂方法”的发明专利申请的分案申请。
技术领域
本发明涉及集成电路装置，尤其涉及一种鳍式场效应晶体管(finfield-effect transistor,FinFET)的掺杂方法。
背景技术
在快速进步的半导体制造工业中，互补型金属氧化物半导体(complementary metal oxide semiconductor,CMOS)FinFET装置可用于许多逻辑及其他应用，且整合成为各种不同的半导体装置。FinFET装置一般包括具有高深宽比的半导体鳍板，在鳍板中形成晶体管的沟道及源极/漏极区。在部分鳍板装置上方及沿着其侧边处形成栅极可增加沟道及源极/漏极部分的表面积，以制作更快速、更可靠且控制更佳的半导体晶体管装置。FinFETs更进一步的优点包括减少短沟道效应及增加电流量。
然而目前的FinFET科技已面临挑战。例如通常以离子注入法形成轻掺杂漏极(lightly doped drain,LDD)区，而离子注入法会造成鳍板非共形(non-conformal)的掺杂轮廓(如:在鳍板顶的掺杂较离基板近的鳍板底的掺杂重)。此非共形的掺杂轮廓可造成的问题包括开启相关非一致的装置(associated non-uniform device)。利用倾斜注入(tilt implant)的缺点为光致抗蚀剂高度所引发的阴影效应(shadowing effect)及预先非晶化离子注入(preamorphization implantation,PAI)引发的孪晶界效应(twin boundary effect)。
因此，有需要改善FinFET元件的制作方法。
发明内容
为克服上述现有技术的缺陷，本发明提供一种掺杂鳍式场效应晶体管的方法，包括：提供一基板，该基板包括一半导体鳍板形成于该基板的一表面上，其中该半导体鳍板具有一顶表面及侧壁；沉积一包括掺质的富掺质层于该半导体鳍板的该顶表面及侧壁上；沉积一盖层在该富掺质层上；以及该基板回火以将该掺质由该富掺质层趋入该半导体鳍板中。
一种掺杂鳍式场效应晶体管的方法，包括：形成一硬掩模覆盖一基板的一第一半导体鳍板而露出该基板的一第二半导体鳍板；沉积一包括掺质的富掺质层在该第二半导体鳍板的一顶表面及侧壁上；沉积一盖层以覆盖该富掺质层；以及进行一回火工艺以将该掺质由该富掺质层趋入该第二半导体鳍板中。其中更包括：形成另一硬掩模覆盖该第二半导体鳍板而露出该第一半导体鳍板；沉积包含另一掺质的另一富掺质层在该第一半导体鳍板的该顶表面及该侧壁上，其中该另一掺质及在该第二半导体鳍板的该掺质为相反类型；沉积另外一盖层以覆盖该另外富掺质层；以及进行另一回火工艺以将该另一的掺质趋入该第一半导体鳍板中。
本发明的多种实施例可改善传统LDD工艺的缺点。例如，在不同实施例中形成富掺质层、形成盖层以及将杂质趋入LDD区以达所需厚度却不用顾虑阴影效应及PAI孪晶界缺陷的回火工艺。因此，可改善装置的电性。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下：
附图说明
图1～图8显示根据一实施例在基板上制作FinFET结构时的不同阶段。
图9为显示用来执行一实施例所述方法的设备。
图10显示在富掺质层的沉积时施以DC及RF偏压的示意图。
图11为根据一实施例制作FinFET结构的方法流程图。
其中，附图标记说明如下：
500～根据本发明一实施例制作FinFET结构的方法
501,503,505,507,509,511,513,515～工艺步骤
105～第一鳍板107～第二鳍板
101～基板103～浅沟槽隔离区
111～第一鳍板的顶表面109～第一鳍板的侧壁
115～第二鳍板的顶表面113～第二鳍板的侧壁
100～第一装置区200～第二装置区
117～栅极介电层119～电极层
123,127～栅极121,125～栅极介电材料
129～硬掩模10～晶片
300～设备302～反应室
304,306～电源131～富掺质层
308～等离子体133～盖层
135,137～LDD区
具体实施方式
图1至图8为制作FinFET的不同阶段的透视及剖面图。图11描述根据本发明一实施例制作FinFET结构的方法500的流程图。
图1与图11所示，工艺步骤501提供包括第一鳍板105及第二鳍板107的基板。在部分实施例中，基板101可为硅基板、锗基板或其他半导体材料的基板。基板101可由p型或n型掺质掺杂。可于基板101中或上方形成隔离区如浅沟槽隔离区103(shallow trench isolation region,STI region)。第一半导体鳍板105及第二半导体鳍板107延伸至STI区103的顶表面上方。第一半导体鳍板105具有顶表面111及侧壁109。第二半导体鳍板107具有顶表面115及侧壁113。基板101包括在第一装置区100的部分及在第二装置区200的部分。半导体鳍板105及107分别在第一装置区100及第二装置区200中。在一实施例中，利用第一装置区100及第二装置区200以形成一个n型FinFET及一个p型FinFET。
如图2所示，在第一装置区100及第二装置区200中与半导体鳍板105及107上，皆沉积上栅极介电层117及栅极层119。在一实施例中，以高介电常数(high k)的介电材料形成栅极介电层117。高介电常数材料的介电常数值可高于4甚或高于7，且可包括：包含铝的介电材料如氧化铝、氧化铝铪、氮氧化铝铪或氧化锆铝；包含铪的材料如氧化铪、氧化硅铪、氧化铝铪、氧化硅锆铪或氮氧化硅铪；和/或其他材料如氧化铝镧或氧化锆。在栅极介电层117上形成栅极层119，且其可导电材料形成如掺杂的多晶硅、金属或金属氮化物。
如图3与图11所示，在工艺步骤503中，栅极层119及栅极介电层117而后进行图案化以形成栅极堆叠(gate stacks)。于第一装置区100中，栅极堆叠包括栅极123及栅极介电材料121。于第二装置区200中，栅极堆叠包括栅极127及栅极介电材料125。栅极堆叠位于各半导体鳍板105及107的部分顶表面111,115及侧壁109,113上。在部分实施例中，保留半导体鳍板105及107的暴露部分，以于后续形成口袋(pocket)及轻掺杂源极及漏极区。在部分实施例中，可移除半导体鳍板105及107的暴露部分以形成凹陷(recesses)，而在凹陷中以外延成长半导体应力源(stressors)。在一实施例中，第一装置区100的半导体应力源可包括碳化硅，而在第二装置区200的半导体应力源可包括锗化硅。
如图4与图11所示，在工艺步骤505中形成硬掩模(hard mask)129并进行图案化以覆盖第一装置区100，而没有覆盖第二装置区200。图4为由图3中沿切线A-A’的垂直面而得的剖面图，因此没有显示栅极堆叠。
如图11所示，工艺步骤507在各半导体鳍板105及107的顶表面111,115及侧壁109,113的暴露部分移除原生氧化层(native oxide layer)。在一实施例中，基板101浸泡于包括氢氟酸溶液的溶液中，该溶液以比例350：1稀释。在另一实施例中，湿溶液包括本领域技术人员所熟知的任何适当的溶液。在部分实施例中，工艺步骤507包括本领域技术人员所熟知的干蚀刻工艺。
如图5所示，将晶片10放置于如图9所示的设备300上，该设备300用以进行等离子体辅助沉积(plasma assisted deposition)工艺。设备300包括具晶片10放置其中的反应室302以及与反应室连接的电源304及306。晶片10包括在基板101上的半导体鳍板105及107。电源304可为具有可程控的脉冲调节(programmable pulse modulation)功能的无线电射频(radio frequency,RF)电源，而电源306可为脉冲直流(DC)或RF电源以在晶片10上提供偏压。电源304及306可彼此独立操作。各电源304及306可程控为独立电源开关而不会彼此影响。
如图5与图11所示工艺步骤509，借由如图9所示的机台300，在第二半导体鳍板107的顶表面115及侧壁113上沉积富掺质(dopant rich)层131。富掺质层131包括在第二半导体鳍板107中用以形成LDD区的掺质。根据FinFET所需的导电型态(conductivity type)，富掺质层131可为n型掺质(杂质)或p型掺质(杂质)。例如，假如所得FinFET为p型FinFET，则富掺质层131可包括硼和/或铟，而若所得FinFET为n型FinFET，则富掺质层131可包括磷和/或砷。在一实施例中，在富掺质层131中掺质的原子百分比可大于约90％，且实际上可为纯掺质层。
依据富掺质层131的成分，在反应室302(如图9)中的工艺气体可包括砷化氢、乙硼烷(B2H6)、磷化氢(PH3)、三氟化硼(BF3)，稀释气体如氙、氩、氦、氖、氢等。该工艺可在小于100mTorr的压力下进行。开启RF电源304(图9)以产生等离子体308。RF电源304的电力例如可介于约50watts与1000watts间，但也可适用更大或更小的电力。在一实施例中，在形成富掺质层131的整个过程中持续开启RF电源304。在另一实施例中，以脉冲的(为开及关交替的模式)RF电源304改善富掺质层131的共形性(阶梯覆盖性)。
在形成富掺质层131时，如图9DC电源306具有低于约2kV的低偏压，因此在形成掺质层时不会形成不要的非晶质层。在一实施例中，DC电源306的输出偏压介于约0kV与约2kV之间。因DC偏压很小甚或为零而减低离子掺杂工艺的方向性(directionality)，因此富掺质层131可沉积在第二半导体鳍板107上成为分离层而非直接注入鳍板107中。在形成富掺质层131时，DC电源306所提供的DC电流也可如图10所示为以约0.5至约10KHz的频率脉冲(开及关交替)。
如图6与图11所示，在工艺步骤511中，在第二半导体鳍板107上的富掺质层131上沉积盖层133。在部分实施例中，盖层133可包括氧化硅、氮化硅、碳化硅或前述的组合物。盖层133的厚度介于约30埃至约300埃。根据盖层133的薄膜密度及紧密度(compactness)，应控制盖层133的厚度在适当范围内。例如在部分实施例中，当其厚度小于约30埃时，在之后回火工艺中富掺质层131中的掺质将经由盖层133扩散出来；当其厚度大于约300埃时，盖层133可能会从富掺质层131脱落。
在一实施例中，以等离子体强化原子层沉积(plasma enhanced atomic layerdeposition)形成盖层133。工艺先行物可包括二胺硅烷(silanediamine)、N,N,N’,N’-四乙基(N,N,N’,N’-tetraethyl，市售为Air Liquide的SAM24)及氧。该沉积的操作功率为约20W至约500W。在温度低于约300℃形成盖层133，以避免在形成盖层的工艺中，富掺质层131中的掺质经由盖层133扩散出去。在部分实施例中，盖层133的沉积可利用其他可以形成氧化硅、氮化硅或碳化硅的共形层的沉积技术。
如图7与图11所示，工艺步骤512中，基板101进行回火以在第二半导体鳍板107中形成LDD区137。活化富掺质层131中的杂质而扩散进入第二半导体鳍板107中。在回火工艺中，盖层133防止富掺质层131的掺质经由盖层133扩散出去。进行回火的温度可介于约900℃与约1100℃间。该回火可为毫秒回火(millisecond annealing,MSA)或快速热回火(rapid thermalannealing,RTA)。
接下来，在图11的工艺步骤513中，移除在第一装置区100的硬掩模129。如图11所示在工艺步骤515中移除盖层133及富掺质层131。在一实施例中，工艺步骤515包括将基板101浸泡在包含氢氟酸的湿溶液中。在部分实施例中，工艺步骤515包括借干蚀刻工艺蚀刻盖层133及富掺质层131。
图8显示包括第一鳍板105及第二鳍板107的基板分别具有LDD区135及LDD区137。在第一半导体鳍板105形成LDD区135时，可借由基本上与上述相同工艺形成，但在形成LDD区时以硬质掩模覆盖第二半导体鳍板107，且第一半导体鳍板105可与第二半导体鳍板107的导电型态相反。在LDD区的掺质浓度例如可介于约1E20/cm3与约1E21/cm3。
在形成LDD区135及137之后可形成栅极间隔物(未显示)。在后续工艺步骤中，可依据所需导电类型，在鳍板105及107中注入n型杂质(如磷)及p型杂质(如硼)以形成深源极/漏极区(未显示)。在深源极/漏极区的掺质浓度例如可介于约1E20/cm3与约1E21/cm3间。因此在第一装置区100及第二装置区200中形成FinFET。
图1至图11是为了本揭露的发明概念更易理解而经过简化。例如：虽然附图为FinFET，集成电路(ICs)可包括多种不同装置包括电阻器、电容、电感、导线等。可利用本发明的多种实施例改善传统LDD工艺的缺点。例如，在不同实施例中形成富掺质层131、形成盖层133以及将杂质趋入LDD区以达所需厚度却不用顾虑阴影效应及PAI孪晶界缺陷的回火工艺。因此，可改善装置的电性。
虽然本发明已以数个优选实施例揭露如上，然而其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作任意的更动更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。7 -->

Claims (10)

1.一种掺杂鳍式场效应晶体管的方法，包括：
提供一基板，该基板包括一第一装置区、一第二装置区、及一半导体鳍板形成于该基板的一表面上，其中该半导体鳍板具有一顶表面及侧壁且形成在该第二装置区中；
形成硬掩模覆盖该第一装置区；
沉积一包括掺质的富掺质层于该半导体鳍板的该顶表面及侧壁上，其中在该富掺质层中掺质的原子百分比大于约90％；
沉积一盖层在该富掺质层上，其中该盖层的厚度介于约30埃至约300埃之间，并且在温度低于约300℃下沉积该盖层；以及
该基板回火以将该掺质由该富掺质层趋入该半导体鳍板中，进行该回火时该半导体鳍板没有被该硬掩模覆盖，而该第一装置区被该硬掩模覆盖且没有该负掺质层。
2.如权利要求1所述的方法，其中该富掺质层主要以掺质组成。
3.如权利要求1所述的方法，其中该掺质包括硼、铟、磷或砷。
4.如权利要求1所述的方法，其中在该回火在该半导体鳍板中形成一轻掺杂源极/漏极区。
5.如权利要求1所述的方法，其中该盖层包括氧化硅、氮化硅或碳化硅。
6.一种掺杂鳍式场效应晶体管的方法，包括：
形成一硬掩模覆盖一基板的一第一半导体鳍板而露出该基板的一第二半导体鳍板；
沉积一包括掺质富掺质层在该第二半导体鳍板的一顶表面及侧壁上，其中在该富掺质层中掺质的原子百分比大于约90％；
沉积一盖层以覆盖该富掺质层，其中该盖层的厚度介于约30埃至约300埃之间，并且在温度低于约300℃下沉积该盖层；以及
进行一回火工艺以将该掺质由该富掺质层趋入该第二半导体鳍板中，进行该回火时该半导体鳍板没有被该硬掩模覆盖，而该第一装置区被该硬掩模覆盖且没有该负掺质层。
7.如权利要求6所述的方法，更包括：
形成另外一硬掩模覆盖该第二半导体鳍板而露出该第一半导体鳍板；
沉积包含另一掺质的另一富掺质层在该第一半导体鳍板的该顶表面及该侧壁上，其中该另一掺质及在该第二半导体鳍板的该掺质为相反类型；
沉积另外一盖层以覆盖该另外富掺质层；以及
进行另一回火工艺以将该另一的掺质趋入该第一半导体鳍板中。
8.如权利要求6所述的方法，其中经由一机台形成该富掺质层，该机台包括一电源，该电源的输出偏压介于约0kV至约2kV之间。
9.一种掺杂鳍式场效应晶体管的方法，包括：
提供一基板，该基板包括一第一装置区、一第二装置区、及一半导体鳍板形成于该基板的一表面上，其中该半导体鳍板具有一顶表面及侧壁且形成在该第二装置区中；
形成硬掩模覆盖该第一装置区；
沉积一包括掺质的富掺质层于该半导体鳍板的该顶表面及侧壁上，其中在该富掺质层中掺质的原子百分比大于约90％；
沉积一盖层在该富掺质层上；以及
该基板回火以将该掺质由该富掺质层趋入该半导体鳍板中，进行该回火时该半导体鳍板没有被该硬掩模覆盖，而该第一装置区被该硬掩模覆盖且没有该负掺质层。
10.如权利要求9所述的方法，其中以等离子强化原子层沉积形成该盖层。
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CN107919347B (zh) * 2016-10-10 2020-07-10 中芯国际集成电路制造(上海)有限公司 鳍式电阻元件及半导体器件的形成方法
CN108122910A (zh) * 2016-11-28 2018-06-05 台湾积体电路制造股份有限公司 半导体元件
CN108122910B (zh) * 2016-11-28 2021-10-15 台湾积体电路制造股份有限公司 半导体元件及其制造方法
CN108962753A (zh) * 2017-05-19 2018-12-07 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109599400A (zh) * 2017-09-12 2019-04-09 联发科技股份有限公司 集成电路、半导体结构及其制造方法
CN109599400B (zh) * 2017-09-12 2021-06-08 联发科技股份有限公司 集成电路、半导体结构及其制造方法

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