CN104571735A - Panel time delay detection circuit - Google Patents
Panel time delay detection circuit Download PDFInfo
- Publication number
- CN104571735A CN104571735A CN201310504593.0A CN201310504593A CN104571735A CN 104571735 A CN104571735 A CN 104571735A CN 201310504593 A CN201310504593 A CN 201310504593A CN 104571735 A CN104571735 A CN 104571735A
- Authority
- CN
- China
- Prior art keywords
- signal
- current
- electric capacity
- lens unit
- time delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 78
- 238000012937 correction Methods 0.000 claims abstract description 65
- 238000012360 testing method Methods 0.000 claims description 93
- 239000013078 crystal Substances 0.000 description 12
- 230000003044 adaptive effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000005574 cross-species transmission Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002045 lasting effect Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
- G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
- Position Input By Displaying (AREA)
Abstract
The invention provides a panel time delay detection circuit, which is applied to baseline correction of a touch panel and comprises a detection amplifier, a comparator and a correction unit. The detection amplifier receives a capacitance baseline detection signal from an electrode of the touch panel, and converts the capacitance baseline detection signal into a detection result signal. The comparator compares the detection result signal with the reference signal, and generates a comparison signal according to the comparison result signal. The correction unit generates a control signal according to the comparison signal and transmits the control signal to the detection amplifier for controlling the detection amplifier to correct the detection result signal. When the detection result signal is larger than the reference signal, the detection amplifier subtracts the correction signal from the capacitance baseline detection signal according to the control signal, so that the detection result signal generated by the detection amplifier is lower than a critical value.
Description
Technical field
The present invention relates to a kind of contact panel, and particularly a kind of panel time delay testing circuit being applied to contact panel baseline correction.
Background technology
Please refer to Fig. 1, Fig. 1 is the schematic diagram of traditional capacitance touching control panel.Contact panel 1 comprises touch interface 11, driving circuit 12 and testing circuit 13.Touch interface 11 has multiple electrode interlaced with each other usually, and driving circuit 12 provides drive singal TX to the electrode of one of them axis of touch interface 11.Testing circuit 13 is in order to detect the capacitance (or capacitance variation) of the electrode of another axis of touch interface 11.Such as: as shown in Figure 1, testing circuit 13 detects the electric capacity baseline detection signal RX of the electrode of another axis of touch interface 11.Because the size of touch interface 11, drive singal TX suffered by the electrode of diverse location is not only not identical with the signaling path producing electric capacity baseline detection signal RX, and path is not identical yet.The different length that basis signal transmits, although use identical drive singal TX, Resistance-Capacitance delay (RCdelay) (or being called time delay) that different path causes can be different, make produced electric capacity baseline detection signal RX have notable difference.
The electric capacity baseline detection signal of traditional capacitance touching control panel and the oscillogram of correction signal referring to Fig. 1 and Fig. 2, Fig. 2.As shown in Figure 1, the length of path P 1 is obviously also short than the length of path P 2, therefore, on a timeline, testing circuit 13 measure the detection signal corresponding to path P 1 can early than corresponding to the detection signal of path P 2.In addition, having may very briefer (rush) and have larger peak value compared with the detection signal of short path.As shown in Figure 2, the peak value of the signal of path P 1 is greater than the peak value of the signal of path P 2, and the signal of path P 2 is milder comparatively speaking.In addition, may be easier to compared with the signal excursion of the detection signal corresponding to short path the dynamic range (dynamic range) exceeding circuit presets.As shown in Figure 2, in the dynamic range that the signal excursion of below critical value Th is default, a part for the signal of path P 1 is greater than critical value Th, this part is spill over (overflow or loss signal), traditional testing circuit 13 can cut out spill over, makes detection signal cause distortion.
In order to reach the object of baseline correction, traditional practice is to provide a correction signal, the detection signal in each different path is corrected, the waveform of correction signal as shown in Figure 2, the waveform of correction signal is the signal providing a suppression (or button supports) in the position of the time shaft of detection signal, and the correction signal of such as Fig. 2 changes into second electrical level Vb by the first level Va.No matter be that path P 1 or path P 2 all can deduct an identical correction signal, avoid producing the situation that detection signal exceeds dynamic range.But the detection signal position on a timeline in different path is not identical, make correction signal may the detection signal be positioned on different time axle that produces of corresponding different path.Therefore, the difference that the path of size to detection signal due to contact panel is caused, traditional correcting mode is not easy to correct the detection signal in paths all on contact panel.
Summary of the invention
The embodiment of the present invention provides a kind of panel time delay testing circuit being applied to contact panel baseline correction, to carry out real-time baseline correction to contact panel.
The embodiment of the present invention provides a kind of panel time delay testing circuit being applied to contact panel baseline correction, comprises detecting amplifier, comparer and correcting unit.Detecting amplifier receives the electric capacity baseline detection signal from the electrode of contact panel, and electric capacity baseline detection signal is converted to testing result signal by detecting amplifier.Comparer couples detecting amplifier, and testing result signal and reference signal is compared, and produces comparison signal accordingly.Correcting unit couples detecting amplifier and comparer, and correcting unit produces control signal according to comparison signal, and control signal is sent to detecting amplifier, in order to control detecting amplifier correct detection consequential signal.When testing result signal is greater than reference signal, electric capacity baseline detection signal is deducted correction signal according to control signal by detecting amplifier, and the testing result signal produced to make detecting amplifier is lower than a critical value.
In sum, the embodiment of the present invention provides a kind of panel time delay testing circuit being applied to contact panel baseline correction, and it can carry out real-time baseline correction to contact panel.Described panel time delay testing circuit can provide the Real-Time Monitoring of Resistance-Capacitance delay, and is automatic, adaptive correction.Described panel time delay testing circuit is independently testing mechanism, is bonded to easily in the framework of the testing circuit of existing contact panel.
Further understand feature of the present invention and technology contents for enable, refer to following detailed description for the present invention and accompanying drawing, but these illustrate and institute's accompanying drawings is only used to the present invention is described, but not any restriction is done to right of the present invention.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of traditional capacitance touching control panel.
Fig. 2 is the electric capacity baseline detection signal of traditional capacitance touching control panel and the oscillogram of correction signal.
Fig. 3 is the circuit diagram being applied to the panel time delay testing circuit of contact panel baseline correction that the embodiment of the present invention provides.
Fig. 4 is the circuit diagram being applied to the panel time delay testing circuit of contact panel baseline correction that another embodiment of the present invention provides.
[symbol description]
1: contact panel
11: touch interface
12: driving circuit
13: testing circuit
P1, P2: path
TX, Vdrv: drive singal
RX, SS: electric capacity baseline detection signal
Th: critical value
E: electrode
C, Cm, Cint: electric capacity
3,4: panel time delay testing circuit
31,41: detecting amplifier
32,42: comparer
33,43: correcting unit
34: analog/digital converter
Vout: testing result signal
Vref: reference signal
Kflag: comparison signal
CK: control signal
Dout: digital signal
415: current lens unit
411: the first current sources
412: the second current sources
413: the first switches
414: second switch
I1: the first electric current
I2: the second electric current
A: first end
B: the second end
VDD: supply voltage
N1, N2, N3:N transistor npn npn
P1, P2, P3:P transistor npn npn
Biasa, biasb: bias voltage
GND: ground connection
Embodiment
(being applied to the embodiment of the panel time delay testing circuit of contact panel baseline correction)
Please refer to Fig. 3, Fig. 3 is the circuit diagram being applied to the panel time delay testing circuit of contact panel baseline correction that the embodiment of the present invention provides.The panel time delay testing circuit 3 being applied to contact panel baseline correction comprises detecting amplifier 31, comparer 32, correcting unit 33 and analog/digital converter 34.
Detecting amplifier 31 connects the electrode of contact panel, is capacitance type touch-control panel at this contact panel.Detecting amplifier 31 detects the electric capacity of the electrode of contact panel, and described electric capacity can be from perhaps mutual tolerance.As shown in Figure 3, one end of electric capacity C receives drive singal Vdrv, and the other end connecting electrode E of electric capacity C, electrode E represents with the node of circuit, and it represents one of them electrode of contact panel.The present invention does not limit the shape of described electrode, and panel time delay testing circuit 3 is for being connected to electrode E with Detection capacitance value.
Comparer 32 couples detecting amplifier 31, and correcting unit 33 couples detecting amplifier 31 and comparer 32.Analog/digital converter 34 couples detecting amplifier 31.The testing result signal Vout that detecting amplifier 31 produces by analog/digital converter 34 is converted to digital signal Dout.In the present embodiment, the algorithm of the touch control detection that analog/digital converter 34 uses along with contact panel and designing, those of ordinary skill in the art can change analog/digital converter 34 according to actual needs, and therefore the present invention does not limit.
Detecting amplifier 31 receives the electric capacity baseline detection signal SS of the electrode E from contact panel, and electric capacity baseline detection signal SS is converted to testing result signal Vout by detecting amplifier 31.Testing result signal Vout and reference signal Vref compares by comparer 32, produces comparison signal Kflag accordingly.Correcting unit 33 produces control signal CK according to comparison signal Kflag, and control signal CK is sent to detecting amplifier 31, in order to control detecting amplifier 31 correct detection consequential signal Vout.
Detecting amplifier 31 can be current amplifier.In the present embodiment, the electric capacity baseline detection signal SS that detecting amplifier 31 receives is current forms.But the present invention does not limit the type of detecting amplifier 31, detecting amplifier 31 also can be voltage amplifier.
Comparer 32 is in order to compare testing result signal Vout and reference signal Vref, and described reference signal Vref can be a critical value Th of the testing result signal Vout corresponding to required design.Such as: when testing result signal Vout is voltage form, reference signal Vref is also voltage form, and the current potential of reference signal Vref can equal the critical value Th described in Fig. 2.But the present invention does not limit the implementation of comparer 32, do not limit reference signal Vref content yet.
Correcting unit 33 is controlled by comparison signal Kflag, such as: correcting unit 33 can be trigger circuit, is controlled by the triggering (such as comparison signal Kflag changes into a noble potential by an electronegative potential) of comparison signal Kflag, and produces control signal CK.An electric capacity baseline detection signal SS and correction signal (Fig. 3 is not shown) subtracts each other in order to make detecting amplifier 31 by control signal CK, makes the signal received by the input end of detecting amplifier 31 (end points of connecting electrode E) change into remaining electric capacity baseline detection signal SS by electric capacity baseline detection signal SS originally and deducts a correction signal.Because testing result signal Vout changes (such as: testing result signal Vout is directly proportional to electric capacity baseline detection signal SS) along with electric capacity baseline detection signal SS, therefore, when electric capacity baseline detection signal SS deducts a correction signal, testing result signal Vout also can reduce, and reaches the object making testing result signal Vout lower than critical value Th by this.
In other words, when testing result signal Vout is greater than reference signal Vref, electric capacity baseline detection signal SS is deducted correction signal according to the control signal CK of correcting unit 33 by detecting amplifier 31, and the testing result signal Vout produced to make detecting amplifier 31 is lower than a set critical value.Electric capacity baseline detection signal SS and subtracting each other of correction signal can be real-time, the adaptive change along with testing result signal Vout.
In addition, in one embodiment, when testing result signal Vout is greater than reference signal Vref, detecting amplifier 31 can make electric capacity baseline detection signal SS and correction signal be subtracted from one another in a Preset Time according to control signal CK.Described Preset Time can adjust according to the signal intensity amplitude of electric capacity baseline detection signal SS (waveform mild or precipitous), and by this, electric capacity baseline detection signal SS and subtracting each other of correction signal also can be the lasting Preset Times set by maintenance one section.
In order to reach the object of signal correction, when testing result signal Vout is greater than reference signal Vref, correction signal can be the first level Va, as shown in Figure 2.When testing result signal Vout is not more than reference signal Vref, correction signal is second electrical level Vb.With traditional way unlike the panel time delay testing circuit 3 of, the embodiment of the present invention be put into effect for the electric capacity baseline detection signal SS of each detected electrode time, adaptive baseline correction.The correction signal that the present embodiment provides, when electric capacity baseline detection signal SS is greater than critical value Th, produces correction signal immediately, does not have the problem that correction signal and electric capacity baseline detection signal SS are positioned at the diverse location on time shaft.It is worth mentioning that, described correction signal is different according to the design of detecting amplifier 31, refers to the explanation of subsequent embodiment.
(being applied to another embodiment of the panel time delay testing circuit of contact panel baseline correction)
Please refer to Fig. 4, Fig. 4 is the circuit diagram being applied to the panel time delay testing circuit of contact panel baseline correction that another embodiment of the present invention provides.Panel time delay testing circuit 4 comprises detecting amplifier 41, comparer 42 and correcting unit 43, and correcting unit 43 also can be called baseline correction controller (Baseline Calibration Controller) in the present embodiment.Fig. 4 provides and a kind of detecting amplifier 41 is applied to panel time delay testing circuit 4.
As shown in Figure 4, detecting amplifier 41 connects the electrode E of contact panel, and electrode E represents with the node of circuit in the present embodiment.One end of electric capacity Cm receives drive singal Vdrv, other end connecting electrode E, and this electric capacity Cm represents mutual tolerance, and the mutual tolerance received between the electrode of drive singal Vdrv and institute pole E is electric capacity Cm.Panel time delay testing circuit 4 is for being connected to electrode E to detect the capacitance of its mutual tolerance.
Comparer 42 couples detecting amplifier 41, and correcting unit 43 couples detecting amplifier 41 and comparer 42.When testing result signal Vout is greater than reference signal Vref, electric capacity baseline detection signal SS is deducted correction signal according to the control signal CK of correcting unit 43 by detecting amplifier 41, and the testing result signal Vout produced to make detecting amplifier 41 is lower than a set critical value Th.Described correction signal can be electric current I 1 in Fig. 4 or electric current I 2.
The thin portion circuit of detecting amplifier 41 please refer to explanation below.In the present embodiment, detecting amplifier 41 comprises at least one current source (411 or 412), at least one switch element 413 or 414, current lens unit 415 and electric capacity Cint.The present invention is the number of current limiting power and switch element and annexation not.Current source (411 or 412) is in order to generation current (I1 or I2), and electric current (I1 or I2) represents described correction signal.Switch element couples current source (411 or 412) and correcting unit 43, receives the control signal CK of correcting unit 43, and controls according to control signal CK the electrode E whether current source (411 or 412) couples contact panel.
Current lens unit 415 has first end A and the second end B, first end A is in order to be coupled to electrode E, current lens unit 415 does phase reversal to the electric capacity baseline detection signal SS received by electrode E, and produce testing result signal Vout in this second end B of current lens unit 415, wherein testing result signal Vout is contrary with the phase place of electric capacity baseline detection signal SS.The first end of electric capacity connects the second end B of current lens unit 415, and the second end of electric capacity connects ground connection GND.When testing result signal Vout is greater than reference signal Vref, electric capacity baseline detection signal SS is deducted the electric current (I1 or I2) of current source (411 or 412) by switch element (413 or 414) according to control signal CK.Fig. 4 of the present embodiment is only a kind of implementation of detecting amplifier 41, the implementation of the present invention also not current limiting power (411 or 412), switch element (413 or 414) and current lens unit 415.
In more detail, detecting amplifier 41 comprises the first current source 411, second current source 412, first switch element 413, second switch unit 414, current lens unit 415 and electric capacity Cint as shown in Figure 4.First current source 411 couples supply voltage VDD, produces the first electric current I 1.Second current source 412 couples ground connection GND, produces the second electric current I 2, and described first electric current I 1 and the second electric current I 2 represent correction signal.First switch element 413 couples the first current source 411 and correcting unit 43, and is controlled by the control signal CK of correcting unit 43, and controls according to control signal CK the electrode E whether the first current source 411 couples contact panel.In other words, whether the first electric current I 1 that the first switch element 413 controls the first current source 411 flows into electrode E, and therefore the first electric current I 1 can as correction signal.
Second switch unit 414 couples the second current source 412 and correcting unit 43, and is controlled by the control signal CK of correcting unit 43, and controls according to control signal CK the electrode E whether the second current source 412 couples contact panel.In other words, whether the second electric current I 2 that second switch unit 414 controls the second current source 412 flows into electrode E, and therefore the second electric current I 2 can as correction signal.
Further, current lens unit 415 comprises P-type crystal pipe P1, P2, P3 and N-type transistor N1, N2, N3.Current lens unit 415 is made up of two current mirrors, and the two ends of two current mirrors are connected to each other, and the other two ends of two current mirrors connect supply voltage VDD and ground connection GND respectively.One of them current mirror above-mentioned is made up of P-type crystal pipe P1, P2 and N-type transistor N1 and is applied in bias voltage biasa, and another current mirror above-mentioned to be then made up of with N-type transistor N2, N3 P-type crystal pipe P3 and to be applied in bias voltage biasb.
Then, the detailed construction of current lens unit 415 is described further.The source electrode of P-type crystal pipe P1, P2 connects supply voltage VDD, and the grid of P-type crystal pipe P1, P2 is connected to each other.The drain electrode of N-type transistor N1 connects grid and the drain electrode of P-type crystal pipe P1, and the source electrode of N-type transistor N1 and the drain electrode of P-type crystal pipe P2 are connected first end A and the second end B respectively, wherein first end A is in order to receive the input current representing electric capacity baseline detection signal SS, and the second end B is in order to export follow-up signal sampling circuit (such as: the analog/digital converter 34 of Fig. 3) to by testing result signal Vout.
The source electrode of N-type transistor N2, N3 connects ground connection GND, and the grid of N-type transistor N2, N3 is connected to each other.The drain electrode of P-type crystal pipe P3 connects grid and the drain electrode of N-type transistor N2, and the source electrode of P-type crystal pipe P3 and the drain electrode of N-type transistor N3 are connected first end A and the second end B respectively.The first end of the Cint of electric capacity connects the second end B of current lens unit 415, and second end of electric capacity Cint connects ground connection GND.
Briefly, the circuit structure of current lens unit 415 can be described below.Current lens unit 415 has the first current mirror (be made up of P-type crystal pipe P1, P2), the first bias transistor (i.e. N-type transistor N1), the second bias transistor (i.e. P-type crystal pipe P3) and the second current mirror (be made up of N-type transistor N2, N3).First current mirror and the second current mirror are connected to high voltage VDD and ground connection GND respectively.The input end of the first current mirror and the input end of the second current mirror are connected to the first end A of current lens unit 415 respectively by the first bias transistor (N-type transistor N1) and the second bias transistor (P-type crystal pipe P3).The output terminal of the first current mirror and the output terminal of the second current mirror are connected to the second end B of current lens unit 415.
Based on the circuit of Fig. 4, when testing result signal Vout is greater than reference signal Vref, electric capacity baseline detection signal SS is deducted the first electric current I 1 of the first current source 411 and the second electric current I 2 of the second current source 412 by the first switch element 413 and second switch unit 414 according to control signal CK.Electric capacity baseline detection signal SS and subtracting each other of correction signal (first electric current I 1 and the second electric current I 2) can be real-time, the adaptive change along with testing result signal Vout.
In addition, in one embodiment, when testing result signal Vout is greater than reference signal Vref, detecting amplifier 31 can make electric capacity baseline detection signal SS and correction signal be subtracted from one another in a Preset Time according to control signal CK.As shown in Figure 4, described control signal CK can make the first switch element 413 and second switch unit 413 conducting Preset Time, to make in Preset Time, electric capacity baseline detection signal SS and correction signal (comprising the first electric current I 1 and the second electric current I 2) are subtracted from one another.By this, electric capacity baseline detection signal SS and subtracting each other of correction signal (first electric current I 1 and the second electric current I 2) also can be the lasting Preset Times set by maintenance one section.In addition, the present invention does not limit the size of the first electric current I 1 and the second electric current I 2 yet.
(the possible effect of embodiment)
In sum, a kind of panel time delay testing circuit being applied to contact panel baseline correction that the embodiment of the present invention provides, it can carry out real-time baseline correction to contact panel.Described panel time delay testing circuit can provide the Real-Time Monitoring of Resistance-Capacitance delay, and is automatic, adaptive correction.Described panel time delay testing circuit is independently testing mechanism, is bonded to easily in the framework of the testing circuit of existing contact panel.In addition, the panel time delay testing circuit that provides of the embodiment of the present invention reaches described automatic, adaptive correction by the current operating mode of current amplifier.
The foregoing is only embodiments of the invention, it is also not used to limit to the scope of the claims of the present invention.
Claims (10)
1. a panel time delay testing circuit, is applied to the baseline correction of contact panel, it is characterized in that, described panel time delay testing circuit comprises:
One detecting amplifier, receive an electric capacity baseline detection signal of the electrode from described contact panel, described electric capacity baseline detection signal is converted to a testing result signal by described detecting amplifier;
One comparer, couples described detecting amplifier, and described testing result signal and a reference signal compare by described comparer, produce a comparison signal accordingly; And
One correcting unit, couple described detecting amplifier and described comparer, described correcting unit produces a control signal according to described comparison signal, and described control signal is sent to described detecting amplifier, corrects described testing result signal in order to control described detecting amplifier;
Wherein, when described testing result signal is greater than described reference signal, described electric capacity baseline detection signal is deducted a correction signal according to described control signal by described detecting amplifier, and the described testing result signal produced to make described detecting amplifier is lower than a critical value.
2. panel time delay testing circuit according to claim 1, it is characterized in that, described reference signal represents described critical value, and the described testing result signal that described panel time delay testing circuit makes described detecting amplifier produce is lower than described reference signal.
3. panel time delay testing circuit according to claim 1, is characterized in that, described panel time delay testing circuit also comprises:
One analog/digital converter, couples described detecting amplifier, and described testing result signal is converted to a digital signal.
4. panel time delay testing circuit according to claim 1, it is characterized in that, described detecting amplifier comprises:
At least one current source, produces an electric current, and described electric current represents described correction signal;
At least one switch element, couples described current source and described correcting unit, receives the described control signal of described correcting unit, and controls according to described control signal the described electrode whether described current source couples described contact panel;
One current lens unit, described current lens unit has a first end and one second end, the first end of described current lens unit is in order to be coupled to described electrode, described current lens unit does phase reversal to the described electric capacity baseline detection signal received by described electrode, and producing described testing result signal in the second end of described current lens unit, wherein said testing result signal is contrary with the phase place of described electric capacity baseline detection signal; And
One electric capacity, the first end of described electric capacity connects the second end of described current lens unit, and the second end of described electric capacity connects a ground connection;
Wherein, when described testing result signal is greater than described reference signal, described electric capacity baseline detection signal is deducted the described electric current of described current source by described switch element according to described control signal.
5. panel time delay testing circuit according to claim 1, it is characterized in that, described detecting amplifier comprises:
One first current source, described first current source couples a supply voltage, and produces one first electric current;
One second current source, described second current source couples a ground connection, and produces one second electric current, and described first electric current and described second electric current represent described correction signal;
One first switch element, couple described first current source and described correcting unit, described first switch element is controlled by the described control signal of described correcting unit, and controls according to described control signal the described electrode whether described first current source couples described contact panel;
One second switch unit, couple described second current source and described correcting unit, described second switch unit is controlled by the described control signal of described correcting unit, and controls according to described control signal the described electrode whether described second current source couples described contact panel;
One current lens unit, described current lens unit has a first end and one second end, the first end of described current lens unit is in order to be coupled to described electrode, described current lens unit does phase reversal to the described electric capacity baseline detection signal received by described electrode, and producing described testing result signal in the second end of described current lens unit, wherein said testing result signal is contrary with the phase place of described electric capacity baseline detection signal; And
One electric capacity, the first end of described electric capacity connects the second end of described current lens unit, and the second end of described electric capacity connects described ground connection;
Wherein, when described testing result signal is greater than described reference signal, described electric capacity baseline detection signal is deducted described first electric current of described first current source and described second electric current of described second current source according to described control signal by described first switch element and described second switch unit.
6. panel time delay testing circuit according to claim 4, it is characterized in that, described current lens unit has one first current mirror, one first bias transistor, one second bias transistor and one second current mirror, described first current mirror is connected to a supply voltage, and described second current mirror is connected to described ground connection, the input end of described first current mirror is connected to the first end of described current lens unit by described first bias transistor, and the input end of described second current mirror is connected to the first end of described current lens unit by described second bias transistor, the output terminal of wherein said first current mirror and the output terminal of described second current mirror are connected to the second end of described current lens unit.
7. panel time delay testing circuit according to claim 5, it is characterized in that, described current lens unit has one first current mirror, one first bias transistor, one second bias transistor and one second current mirror, described first current mirror is connected to described supply voltage, and described second current mirror is connected to described ground connection, the input end of described first current mirror is connected to the first end of described current lens unit by described first bias transistor, and the input end of described second current mirror is connected to the first end of described current lens unit by described second bias transistor, the output terminal of wherein said first current mirror and the output terminal of described second current mirror are connected to the second end of described current lens unit.
8. panel time delay testing circuit according to claim 1, is characterized in that, described detecting amplifier is current amplifier.
9. panel time delay testing circuit according to claim 1, it is characterized in that, when described testing result signal is greater than described reference signal, described correction signal is one first level, when described testing result signal is less than or equal to described reference signal, described correction signal is a second electrical level.
10. panel time delay testing circuit according to claim 4, it is characterized in that, when described testing result signal is greater than described reference signal, described detecting amplifier makes described electric capacity baseline detection signal and described correction signal be subtracted from one another in a Preset Time.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102136520 | 2013-10-09 | ||
| TW102136520A TWI502443B (en) | 2013-10-09 | 2013-10-09 | Rc delay detection circuit for baseline calibration of touch panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104571735A true CN104571735A (en) | 2015-04-29 |
Family
ID=53087971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310504593.0A Pending CN104571735A (en) | 2013-10-09 | 2013-10-23 | Panel time delay detection circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104571735A (en) |
| TW (1) | TWI502443B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107844222A (en) * | 2016-09-21 | 2018-03-27 | 奕力科技股份有限公司 | Touch sensing device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107422927A (en) * | 2016-05-23 | 2017-12-01 | 联合聚晶股份有限公司 | Touch control display device and its touch control detection circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1689294A (en) * | 2002-10-17 | 2005-10-26 | 皇家飞利浦电子股份有限公司 | Method and device for signal amplitude detection |
| CN101194172A (en) * | 2005-06-16 | 2008-06-04 | 艾勒博科技股份有限公司 | Touch sensor and signal generation method thereof |
| CN101227176A (en) * | 2007-01-19 | 2008-07-23 | 联发科技股份有限公司 | Gain control system and calibration method thereof |
| CN102591511A (en) * | 2011-01-17 | 2012-07-18 | 瑞鼎科技股份有限公司 | Control device of touch panel |
| CN102999205A (en) * | 2011-06-10 | 2013-03-27 | 美法思株式会社 | Touch panel system with delay compensation capability and method for compensating delay in touch panel system |
| US8502801B2 (en) * | 2008-08-28 | 2013-08-06 | Stmicroelectronics Asia Pacific Pte Ltd. | Capacitive touch sensor system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWM375284U (en) * | 2009-10-05 | 2010-03-01 | Hai Teh Electronic Co Ltd | Touch delay controller |
| KR101190276B1 (en) * | 2009-10-28 | 2012-10-12 | 주식회사 애트랩 | Input device and touch position detecting method thereof |
| US9158143B2 (en) * | 2011-09-12 | 2015-10-13 | Apple Inc. | Dual purpose touch sensor panel and optical retarder |
-
2013
- 2013-10-09 TW TW102136520A patent/TWI502443B/en not_active IP Right Cessation
- 2013-10-23 CN CN201310504593.0A patent/CN104571735A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1689294A (en) * | 2002-10-17 | 2005-10-26 | 皇家飞利浦电子股份有限公司 | Method and device for signal amplitude detection |
| CN101194172A (en) * | 2005-06-16 | 2008-06-04 | 艾勒博科技股份有限公司 | Touch sensor and signal generation method thereof |
| CN101227176A (en) * | 2007-01-19 | 2008-07-23 | 联发科技股份有限公司 | Gain control system and calibration method thereof |
| US8502801B2 (en) * | 2008-08-28 | 2013-08-06 | Stmicroelectronics Asia Pacific Pte Ltd. | Capacitive touch sensor system |
| CN102591511A (en) * | 2011-01-17 | 2012-07-18 | 瑞鼎科技股份有限公司 | Control device of touch panel |
| CN102999205A (en) * | 2011-06-10 | 2013-03-27 | 美法思株式会社 | Touch panel system with delay compensation capability and method for compensating delay in touch panel system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107844222A (en) * | 2016-09-21 | 2018-03-27 | 奕力科技股份有限公司 | Touch sensing device |
| CN107844222B (en) * | 2016-09-21 | 2021-01-26 | 奕力科技(开曼)股份有限公司 | Touch sensing device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201514790A (en) | 2015-04-16 |
| TWI502443B (en) | 2015-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9189004B2 (en) | Control circuit, control method used in PFC circuit and power source system thereof | |
| CN103869867B (en) | Chopped wave band-gap reference circuit | |
| TWI392877B (en) | Capacitor sensing circuit and capacitor difference sensing method | |
| JP5529214B2 (en) | Power supply device for test apparatus and test apparatus using the same | |
| JP2008206348A (en) | Semiconductor device | |
| JP2012147183A (en) | Photoelectric converter | |
| JP5390932B2 (en) | Power circuit | |
| TWI466000B (en) | Touch sensor circuit and touch display device | |
| KR20150069936A (en) | Offset correction apparatus for differential amplifier and method thereof | |
| CN111414091A (en) | Capacitive touch detection circuit | |
| CN104571735A (en) | Panel time delay detection circuit | |
| JP2016070835A (en) | Detector and detection system | |
| JP2018506887A (en) | Analog-to-digital converter protection circuit, method for controlling analog-to-digital converter protection circuit, and controller | |
| CN103616924B (en) | Sensor circuit | |
| JP5964001B2 (en) | Power monitoring device and receiving device | |
| JP6106045B2 (en) | Light receiving circuit | |
| US8232828B2 (en) | Analog circuit having improved response time | |
| TW201624890A (en) | Current sensing circuit and method thereof for power converting device | |
| US20150256191A1 (en) | Control method of d/a converter, d/a converter, control method of a/d converter, and a/d converter | |
| CN101783661A (en) | High-accuracy hysteresis comparator circuit and operating method thereof | |
| US9093961B2 (en) | Operational amplifier | |
| JP2004282959A (en) | Drive device of voltage-control type drive element | |
| JP6115784B2 (en) | Electronic equipment | |
| JP6223672B2 (en) | Voltage output device and offset cancel method for voltage output device | |
| CN105553427A (en) | Alternating-current coupling amplifying circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: Taiwan Hsinchu County China jhubei City, Taiwan two yuan Street No. 1 10 floor -1 Applicant after: ILI TECHNOLOGY Corp. Address before: Taiwan Hsinchu County China jhubei City, Taiwan two yuan Street No. 1 10 floor -1 Applicant before: Morning hair Polytron Technologies Inc. |
|
| CB02 | Change of applicant information | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20161222 Address after: Taiwan Hsinchu County China jhubei City, Taiwan two yuan Street No. 1 10 floor -1 Applicant after: Morning hair Polytron Technologies Inc. Address before: Taiwan, China Applicant before: ILI Technology Corp. |
|
| TA01 | Transfer of patent application right | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150429 |
|
| WD01 | Invention patent application deemed withdrawn after publication |