TW201514790A - RC delay detection circuit for baseline calibration of touch panel - Google Patents

RC delay detection circuit for baseline calibration of touch panel Download PDF

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Publication number
TW201514790A
TW201514790A TW102136520A TW102136520A TW201514790A TW 201514790 A TW201514790 A TW 201514790A TW 102136520 A TW102136520 A TW 102136520A TW 102136520 A TW102136520 A TW 102136520A TW 201514790 A TW201514790 A TW 201514790A
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signal
current
current mirror
detection
unit
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TW102136520A
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TWI502443B (en
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Chih-Jen Cheng
Cheng-Chung Hsu
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Ili Technology Corp
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Priority to CN201310504593.0A priority patent/CN104571735A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Position Input By Displaying (AREA)
  • Amplifiers (AREA)

Abstract

The present disclosure provides a RC delay detection circuit for baseline calibration of touch panel. The RC delay detection circuit comprises a detection amplifier, a comparator and a calibration unit. The detection amplifier receives a capacitor baseline detecting signal from an electrode of the touch panel and converts the capacitor baseline detecting signal to a detection result signal. The comparator compares the detection result signal with a reference signal to generate a comparing signal. The calibration unit generates a control signal according to the comparing signal. The calibration unit transmits the control signal to the detection amplifier for calibrating the detection result signal. When the detection result is larger than the reference signal, the detection amplifier deducts a calibration signal from the capacitor baseline detecting signal in order to make the detection result signal generated by the detection amplifier be less than a threshold.

Description

應用於觸控面板基線校正的面板時間延遲檢測電路 Panel time delay detection circuit applied to touch panel baseline correction

本發明有關於一種觸控面板，且特別是一種應用於觸控面板基線校正的面板時間延遲檢測電路。 The invention relates to a touch panel, and in particular to a panel time delay detecting circuit applied to a touch panel baseline correction.

請參照圖1，圖1是傳統的電容觸控面板的示意圖。觸控面板1包括觸控介面11、驅動電路12與檢測電路13。觸控介面11通常具有多個彼此交錯的電極，驅動電路12提供驅動信號TX至觸控介面11的其中一個軸向的電極。檢測電路13則用以檢測觸控介面11的另一個軸向的電極的電容值(或電容值變化)。例如：如圖1所示，檢測電路13檢測觸控介面11的另一個軸向的電極的電容基線檢測信號RX。因為觸控介面11的尺寸，不同位置的電極所受到驅動信號TX和產生電容基線檢測信號RX的信號傳遞路徑不僅不相同，路徑長度也不相同。依據信號傳遞的不同長度，雖然使用相同的驅動信號TX，不同路徑長度所造成的電阻-電容延遲(RC delay)(或稱為時間延遲)會不同，使得所產生的電容基線檢測信號RX會有明顯差異。 Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional capacitive touch panel. The touch panel 1 includes a touch interface 11 , a driving circuit 12 , and a detecting circuit 13 . The touch interface 11 generally has a plurality of electrodes staggered with each other, and the driving circuit 12 provides a driving signal TX to one of the axial electrodes of the touch interface 11 . The detecting circuit 13 is configured to detect a capacitance value (or a change in capacitance value) of another axial electrode of the touch interface 11 . For example, as shown in FIG. 1 , the detecting circuit 13 detects the capacitance baseline detection signal RX of the other axial electrode of the touch interface 11 . Because of the size of the touch interface 11, the signal transmission path of the driving signal TX and the capacitance baseline detection signal RX of the electrodes at different positions is not only different, but the path length is also different. Depending on the length of the signal transmission, although the same drive signal TX is used, the RC delay (or time delay) caused by the different path lengths will be different, so that the generated capacitance baseline detection signal RX will be Significant differences.

請同時參照圖1和圖2，圖2是傳統的電容觸控面板的電容基線檢測信號與校正信號的波形圖。如圖1所示，路徑P1的長度明顯比路徑P2的長度還短，因此，在時間軸上，檢測電路13所量到對應於路徑P1的檢測信號會早於對應於路徑P2的檢測信號。另外，具有較短路徑的檢測信號可能會較短促(rush)與具有較大的 峰值。如圖2所示，路徑P1的信號的峰值大於路徑P2的信號的峰值，且相對而言路徑P2的信號較平緩。另外，較短路徑所對應的檢測信號的信號變化範圍可能會較容易超出電路預設的動態範圍(dynamic range)。如圖2所示，在臨界值Th以下的信號變化範圍是預設的動態範圍，路徑P1的信號的一部份大於臨界值Th，此部份是溢出信號(overflow或loss signal)，傳統的檢測電路13會把溢出信號截掉，使得檢測信號造成失真。 Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a waveform diagram of a capacitance baseline detection signal and a correction signal of a conventional capacitive touch panel. As shown in FIG. 1, the length of the path P1 is significantly shorter than the length of the path P2. Therefore, on the time axis, the detection signal measured by the detecting circuit 13 corresponding to the path P1 is earlier than the detection signal corresponding to the path P2. In addition, detection signals with shorter paths may be shorter and have larger Peak. As shown in FIG. 2, the peak value of the signal of the path P1 is larger than the peak value of the signal of the path P2, and the signal of the path P2 is relatively flat. In addition, the signal variation range of the detection signal corresponding to the shorter path may be more likely to exceed the dynamic range of the circuit preset. As shown in FIG. 2, the signal variation range below the threshold Th is a preset dynamic range, and a portion of the signal of the path P1 is greater than the threshold Th, which is an overflow signal (overflow or loss signal), conventional The detection circuit 13 intercepts the overflow signal, causing the detection signal to cause distortion.

為了達到基線校正的目的，傳統的作法是提供一個校正信號，對每一個不同路徑的檢測信號做校正，如圖2所示的校正信號的波形，校正信號的波形是在檢測信號的時間軸的位置提供一個抑制(或扣抵)的信號，例如圖2的校正信號由第一準位Va改變為第二準位Vb。不論是路徑P1或路徑P2都可減去一個相同的校正信號，避免產生檢測信號超出動態範圍的情況。然而，不同路徑的檢測信號在時間軸上的位置並不相同，使得校正信號可能無法對應不同路徑所產生的位於不同時間軸上的檢測信號。因此，由於觸控面板的尺寸對檢測信號的路徑所造成的差異，傳統的校正方式不容易對觸控面板上所有路徑的檢測信號進行校正。 In order to achieve the purpose of baseline correction, the conventional method is to provide a correction signal for correcting the detection signal of each different path, as shown in the waveform of the correction signal shown in FIG. 2, the waveform of the correction signal is on the time axis of the detection signal. The position provides a signal that is suppressed (or offset), for example, the correction signal of FIG. 2 is changed from the first level Va to the second level Vb. Either the path P1 or the path P2 can be subtracted from the same correction signal to avoid the situation where the detection signal is out of the dynamic range. However, the positions of the detection signals of different paths on the time axis are not the same, so that the correction signals may not correspond to the detection signals on different time axes generated by different paths. Therefore, due to the difference between the size of the touch panel and the path of the detection signal, the conventional correction method does not easily correct the detection signals of all the paths on the touch panel.

本發明實施例提供一種應用於觸控面板基線校正的面板時間延遲檢測電路，以對觸控面板進行即時的基線校正。 Embodiments of the present invention provide a panel time delay detecting circuit applied to a touch panel baseline correction to perform immediate baseline correction on a touch panel.

本發明實施例提供一種應用於觸控面板基線校正的面板時間延遲檢測電路，包括檢測放大器、比較器以及校正單元。檢測放大器接收來自觸控面板之電極的電容基線檢測信號，檢測放大器將電容基線檢測信號轉換為檢測結果信號。比較器耦接檢測放大器，並將檢測結果信號與參考信號做比較，據此產生比較信號。校正單元耦接檢測放大器以及比較器，校正單元依據比較信號產生控制信號，並將控制信號傳送至檢測放大器，用以控制檢測放大器校正檢測結果信號。當檢測結果信號大於參考信號時，檢測 放大器依據控制信號而將電容基線檢測信號減去校正信號，以使檢測放大器產生的檢測結果信號低於一臨界值。 Embodiments of the present invention provide a panel time delay detecting circuit applied to a touch panel baseline correction, including a detecting amplifier, a comparator, and a correcting unit. The sense amplifier receives a capacitance baseline detection signal from an electrode of the touch panel, and the sense amplifier converts the capacitance baseline detection signal into a detection result signal. The comparator is coupled to the sense amplifier and compares the detection result signal with the reference signal to generate a comparison signal. The correction unit is coupled to the detection amplifier and the comparator. The correction unit generates a control signal according to the comparison signal, and transmits the control signal to the detection amplifier for controlling the detection amplifier to correct the detection result signal. When the detection result signal is greater than the reference signal, the detection The amplifier subtracts the correction signal from the capacitance baseline detection signal according to the control signal, so that the detection result signal generated by the detection amplifier is lower than a critical value.

綜上所述，本發明實施例提供一種應用於觸控面板基線校正的面板時間延遲檢測電路，其可對觸控面板進行即時的基線校正。所述面板時間延遲檢測電路可提供電阻-電容延遲的即時監測，且是自動的、適應性的校正。所述面板時間延遲檢測電路是獨立的檢測機制，方便地結合至現有的觸控面板的檢測電路的架構中。 In summary, the embodiments of the present invention provide a panel time delay detecting circuit applied to a touch panel baseline correction, which can perform immediate baseline correction on the touch panel. The panel time delay detection circuit provides instant monitoring of the resistance-capacitance delay and is an automatic, adaptive correction. The panel time delay detection circuit is an independent detection mechanism and is conveniently incorporated into the architecture of the detection circuit of the existing touch panel.

為使能更進一步瞭解本發明之特徵及技術內容，請參閱以下有關本發明之詳細說明與附圖，但是此等說明與所附圖式僅係用來說明本發明，而非對本發明的權利範圍作任何的限制。 The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

1‧‧‧觸控面板 1‧‧‧ touch panel

11‧‧‧觸控介面 11‧‧‧ Touch interface

12‧‧‧驅動電路 12‧‧‧Drive circuit

13‧‧‧檢測電路 13‧‧‧Detection circuit

P1、P2‧‧‧路徑 P1, P2‧‧‧ path

TX、Vdrv‧‧‧驅動信號 TX, Vdrv‧‧‧ drive signal

RX、SS‧‧‧電容基線檢測信號 RX, SS‧‧‧ Capacitance Baseline Detection Signal

Th‧‧‧臨界值 Th‧‧‧ threshold

E‧‧‧電極 E‧‧‧electrode

C、Cm、Cint‧‧‧電容 C, Cm, Cint‧‧‧ capacitors

3、4‧‧‧面板時間延遲檢測電路 3, 4‧‧‧ Panel time delay detection circuit

31、41‧‧‧檢測放大器 31, 41‧‧‧Detection amplifier

32、42‧‧‧比較器 32, 42‧‧‧ comparator

33、43‧‧‧校正單元 33, 43‧‧‧ calibration unit

34‧‧‧類比/數位轉換器 34‧‧‧ Analog/Digital Converter

Vout‧‧‧檢測結果信號 Vout‧‧‧ test result signal

Vref‧‧‧參考信號 Vref‧‧‧ reference signal

Kflag‧‧‧比較信號 Kflag‧‧‧ comparison signal

CK‧‧‧控制信號 CK‧‧‧ control signal

Dout‧‧‧數位信號 Dout‧‧‧ digital signal

415‧‧‧電流鏡單元 415‧‧‧current mirror unit

411‧‧‧第一電流源 411‧‧‧First current source

412‧‧‧第二電流源 412‧‧‧second current source

413‧‧‧第一開關 413‧‧‧First switch

414‧‧‧第二開關 414‧‧‧second switch

I1‧‧‧第一電流 I1‧‧‧First current

I2‧‧‧第二電流 I2‧‧‧second current

A‧‧‧第一端 A‧‧‧ first end

B‧‧‧第二端 B‧‧‧ second end

VDD‧‧‧供應電壓 VDD‧‧‧ supply voltage

N1、N2、N3‧‧‧N型電晶體 N1, N2, N3‧‧‧N type transistors

P1、P2、P3‧‧‧P型電晶體 P1, P2, P3‧‧‧P type transistor

biasa、biasb‧‧‧偏壓 Biasa, biasb‧‧‧ bias

GND‧‧‧接地 GND‧‧‧ Grounding

圖1是傳統的電容觸控面板的示意圖。 FIG. 1 is a schematic diagram of a conventional capacitive touch panel.

圖2是傳統的電容觸控面板的電容基線檢測信號與校正信號的波形圖。 2 is a waveform diagram of a capacitance baseline detection signal and a correction signal of a conventional capacitive touch panel.

圖3是本發明實施例提供的應用於觸控面板基線校正的面板時間延遲檢測電路的電路圖。 FIG. 3 is a circuit diagram of a panel time delay detecting circuit applied to a touch panel baseline correction according to an embodiment of the present invention.

圖4是本發明另一實施例提供的應用於觸控面板基線校正的面板時間延遲檢測電路的電路圖。 FIG. 4 is a circuit diagram of a panel time delay detecting circuit applied to a touch panel baseline correction according to another embodiment of the present invention.

〔應用於觸控面板基線校正的面板時間延遲檢測電路之實施例〕 [Embodiment of Panel Time Delay Detection Circuit Applied to Base Panel Correction of Touch Panel]

請參照圖3，圖3是本發明實施例提供的應用於觸控面板基線校正的面板時間延遲檢測電路的電路圖。應用於觸控面板基線校正的面板時間延遲檢測電路3包括檢測放大器31、比較器32、校正單元33與類比/數位轉換器34。 Please refer to FIG. 3. FIG. 3 is a circuit diagram of a panel time delay detecting circuit applied to a touch panel baseline correction according to an embodiment of the present invention. The panel time delay detecting circuit 3 applied to the touch panel baseline correction includes a sense amplifier 31, a comparator 32, a correcting unit 33, and an analog/digital converter 34.

檢測放大器31連接觸控面板之電極，在此之觸控面板是電容 式觸控面板。檢測放大器31檢測觸控面板之電極的電容，所述電容可以是自容或互容。如圖3所示，電容C的一端接收驅動信號Vdrv，電容C的另一端連接電極E，電極E以電路的節點表示，其代表觸控面板的其中一個電極。本發明並不限定所述電極的形狀，面板時間延遲檢測電路3是用於連接至電極E以檢測電容值。 The detecting amplifier 31 is connected to the electrode of the touch panel, where the touch panel is a capacitor Touch panel. The detection amplifier 31 detects the capacitance of the electrodes of the touch panel, and the capacitances may be self-contained or mutual capacitance. As shown in FIG. 3, one end of the capacitor C receives the driving signal Vdrv, and the other end of the capacitor C is connected to the electrode E. The electrode E is represented by a node of the circuit, which represents one of the electrodes of the touch panel. The present invention does not limit the shape of the electrode, and the panel time delay detecting circuit 3 is for connecting to the electrode E to detect the capacitance value.

比較器32耦接檢測放大器31，校正單元33耦接檢測放大器31以及比較器32。類比/數位轉換器34耦接檢測放大器31。類比/數位轉換器34將檢測放大器31產生的檢測結果信號Vout轉換為數位信號Dout。在本實施例中，類比/數位轉換器34是隨著觸控面板所使用的觸控檢測的演算法而設計，本領域的通常知識者可以根據實際需要而改變類比/數位轉換器34，本發明並不因此限定。 The comparator 32 is coupled to the sense amplifier 31, and the correction unit 33 is coupled to the sense amplifier 31 and the comparator 32. The analog/digital converter 34 is coupled to the sense amplifier 31. The analog/digital converter 34 converts the detection result signal Vout generated by the sense amplifier 31 into a digital signal Dout. In this embodiment, the analog/digital converter 34 is designed according to the algorithm of touch detection used by the touch panel, and a person skilled in the art can change the analog/digital converter 34 according to actual needs. The invention is not limited thereby.

檢測放大器31接收來自觸控面板之電極E的電容基線檢測信號SS，檢測放大器31將電容基線檢測信號SS轉換為檢測結果信號Vout。比較器32將檢測結果信號Vout與參考信號Vref做比較，據此產生比較信號Kflag。校正單元33依據比較信號Kflag產生控制信號CK，並將控制信號CK傳送至檢測放大器31，用以控制檢測放大器31校正檢測結果信號Vout。 The sense amplifier 31 receives the capacitance baseline detection signal SS from the electrode E of the touch panel, and the sense amplifier 31 converts the capacitance baseline detection signal SS into the detection result signal Vout. The comparator 32 compares the detection result signal Vout with the reference signal Vref, thereby generating a comparison signal Kflag. The correcting unit 33 generates the control signal CK according to the comparison signal Kflag, and transmits the control signal CK to the sense amplifier 31 for controlling the sense amplifier 31 to correct the detection result signal Vout.

檢測放大器31可以是電流放大器。在本實施例中，檢測放大器31所接收的電容基線檢測信號SS為電流形式。然而，本發明並不限定檢測放大器31的類型，檢測放大器31也可以是電壓放大器。 The sense amplifier 31 can be a current amplifier. In the present embodiment, the capacitance baseline detection signal SS received by the sense amplifier 31 is in the form of current. However, the present invention does not limit the type of the sense amplifier 31, and the sense amplifier 31 may also be a voltage amplifier.

比較器32用以比較檢測結果信號Vout與參考信號Vref，所述參考信號Vref可以是對應於所需求設計的檢測結果信號Vout的一個臨界值Th。例如：當檢測結果信號Vout是電壓形式時，參考信號Vref也是電壓形式，參考信號Vref的電位可以等於圖2所述的臨界值Th。然而，本發明並不限定比較器32的實現方式，也不限定參考信號Vref內容。 The comparator 32 is configured to compare the detection result signal Vout with a reference signal Vref, which may be a threshold value Th corresponding to the desired design result signal Vout. For example, when the detection result signal Vout is in the form of voltage, the reference signal Vref is also in the form of voltage, and the potential of the reference signal Vref may be equal to the threshold value Th described in FIG. However, the present invention does not limit the implementation of the comparator 32, nor does it limit the content of the reference signal Vref.

校正單元33受控於比較信號Kflag，例如：校正單元33是可以是一個觸發電路，受控於比較信號Kflag的觸發(例如比較信號Kflag由一低電位改變為一高電位)，而產生控制信號CK。控制信號CK用以使檢測放大器31將電容基線檢測信號SS與一個校正信號(圖3未繪示)相減，使得檢測放大器31的輸入端(連接電極E的端點)所接收到的信號由原本的電容基線檢測信號SS改變為剩下電容基線檢測信號SS減去一個校正信號。由於檢測結果信號Vout是隨著電容基線檢測信號SS而改變(例如：檢測結果信號Vout與電容基線檢測信號SS成正比)，因此，當電容基線檢測信號SS減去一個校正信號時，檢測結果信號Vout也會減少，藉此達到讓檢測結果信號Vout低於臨界值Th的目的。 The correction unit 33 is controlled by the comparison signal Kflag. For example, the correction unit 33 is a trigger circuit that is controlled by the trigger of the comparison signal Kflag (for example, the comparison signal Kflag is changed from a low potential to a high potential) to generate a control signal. CK. The control signal CK is used to cause the sense amplifier 31 to subtract the capacitance baseline detection signal SS from a correction signal (not shown in FIG. 3), so that the signal received by the input terminal of the sense amplifier 31 (the end point of the connection electrode E) is The original capacitance baseline detection signal SS is changed to the remaining capacitance baseline detection signal SS minus one correction signal. Since the detection result signal Vout changes with the capacitance baseline detection signal SS (for example, the detection result signal Vout is proportional to the capacitance baseline detection signal SS), when the capacitance baseline detection signal SS subtracts a correction signal, the detection result signal Vout is also reduced, thereby achieving the purpose of making the detection result signal Vout lower than the critical value Th.

換句話說，當檢測結果信號Vout大於參考信號Vref時，檢測放大器31依據校正單元33的控制信號CK而將電容基線檢測信號SS減去校正信號，以使檢測放大器31產生的檢測結果信號Vout低於一個所設定臨界值。電容基線檢測信號SS與校正信號的相減可以是即時的，隨著檢測結果信號Vout而適應性改變的。 In other words, when the detection result signal Vout is greater than the reference signal Vref, the sense amplifier 31 subtracts the correction signal from the capacitance baseline detection signal SS according to the control signal CK of the correction unit 33, so that the detection result signal Vout generated by the detection amplifier 31 is low. Set a threshold for one. The subtraction of the capacitance baseline detection signal SS from the correction signal can be instantaneous and adaptively changes with the detection result signal Vout.

另外，在一實施例中，當檢測結果信號Vout大於參考信號Vref時，檢測放大器31可以依據控制信號CK而在一個預設時間內使電容基線檢測信號SS與校正信號彼此相減。所述預設時間可以依據電容基線檢測信號SS的信號變化幅度(波形的平緩或陡峭)來調整，藉此，電容基線檢測信號SS與校正信號的相減也可以是持續的維持一段所設定的預設時間。 In addition, in an embodiment, when the detection result signal Vout is greater than the reference signal Vref, the sense amplifier 31 may subtract the capacitance baseline detection signal SS and the correction signal from each other for a preset time according to the control signal CK. The preset time may be adjusted according to a signal variation amplitude (smooth or steep waveform) of the capacitance baseline detection signal SS, whereby the subtraction of the capacitance baseline detection signal SS and the correction signal may also be maintained for a sustained period of time. Preset time.

為了達到信號校正的目的，當檢測結果信號Vout大於參考信號Vref時，校正信號可以為第一準位Va，如圖2所示。當檢測結果信號Vout不大於參考信號Vref時，校正信號為第二準位Vb。與傳統的做法不同的是，本發明實施例的面板時間延遲檢測電路3是針對每一個被偵測的電極的電容基線檢測信號SS作即時的、適應性的基線校正。本實施例所提供的校正信號在電容基線檢測信 號SS大於臨界值Th時，立即產生校正信號，不會有校正信號與電容基線檢測信號SS位於時間軸上的不同位置的問題。值得一提的是，所述校正信號是依據檢測放大器31的設計而有所不同，請參見後續實施例的說明。 For the purpose of signal correction, when the detection result signal Vout is greater than the reference signal Vref, the correction signal may be the first level Va, as shown in FIG. When the detection result signal Vout is not greater than the reference signal Vref, the correction signal is the second level Vb. Different from the conventional method, the panel time delay detecting circuit 3 of the embodiment of the present invention performs an instantaneous and adaptive baseline correction for the capacitance baseline detection signal SS of each detected electrode. The correction signal provided in this embodiment is in the capacitance baseline detection signal. When the SS is larger than the threshold Th, the correction signal is immediately generated, and there is no problem that the correction signal and the capacitance baseline detection signal SS are located at different positions on the time axis. It is worth mentioning that the correction signal is different according to the design of the detection amplifier 31, please refer to the description of the subsequent embodiments.

〔應用於觸控面板基線校正的面板時間延遲檢測電路之另一實施例〕 [Another embodiment of a panel time delay detecting circuit applied to touch panel baseline correction]

請參照圖4，圖4是本發明另一實施例提供的應用於觸控面板基線校正的面板時間延遲檢測電路的電路圖。面板時間延遲檢測電路4包括檢測放大器41、比較器42與校正單元43，在本實施例中校正單元43也可以稱為基線校正控制器(Baseline Calibration Controller)。圖4提供了將一種檢測放大器41應用於面板時間延遲檢測電路4。 Please refer to FIG. 4. FIG. 4 is a circuit diagram of a panel time delay detecting circuit applied to a touch panel baseline correction according to another embodiment of the present invention. The panel time delay detecting circuit 4 includes a detecting amplifier 41, a comparator 42 and a correcting unit 43, which in the present embodiment may also be referred to as a Baseline Calibration Controller. FIG. 4 provides the application of a sense amplifier 41 to the panel time delay detecting circuit 4.

如圖4所示，檢測放大器41連接觸控面板之電極E，在本實施例中電極E以電路的節點表示。電容Cm的一端接收驅動信號Vdrv，另一端連接電極E，此電容Cm代表互容，接收驅動信號Vdrv的電極與所極E之間的互容為電容Cm。面板時間延遲檢測電路4是用於連接至電極E以檢測其互容的電容值。 As shown in FIG. 4, the detecting amplifier 41 is connected to the electrode E of the touch panel, and in the embodiment, the electrode E is represented by a node of the circuit. One end of the capacitor Cm receives the driving signal Vdrv, and the other end is connected to the electrode E. The capacitor Cm represents mutual capacitance, and the mutual capacitance between the electrode receiving the driving signal Vdrv and the pole E is the capacitance Cm. The panel time delay detecting circuit 4 is a capacitance value for connecting to the electrode E to detect its mutual capacitance.

比較器42耦接檢測放大器41，校正單元43耦接檢測放大器41以及比較器42。當檢測結果信號Vout大於參考信號Vref時，檢測放大器41依據校正單元43的控制信號CK而將電容基線檢測信號SS減去校正信號，以使檢測放大器41產生的檢測結果信號Vout低於一個所設定臨界值Th。所述校正信號可以是圖4中的電流I1或電流I2。 The comparator 42 is coupled to the sense amplifier 41, and the correction unit 43 is coupled to the sense amplifier 41 and the comparator 42. When the detection result signal Vout is greater than the reference signal Vref, the detection amplifier 41 subtracts the correction signal from the capacitance baseline detection signal SS according to the control signal CK of the correction unit 43 so that the detection result signal Vout generated by the detection amplifier 41 is lower than a set value. The critical value Th. The correction signal may be current I1 or current I2 in FIG.

檢測放大器41的細部電路請參照下面的說明。在本實施例中，檢測放大器41包括至少一電流源(411或412)、至少一開關單元413或414、電流鏡單元415與電容Cint。本發明並不限定電流源與開關單元的數目與連接關係。電流源(411或412)用以產生電流(I1或I2)，電流(I1或I2)代表所述校正信號。開關單元耦接電流 源(411或412)以及校正單元43，接收校正單元43之控制信號CK，並依據控制信號CK控制電流源(411或412)是否耦接觸控面板之電極E。 For the detailed circuit of the sense amplifier 41, please refer to the following description. In the present embodiment, the sense amplifier 41 includes at least one current source (411 or 412), at least one switching unit 413 or 414, a current mirror unit 415, and a capacitor Cint. The invention does not limit the number and connection relationship of the current source and the switching unit. A current source (411 or 412) is used to generate a current (I1 or I2), and a current (I1 or I2) represents the correction signal. Switch unit coupled to current The source (411 or 412) and the correction unit 43 receive the control signal CK of the correction unit 43, and control whether the current source (411 or 412) is coupled to the electrode E of the touch panel according to the control signal CK.

電流鏡單元415，具第一端A與第二端A，第一端A用以耦接於電極E，電流鏡單元415對由電極E所接收的電容基線檢測信號SS做相位反轉，並於電流鏡單元415之該第二端B產生檢測結果信號Vout，其中檢測結果信號Vout與電容基線檢測信號SS的相位相反。電容之第一端連接電流鏡單元415之第二端B，電容之第二端連接接地GND。當檢測結果信號Vout大於參考信號Vref時，開關單元(413或414)依據控制信號CK而將電容基線檢測信號SS減去電流源(411或412)之電流(I1或I2)。本實施例的圖4僅是檢測放大器41的一種實現方式，本發明也不限定電流源(411或412)、開關單元(413或414)以及電流鏡單元415的實現方式。 The current mirror unit 415 has a first end A and a second end A. The first end A is coupled to the electrode E, and the current mirror unit 415 performs phase reversal on the capacitance baseline detection signal SS received by the electrode E. The detection result signal Vout is generated at the second end B of the current mirror unit 415, wherein the detection result signal Vout is opposite to the phase of the capacitance baseline detection signal SS. The first end of the capacitor is connected to the second end B of the current mirror unit 415, and the second end of the capacitor is connected to the ground GND. When the detection result signal Vout is greater than the reference signal Vref, the switching unit (413 or 414) subtracts the current (I1 or I2) of the current source (411 or 412) from the capacitance baseline detection signal SS according to the control signal CK. FIG. 4 of the present embodiment is only one implementation of the sense amplifier 41, and the present invention does not limit the implementation of the current source (411 or 412), the switch unit (413 or 414), and the current mirror unit 415.

更詳細地說，如圖4所示檢測放大器41包括第一電流源411、第二電流源412、第一開關單元413、第二開關單元414、電流鏡單元415與電容Cint。第一電流源411耦接供應電壓VDD，產生第一電流I1。第二電流源412耦接接地GND，產生第二電流I2，所述第一電流I1以及第二電流I2代表校正信號。第一開關單元413耦接第一電流源411以及校正單元43，受控於校正單元43之控制信號CK，並依據控制信號CK控制第一電流源411是否耦接觸控面板之電極E。換句話說，第一開關單元413控制第一電流源411的第一電流I1是否流入電極E，因此第一電流I1可以做為校正信號。 In more detail, the sense amplifier 41 as shown in FIG. 4 includes a first current source 411, a second current source 412, a first switching unit 413, a second switching unit 414, a current mirror unit 415, and a capacitor Cint. The first current source 411 is coupled to the supply voltage VDD to generate a first current I1. The second current source 412 is coupled to the ground GND to generate a second current I2, and the first current I1 and the second current I2 represent a correction signal. The first switch unit 413 is coupled to the first current source 411 and the correction unit 43, controlled by the control signal CK of the correction unit 43, and controls whether the first current source 411 is coupled to the electrode E of the touch panel according to the control signal CK. In other words, the first switching unit 413 controls whether the first current I1 of the first current source 411 flows into the electrode E, and thus the first current I1 can be used as a correction signal.

第二開關單元414耦接第二電流源412以及校正單元43，受控於校正單元43之控制信號CK，並依據控制信號CK控制第二電流源412是否耦接觸控面板之電極E。換句話說，第二開關單元414控制第二電流源412的第二電流I2是否流入電極E，因此第二電流I2可以做為校正信號。 The second switch unit 414 is coupled to the second current source 412 and the correction unit 43, controlled by the control signal CK of the correction unit 43, and controls whether the second current source 412 is coupled to the electrode E of the touch panel according to the control signal CK. In other words, the second switching unit 414 controls whether the second current I2 of the second current source 412 flows into the electrode E, and thus the second current I2 can be used as a correction signal.

更進一步，電流鏡單元415包括P型電晶體P1、P2、P3與N型電晶體N1、N2、N3。電流鏡單元415由兩個電流鏡所組成，兩個電流鏡的兩端彼此連接，且兩電流鏡的另外兩端分別連接供應電壓VDD與接地GND。上述其中一個電流鏡由P型電晶體P1、P2與N型電晶體N1所組成且被施加偏壓biasa，而上述另一個電流鏡則由P型電晶體P3與N型電晶體N2、N3所組成且被施加偏壓biasb。 Further, the current mirror unit 415 includes P-type transistors P1, P2, P3 and N-type transistors N1, N2, N3. The current mirror unit 415 is composed of two current mirrors, and two ends of the two current mirrors are connected to each other, and the other ends of the two current mirrors are respectively connected with the supply voltage VDD and the ground GND. One of the above current mirrors is composed of a P-type transistor P1, P2 and an N-type transistor N1 and is biased biasa, and the other current mirror is composed of a P-type transistor P3 and an N-type transistor N2, N3. Composition and biased biasb.

接著，進一步地說明電流鏡單元415的詳細結構。P型電晶體P1、P2的源極連接供應電壓VDD，且P型電晶體P1、P2的閘極彼此連接。N型電晶體N1的汲極連接P型電晶體P1的閘極與汲極，且N型電晶體N1的源極與P型電晶體P2的汲極分別連接第一端A與第二端B，其中第一端A用以接收代表電容基線檢測信號SS的輸入電流，且第二端B用以將檢測結果信號Vout輸出至後續的信號取樣電路(例如：圖3的類比/數位轉換器34)。 Next, the detailed structure of the current mirror unit 415 will be further described. The sources of the P-type transistors P1, P2 are connected to the supply voltage VDD, and the gates of the P-type transistors P1, P2 are connected to each other. The drain of the N-type transistor N1 is connected to the gate and the drain of the P-type transistor P1, and the source of the N-type transistor N1 and the drain of the P-type transistor P2 are respectively connected to the first end A and the second end B The first end A is configured to receive an input current representative of the capacitance baseline detection signal SS, and the second end B is configured to output the detection result signal Vout to a subsequent signal sampling circuit (eg, the analog/digital converter 34 of FIG. 3) ).

N型電晶體N2、N3的源極連接接地GND，且N型電晶體N2、N3的閘極彼此連接。P型電晶體P3的汲極連接N型電晶體N2的閘極與汲極，且P型電晶體P3的源極與N型電晶體N3的汲極分別連接第一端A與第二端B。電容之Cint的第一端連接電流鏡單元415之第二端B，電容Cint之第二端連接接地GND。 The sources of the N-type transistors N2 and N3 are connected to the ground GND, and the gates of the N-type transistors N2 and N3 are connected to each other. The drain of the P-type transistor P3 is connected to the gate and the drain of the N-type transistor N2, and the source of the P-type transistor P3 and the drain of the N-type transistor N3 are respectively connected to the first end A and the second end B . The first end of the capacitor Cint is connected to the second end B of the current mirror unit 415, and the second end of the capacitor Cint is connected to the ground GND.

簡單地說，電流鏡單元415的電路結構可以敘述如下。電流鏡單元415具有第一電流鏡(由P型電晶體P1、P2所組成)、第一偏壓電晶體(即N型電晶體N1)、第二偏壓電晶體(即P型電晶體P3)以及第二電流鏡(由N型電晶體N2、N3所組成)。第一電流鏡以及第二電流鏡分別連接至高電壓VDD以及接地GND。第一電流鏡之輸入端以及第二電流鏡之輸入端分別透過第一偏壓電晶體(N型電晶體N1)以及第二偏壓電晶體(P型電晶體P3)連接至電流鏡單元415之第一端A。第一電流鏡之輸出端以及第二電流鏡之輸出端連接至電流鏡單元415之第二端B。 Briefly, the circuit configuration of the current mirror unit 415 can be described as follows. The current mirror unit 415 has a first current mirror (composed of P-type transistors P1, P2), a first bias transistor (ie, N-type transistor N1), and a second bias transistor (ie, P-type transistor P3) And a second current mirror (consisting of N-type transistors N2, N3). The first current mirror and the second current mirror are respectively connected to the high voltage VDD and the ground GND. The input end of the first current mirror and the input end of the second current mirror are respectively connected to the current mirror unit 415 through the first bias transistor (N-type transistor N1) and the second bias transistor (P-type transistor P3). The first end A. The output of the first current mirror and the output of the second current mirror are coupled to the second end B of the current mirror unit 415.

基於圖4的電路，當檢測結果信號Vout大於參考信號Vref時，第一開關單元413以及第二開關單元414依據控制信號CK而將電容基線檢測信號SS減去第一電流源411之第一電流I1以及第二電流源412之第二電流I2。電容基線檢測信號SS與校正信號(第一電流I1以及第二電流I2)的相減可以是即時的，隨著檢測結果信號Vout而適應性改變的。 Based on the circuit of FIG. 4, when the detection result signal Vout is greater than the reference signal Vref, the first switching unit 413 and the second switching unit 414 subtract the first current of the first current source 411 from the capacitance baseline detection signal SS according to the control signal CK. I1 and a second current I2 of the second current source 412. The subtraction of the capacitance baseline detection signal SS from the correction signal (the first current I1 and the second current I2) may be instantaneous, and adaptively changes with the detection result signal Vout.

另外，在一實施例中，當檢測結果信號Vout大於參考信號Vref時，檢測放大器31可以依據控制信號CK而在一個預設時間內使電容基線檢測信號SS與校正信號彼此相減。如圖4所示，所述控制信號CK可使第一開關單元413與第二開關單元413導通一個預設時間，以使在預設時間內，電容基線檢測信號SS與校正信號(包括第一電流I1和第二電流I2)彼此相減。藉此，電容基線檢測信號SS與校正信號(第一電流I1以及第二電流I2)的相減也可以是持續的維持一段所設定的預設時間。另外，本發明也不限定第一電流I1和第二電流I2的大小。 In addition, in an embodiment, when the detection result signal Vout is greater than the reference signal Vref, the sense amplifier 31 may subtract the capacitance baseline detection signal SS and the correction signal from each other for a preset time according to the control signal CK. As shown in FIG. 4, the control signal CK can cause the first switching unit 413 and the second switching unit 413 to be turned on for a preset time, so that the capacitance baseline detection signal SS and the correction signal (including the first The current I1 and the second current I2) are subtracted from each other. Thereby, the subtraction of the capacitance baseline detection signal SS and the correction signal (the first current I1 and the second current I2) may also be continued for a preset preset time. Further, the present invention does not limit the magnitudes of the first current I1 and the second current I2.

〔實施例的可能功效〕 [Possible effects of the examples]

綜上所述，本發明實施例所提供的一種應用於觸控面板基線校正的面板時間延遲檢測電路，其可對觸控面板進行即時的基線校正。所述面板時間延遲檢測電路可提供電阻-電容延遲的即時監測，且是自動的、適應性的校正。所述面板時間延遲檢測電路是獨立的檢測機制，方便地結合至現有的觸控面板的檢測電路的架構中。另外，本發明實施例所提供的面板時間延遲檢測電路可透過電流放大器的電流操作模式達到所述的自動的、適應性的校正。 In summary, the present invention provides a panel time delay detecting circuit applied to a touch panel baseline correction, which can perform immediate baseline correction on the touch panel. The panel time delay detection circuit provides instant monitoring of the resistance-capacitance delay and is an automatic, adaptive correction. The panel time delay detection circuit is an independent detection mechanism and is conveniently incorporated into the architecture of the detection circuit of the existing touch panel. In addition, the panel time delay detecting circuit provided by the embodiment of the present invention can achieve the automatic and adaptive correction through the current operation mode of the current amplifier.

以上所述僅為本發明之實施例，其並非用以侷限本發明之專利範圍。 The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

3‧‧‧面板時間延遲檢測電路 3‧‧‧ Panel time delay detection circuit

31‧‧‧檢測放大器 31‧‧‧Detection amplifier

32‧‧‧比較器 32‧‧‧ comparator

33‧‧‧校正單元 33‧‧‧Correction unit

34‧‧‧類比/數位轉換器 34‧‧‧ Analog/Digital Converter

Vdrv‧‧‧驅動信號 Vdrv‧‧‧ drive signal

SS‧‧‧電容基線檢測信號 SS‧‧‧Capacitor Baseline Detection Signal

E‧‧‧電極 E‧‧‧electrode

C‧‧‧電容 C‧‧‧ capacitor

Vout‧‧‧檢測結果信號 Vout‧‧‧ test result signal

Vref‧‧‧參考信號 Vref‧‧‧ reference signal

Kflag‧‧‧比較信號 Kflag‧‧‧ comparison signal

CK‧‧‧控制信號 CK‧‧‧ control signal

Dout‧‧‧數位信號 Dout‧‧‧ digital signal

Claims (10)

一種應用於觸控面板基線校正的面板時間延遲檢測電路，包括：一檢測放大器，接收來自該觸控面板之一電極的一電容基線檢測信號，該檢測放大器將該電容基線檢測信號轉換為一檢測結果信號；一比較器，耦接該檢測放大器，將該檢測結果信號與一參考信號做比較，據此產生一比較信號；以及一校正單元，耦接該檢測放大器以及該比較器，該校正單元依據該比較信號產生一控制信號，並將該控制信號傳送至該檢測放大器，用以控制該檢測放大器校正該檢測結果信號；其中，當該檢測結果信號大於該參考信號時，該檢測放大器依據該控制信號而將該電容基線檢測信號減去一校正信號，以使該檢測放大器產生的該檢測結果信號低於一臨界值。 A panel time delay detecting circuit applied to a touch panel baseline correction includes: a detecting amplifier receiving a capacitance baseline detecting signal from an electrode of the touch panel, the detecting amplifier converting the capacitance baseline detecting signal into a detecting a result signal; a comparator coupled to the sense amplifier, comparing the detection result signal with a reference signal, thereby generating a comparison signal; and a correction unit coupled to the sense amplifier and the comparator, the correction unit Generating a control signal according to the comparison signal, and transmitting the control signal to the detection amplifier for controlling the detection amplifier to correct the detection result signal; wherein, when the detection result signal is greater than the reference signal, the detection amplifier is configured according to the The control signal subtracts a correction signal from the capacitance baseline detection signal such that the detection result signal generated by the detection amplifier is below a threshold. 根據請求項第1項之面板時間延遲檢測電路，其中該參考信號代表該臨界值，該面板時間延遲檢測電路使該檢測放大器產生的該檢測結果信號低於該參考信號。 According to the panel time delay detecting circuit of claim 1, wherein the reference signal represents the threshold, the panel time delay detecting circuit causes the detection result signal generated by the detecting amplifier to be lower than the reference signal. 根據請求項第1項之面板時間延遲檢測電路，更包括：一類比/數位轉換器，耦接該檢測放大器，將該檢測結果信號轉換為一數位信號。 The panel time delay detecting circuit according to Item 1 of the claim further includes: an analog/digital converter coupled to the detecting amplifier to convert the detection result signal into a digital signal. 根據請求項第1項之面板時間延遲檢測電路，其中該檢測放大器包括：至少一電流源，產生一電流，該電流代表該校正信號；至少一開關單元，耦接該電流源以及該校正單元，接收該校正單元之該控制信號，並依據該控制信號控制該電流源是否耦接該觸控面板之該電極；一電流鏡單元，具一第一端與一第二端，該第一端用以耦接於該電極，該電流鏡單元對由該電極所接收的該電容基線檢測信 號做相位反轉，並於該電流鏡單元之該第二端產生該檢測結果信號，其中該檢測結果信號與該電容基線檢測信號的相位相反；以及一電容，該電容之第一端連接該電流鏡單元之該第二端，該電容之第二端連接一接地；其中，當該檢測結果信號大於該參考信號時，該開關單元依據該控制信號而將該電容基線檢測信號減去該電流源之該電流。 The panel time delay detecting circuit of claim 1, wherein the detecting amplifier comprises: at least one current source, generating a current, the current representing the correction signal; at least one switching unit coupled to the current source and the correcting unit, Receiving the control signal of the correction unit, and controlling whether the current source is coupled to the electrode of the touch panel according to the control signal; a current mirror unit having a first end and a second end, wherein the first end is used To couple to the electrode, the current mirror unit detects the capacitance baseline signal received by the electrode The phase inversion is performed, and the detection result signal is generated at the second end of the current mirror unit, wherein the detection result signal is opposite to a phase of the capacitance baseline detection signal; and a capacitor is connected to the first end of the capacitor The second end of the current mirror unit is connected to a ground; wherein, when the detection result signal is greater than the reference signal, the switch unit subtracts the current from the capacitance baseline detection signal according to the control signal The current of the source. 根據請求項第1項之面板時間延遲檢測電路，其中該檢測放大器包括：一第一電流源，耦接一供應電壓，產生一第一電流；一第二電流源，耦接一接地，產生一第二電流，該第一電流以及該第二電流代表該校正信號；一第一開關單元，耦接該第一電流源以及該校正單元，受控於該校正單元之該控制信號，並依據該控制信號控制該第一電流源是否耦接該觸控面板之該電極；一第二開關單元，耦接該第二電流源以及該校正單元，受控於該校正單元之該控制信號，並依據該控制信號控制該第二電流源是否耦接該觸控面板之該電極；一電流鏡單元，具一第一端與一第二端，該第一端用以耦接於該電極，該電流鏡單元對由該電極所接收的該電容基線檢測信號做相位反轉，並於該電流鏡單元之該第二端產生該檢測結果信號，其中該檢測結果信號與該電容基線檢測信號的相位相反；以及一電容，該電容之第一端連接該電流鏡單元之該第二端，該電容之第二端連接該接地；其中，當該檢測結果信號大於該參考信號時，該第一開關單元以及該第二開關單元依據該控制信號而將該電容基線檢測信號減去該第一電流源之該第一電流以及該第二電流源之該第二電流。 The panel time delay detecting circuit of claim 1, wherein the detecting amplifier comprises: a first current source coupled to a supply voltage to generate a first current; and a second current source coupled to a ground to generate a a second current, the first current and the second current represent the correction signal; a first switching unit coupled to the first current source and the correction unit, controlled by the control signal of the correction unit, and The control signal controls whether the first current source is coupled to the electrode of the touch panel; a second switch unit coupled to the second current source and the correction unit is controlled by the control signal of the correction unit, and is controlled by The control signal controls whether the second current source is coupled to the electrode of the touch panel; a current mirror unit having a first end and a second end, the first end being coupled to the electrode, the current The mirror unit performs phase inversion on the capacitance baseline detection signal received by the electrode, and generates the detection result signal at the second end of the current mirror unit, wherein the detection result signal and the capacitance baseline detection a phase of the signal is opposite; and a capacitor, the first end of the capacitor is connected to the second end of the current mirror unit, and the second end of the capacitor is connected to the ground; wherein, when the detection result signal is greater than the reference signal, the The first switching unit and the second switching unit subtract the first current of the first current source and the second current of the second current source according to the control signal. 根據請求項第4項之面板時間延遲檢測電路，其中該電流鏡單元具有一第一電流鏡、一第一偏壓電晶體、一第二偏壓電晶體以及一第二電流鏡，該第一電流鏡以及該第二電流鏡分別連接至一供應電壓以及該接地，該第一電流鏡之輸入端以及該第二電流鏡之輸入端分別透過該第一偏壓電晶體以及該第二偏壓電晶體連接至該電流鏡單元之該第一端，其中該第一電流鏡之輸出端以及該第二電流鏡之輸出端連接至該電流鏡單元之該第二端。 The panel time delay detecting circuit of claim 4, wherein the current mirror unit has a first current mirror, a first bias transistor, a second bias transistor, and a second current mirror, the first The current mirror and the second current mirror are respectively connected to a supply voltage and the ground, and the input end of the first current mirror and the input end of the second current mirror respectively pass through the first bias transistor and the second bias The transistor is coupled to the first end of the current mirror unit, wherein the output of the first current mirror and the output of the second current mirror are coupled to the second end of the current mirror unit. 根據請求項第5項之面板時間延遲檢測電路，其中該電流鏡單元具有一第一電流鏡、一第一偏壓電晶體、一第二偏壓電晶體以及一第二電流鏡，該第一電流鏡以及該第二電流鏡分別連接至該供應電壓以及該接地，該第一電流鏡之輸入端以及該第二電流鏡之輸入端分別透過該第一偏壓電晶體以及該第二偏壓電晶體連接至該電流鏡單元之該第一端，其中該第一電流鏡之輸出端以及該第二電流鏡之輸出端連接至該電流鏡單元之該第二端。 The panel time delay detecting circuit of claim 5, wherein the current mirror unit has a first current mirror, a first bias transistor, a second bias transistor, and a second current mirror, the first The current mirror and the second current mirror are respectively connected to the supply voltage and the ground, and the input end of the first current mirror and the input end of the second current mirror respectively pass through the first bias transistor and the second bias The transistor is coupled to the first end of the current mirror unit, wherein the output of the first current mirror and the output of the second current mirror are coupled to the second end of the current mirror unit. 根據請求項第1項之面板時間延遲檢測電路，其中該檢測放大器是電流放大器。 The panel time delay detecting circuit of claim 1 wherein the sense amplifier is a current amplifier. 根據請求項第1項之面板時間延遲檢測電路，其中當該檢測結果信號大於該參考信號時，該校正信號為一第一準位，當該檢測結果信號不大於該參考信號時，該校正信號為一第二準位。 The panel time delay detecting circuit according to Item 1 of the claim, wherein the correction signal is a first level when the detection result signal is greater than the reference signal, and the correction signal is when the detection result signal is not greater than the reference signal For a second level. 根據請求項第4項之面板時間延遲檢測電路，其中當該檢測結果信號大於該參考信號時，該檢測放大器在一預設時間內使該電容基線檢測信號與該校正信號彼此相減。 The panel time delay detecting circuit of claim 4, wherein when the detection result signal is greater than the reference signal, the detecting amplifier subtracts the capacitance baseline detecting signal and the correction signal from each other within a predetermined time.
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