CN1041364C - 隧道二极管和具有这种隧道二极管的存储元件 - Google Patents
隧道二极管和具有这种隧道二极管的存储元件 Download PDFInfo
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Abstract
本发明涉及一种隧道二极管,它有二个金属导电电极(1,2)电极间有绝缘介质(3),对电子构成一定的势垒高度,势垒的厚度使电子能穿过势垒从一电极到另一电极。在许多应用中希望隧道二极管保持一定的开关状态。本发明的隧道二极管的特征是介质(3)包括一层铁电体材料,此材料在室温下具有影响势垒高度的剩余极化。因而此隧道二极管有与介质(3)的剩余极化有关的许多开关状态。此开关状态一直保持到介质(3)的极化改变。
Description
本发明涉及一种隧道二极管,它有二个中间带有绝缘介质的金属导电电极,构成对电子具有一定势垒高度的势垒,而且该势垒有一厚度从而在其电压高于阈值电压时电子能穿过势垒从一电极到另一电极。本发明还涉及存储元件。
这样的隧道二极管已在S.M.Sze所著半导体器件物理学的第九章隧道器件中公开。此隧道二极管也称为MIM(“金属-绝缘体-金属”)二极管或MIS(“金属-绝缘体-半导体”)二极管,这里“金属”应理解为指优良导体材料。在两电极间加上超过阈值电压的电压后,电子能穿过隧道从一电极到另一电极。电压低于阈值电压时电子不能跨越势垒。这样的开关元件非常适用于高频。
此公知的隧道二极管的缺点是无存储性能,在许多应用中希望隧道二极管保持一定的开关状态,例如在室温的实际条件下开/关。
本发明的目的是要克服所说的缺点。
按照本发明,用以达到此目的器件的特征是,该介质包括一在室温下为铁电体的材料层,带有影响势垒高度的剩余极化。
从而使隧道二极管按照介质的剩余极化有几个开关状态。极化的数值和方向影响势垒高度,或者换言之,通过铁电体介质的剩余极化改变势垒的形状。在电极上加某一电压,电子穿过介质要取决于势垒高度,所以或多或少的隧道电流能流过隧道二极管。因此此隧道二极管有几个开关状态。此铁电体介质可以从一种极化状态转换到另一种极化状态,由于电压加到电介质从而使铁电体材料的开关电场在介质中得到。此开关状态保持到介质的极化状态改变。
如果介质中存在所谓“陷阱”,在这种情况下,电子借助于陷阱能通过介质(“帮助建立隧道的陷阱”),则介质的厚度可以较大。然而这样的介质难以用可重复的方式制造。铁电体材料层的厚度最好小于100。不借助陷阱在较低电压下建立电子贯穿介质的隧道是可能的。很薄的铁电体材料层已不再能获得二极管特性,而被有一定的低电阻性能的二极管代替。铁电体材料层的厚度最好大于1以获得二极管特性。
铁电体材料层中的剩余极化取决于层的结构在不同方向可以有不同的值。剩余极化的大小和方向增强或减弱,影响加在电极之间的电场,因而影响势垒高度和隧道电流。两电极最好采用几乎是平行板的形状,剩余极化最大分量的方向实质上与板垂直。当电压跨接在两电极上时,剩余极化最大分量的方向与电极间的电场平行或逆平行。此时极化效应对势垒的高度和宽度的影响处于最大。当铁电体材料层,即铁电体介质在单晶金属导电氧化物的电极上外延生长时,能得到这样的材料。铁电体材料层的生长方向要如此选择,铁电体材料的优选的极化轴,即指向剩余极化的最大分量方向,实质上与板垂直。极化方向与加到电极之间的电场平行的,介质有这样一种结构,即剩余极化处于最大状态。此金属导电氧化物层包括诸如镧-键-钴氧化物、钌酸锶、钒酸锶、或掺杂铟的氧化锡等公知的单晶材料。金属导电氧化物和铁电体介质用诸如脉冲激光沉积(PLD)、溅射、分子束外延(MBE)或金属有机化学汽相沉积(MOCVD)等标准工艺制得。此材料可提供在非晶基底上,而金属导电电极最好提供在单晶基底上。单晶基底最好与所用的导电氧化物和铁电体介质一起有令人满意的晶格配合(+-10%)。用外延法提供铁电体提质是较简单的。用于单晶基底的材料实例有钛酸锶、氧化镁。镁-铝氧化物或铌酸锂等。然而硅或镓的砷化物的基底也可以使用适合的缓冲层,例如Pr6O11或CeO2。
在另一个实施例中,介质包括在不同的开关电场改变它们的剩余极化方向的二个或多个铁电体材料层。隧道二极管有二个以上的开关状态。此介质可以,例如在第一电极上以两层不同性质的铁电体的方式生长。在所说的层上还提供第二电极。
在另一个实施例中,隧道二极管包括一电极,其上不只一次地提供了一层铁电体材料和一电极,所以隧道二极管包括几个串联连接的二极管。这种隧道二极管有M(FM)n结构,这里M代表电极,F代表铁电体介质,而指数n表示包括铁电体介质F和电极M的组合(FM)重复几次,从而建立MFM单元的串联电路。介质厚度每次不必相同。为了有可能提供隧道电流介质较薄,由于在两电极间的介质中的所谓针孔,有时电极间会发生短路。电极之间的短路意味着在单一介质的情况下隧道二极管失效。在按照此实施例的隧道二极管中,在单一介质中针孔的出现对隧道二极管不再是致命的。因此使隧道二极管可靠性提高。
根据本发明,当隧道二极管包括若干串联连接的元件时,并要求二种以上不同的开关时,由不同的铁电体材料组成的层,在不同的开关电场能改变它们的剩余极化方向。此隧道二极管有二种以上的开关状态。隧道二极管包括例如MFMF′M或M(FMF′M)这样的结构,这里F和F′是能在不同开关电场改变它们的剩余极化方向的铁氧体材料。隧道电流将随铁电体介质F和F′的剩余极化的大小和方向而增加或减少。隧道二极管有二种以上的开关状态。这样的隧道二极管有高的可靠性。在两介质间另外存在的电极防止在两种铁电体材料中介质区域的连接。
本发明还涉及到包括本发明的隧道二极管的存储元件。公知的存储元件包括电容,在每个电容上电荷量可计量信息量。公知的存储元件的读出是困难的。在读出期间将一定电压加到电容,随后测量流向电容的电荷。这种电荷的数量是电容中存在的电荷的度量。在读出之后,最初存在的信息已消失,所以要把它再次写入电容中。在按照本发明的存储元件中,在读出期间将电压加到存储元件上,随后测量通过元件的电流。测量电流比测量电荷容易得多。存储元件中的信息不受读出的影响。本发明的存储元件的读出过程比已知的存储元件的读出过程简单得多。
下面将参照附图结合实施例对本发明进行更详细的说明。
图1示出本发明的隧道二极管;
图2示出已知的隧道二极管的电流-电压特性;
图3示出本发明的隧道二极管的电流-电压特性;
图4示出本发明的存储元件的写入-读出周期;
图5示出本发明的隧道二极管,其中介质包括具有不同的开关电场的二种铁电体材料;
图6示出本发明的隧道二极管,它包括若干串联连接的单元。
各图仅是示意图,未按比例描绘。相应的元件在图中用同样的参考数码标出。
图1示出有两个实质上为平行板型电极1,2的隧道二极管,两电板间有绝缘介质3,构成对电子来说有一势垒高度的势垒,而且此势垒有一厚度,以便在电压高于阈值电压时电子能穿过势垒从一电极到另一电极。此发明也涉及存储元件。
这样的二极管,像隧道二极管或MIM(金属-绝缘体-金属)二极管或MIS(金属-绝缘体-半导体)二极管已经公知。此术语金属应理解为指良导电材料。由于在隧道器件中电荷迁移由电子完成,这样的开关元件是高速的,因而隧道二极管特适用于高频。图2示出一种MIM二极管的电流-电压特性,其中通过二极管的电流I是作为加在电极1,2上的电压的函数绘出。在两电极相同的情况下此电流-电压特性是绕零伏轴对称的。
已知的隧道二极管无存储性能。在许多应用情况下希望隧道二极管在室温这样的实际条件下保持一定的开关状态,例如打开/闭合。这意味着根据二极管的开关状态,在电极1,2上加一给定的电压,有一个以上的电流值的电流通过隧道二极管是可能的。
按照本发明,介质3包括一铁电铁材料层,在室温下具有影响势垒高度的剩余极化。隧道二极管有许多种取决于介质的剩余极化的开关状态。极化的大小和方向增强或减弱了加到两电极间电场的影响,因此影响势垒和隧道电流。介质的极化对加到两电极间电场可以是平行的或逆平行的。在电极上加一定的电压,或多或少都会有隧道电流流过隧道二极管,这取决于铁电体的剩余极化对介质3中的电场是平行的还是逆平行的。隧道二极管有二种不同的开关状态。由于加上电压,铁电体介质可以从一种极化状态转换到另一种极化状态,这就在介质中超过铁电体材料的开关电场。由于开关状态由介质的剩余极化来确定,所以这种开关状态保持到介质的极化状态改变。图3示出按照本发明的具有二个相同电极隧道二极管的电流-电压特性。这种电流-电压特性曲线由二条相应于不同的剩余极化条件的曲线5,6组成。
当电压V未加到隧道二极管时,就没有电流流过该元件(图3中O点)。当电压V加到介质3上,剩余极化抵消了电场影响(极化与所加的电场逆平行)时,电流按曲线5上升。在铁电体介质中用以转换极化的开关电场表示在曲线5上的点8。铁电体介质中的剩余极化相对于电场从逆平行改变到平行。通过隧道二极管的电流上升直到到达曲线6上的点9。当电压进一步增加时,电流将按曲线6上升直到介质击穿。在到达点9后电压下降时,电流将随曲线6下降。当到达曲线6上的点10时,电场变得如此强以致介质的极化再次改变方向。然后电流下降直到到达曲线5上点11处的数值。当电压继续下降时,电流将沿曲线5下降直到介质击穿。如在到达点11后电压上升,电流将随曲线5上升。
事实上,由于电压脉冲以能使介质的剩余极化改变的数值加到介质,隧道二极管转换通断状态。然后隧道二极管在低于剩余极化的开关电场的电压下读出。
图4示出隧道二极管的写-读周期。水平轴代表时间t,垂直轴表示通过隧道二极管的电流I。在t=0瞬间,正电压脉冲以这样数值加到电极,以致超过介质3的开关电场,所以极化方向平行于正电压加到电板上的电场图3曲线6)。为了读出隧道二极管的开关状态,将幅度在O和Vt之间的方波电压加到电极1,2(见图3)。然后一较强的电流流过隧道二极管。此隧道二极管闭合。在t=ts瞬间,负电压脉冲以这样的大小加到电极,以致超过介质3的开关电场,所以极化方向与正电压加到电极的电场逆平行(图3曲线5)。为了读出隧道二极管是否开关元件,将幅度在O和Vt之间的方波加到电极1,2(见图3)。然后一较弱的电流流过隧道二极管。隧道二极管被打开。如果在介质中有所谓陷阱,通过它电子能穿过介质,介质的厚度可以较大(“有助于隧道效应的陷阱”)。然而这种介质是难以制造的。介质3的厚度最好选择得小于100。不使用陷阱就可能在较低电压下使电子穿过介质3的隧道效应。
剩余极化的大小和方向能增强或减弱在电极1,2间所加电场的影响,因此要影响势垒和隧道电流。在一实施例中,使用了其两电极为两个平直的平行板形式的隧道二极管。按照本发明,剩余极化的最大分量的方向4与电场平行或逆平行。极化对势垒大小的影响是在最大值。
当在单晶金属导电氧化物的电极1上外延铁电体介质3时,可获得一另外的优点。介质3有这样一种结构,使剩余极化的值是最大值,而极化方向4与加到电极1,2之间的电场平行。金属导电氧化物层包括诸如镧-锶-钴氧化物、钌酸锶、钒酸锶、或掺杂铟的氧化锡。金属导电氧化物的电极1和铁电体介质3用昭脉冲激光沉积(PLD)、溅射、分子束外延(MBE)或金属有机化学汽相沉积(MOCVD)等标准的工艺方法提供。
材料可以提供在非晶基底15上。然而金属导电电极1最好提供在单晶基底15上。这样的单晶基度最好与所用的电极1的导电氧化物和铁电体介质3有令人满意的配合(晶格位错+-10%)。提供一外延的铁电体介质3是较简单的。可用于单晶基底15的材料是,例如,钛酸锶、氧化镁、镁-铝氧化物或铌酸锂等。也可以使用具有诸如Pr6O11或CeO2这样适当缓冲层的硅或砷化镓基底。
按下述方法制造隧道二极管。基底15使用单晶钛酸锶晶体。这样的晶体相对电极所用的钌酸锶有满意的匹配(1.5%)。钌酸锶是用PLD法在650℃0.2毫巴大气压的氧气氛中形成。以像形成电极1的钌酸锶同样的方法形成一层单晶钛酸铅-锆(PZT)作为铁氧体介质3。用上述工艺得到的典型的钛酸铅锆组合物是PbZ0.05。Ti0.95O3。层3有一外延结构。残余极化约为75μC/cm2。以形成电极1类似的方法形成第二层钌酸锶,以构成第二电极2。借助标准的光刻工艺并通过蚀刻即反应离子蚀刻或氩离子蚀刻构图成电极2和质介质3。此结构被蚀刻成电极2。
用钌酸锶电极1,2和80厚的钛酸铅锆介质3形成图1所示的隧道二极管。图3中的开关点8、10在这种元件中约为0.1V。
在另一实施例中,介质3包括在不同的开关电场能改变它们的残余极化方向的若干铁电体材料。隧道二极管有二种以上的开关状态。图5示出一种隧道二极管,其中介质3以具有不同的铁电体性质的3,6两层的形式生长在第一电极上。第二电极2形成在介质3,6上。作为一种实施例,钛酸锶基底15上再次形成钌酸锶制的第一电极1。50的钛酸铅锆层3用第一实施例类似的方法形成在此电极1上。钛酸铅锆组成的第二铁电体层6以实施例1所述的方法形成在层3上,以公知的方式如此来选择组合物以便与钛酸锆组成的层3相比不同开关电场和剩余极化在这层中完成。介质3有100kV/cm的开关电场和25μC/cm2的残余极化。介质6有30kV/cm的开关电场和25μC/cm2的残余极化。这样的隧道二极管有取决于介质的剩余极化方向的四种开关状态。当我们指示极化方向4具有→和←的从电极1指向电极2的极化或者反之也这样时,则四个开关状态分别是:NO.1:介质3->介质6->;NO.2:介质3->介质6<-;NO.3:介质3<-介质6->;NO.4:介质3<-介质6<-。如果极化有相同数值,仅有三个开关状态,开关状态NO.2和NO.3是一样的。隧道二极管可以交替地有二种以上的不同的铁电体介质。在那种情况下隧道二极管将有相应的多种开关状态。
图6示出又一实施例,其中隧道二极管包括电极1,带电极2的铁电体介质3不止一次的形成在电极1上。因而隧道二极管包括多个串联连接的单元20。隧道二极管有M(FM)n结构,这里M是电极1,2,F是铁电体介质3,指数n是表示包括铁电体介质F和电极M的组合体20(FM)重复n次。由于可能产生电源隧道电源的介质3较薄,所以在介质3中两电极1,2或2,2间有时会因针孔发生极间短路。如果介质的厚度小于20就将更易发生。用单一的介质3,电极间短路意味着隧道二极管失效。
在此隧道二极管的实施例中,在单一介质3中存在针孔对隧道二极管来说已不再是致命的了。因而使隧道二极管的可靠性提高。一附加的优点是元件的开关电压变成由一个元件20构成的隧道二极管的开关电压的n倍那么高。因此,此隧道二极管可以适用于所要求的开关电压。
如果要求二种以上的不同的开关状态,则图6实施例的介质3包括在不同的开关电场能改变它们的残余极化方向的不同的铁电体材料。于是此隧道二极管有二种以上的开关状态。一种隧道二极管有例如MFMF′M或M(FMF′M)n结构,这里F和F′是能在不同的开关电场改变它们的剩余极化方向的铁电体材料。隧道电流取决于铁电体介质F和OF′的剩余极化的大小和方向变得更强或更弱,所以此隧道二极管有二种以上的开关状态。参照图5实施例的上述铁电体介质也可以用于本实施例。
本发明也涉及到包括按照本发明的隧道二极管的存储元件。公知的存储元件包括许多电容,电容上的电荷数值是信息的量度。公知的存储元件的读出是困难的。在读出期间,将一定的电压加给电容,然后测量流向电容的电荷。此电荷的数值是电容器中已有的电荷的量度。在读出之后,原有的信息已消失,所以原有的信息再次被写进电容器。在本发明的存储元件中,在读出期间将电压加到存储元件,随后测量通过存储元件的电流(见图4)。测量电流比例量电荷更简单。存储元件中的信息不受读出的影响。本发明的存储元件的读出过程比公知存储元件的读出过程简单得多。
实际上,存储元件从一种存储状态转换成另一种存储状态,即加到该介质的电压脉冲值使介质的剩余极化改变,或在几个介质时使其中一个介质的剩余极化改变。通过在低于介质3的剩余极化的开关电场所处于的电压下测量通过隧道二极管的电流来读出此存储元件。
本发明不限于上述实施例。可用在基底15上的许多隧道二极管代替简单的隧道二极管,而在此隧道二极管旁边还可以有诸如晶体管、电阻、电容器等其它元件。换言之,隧道二极管可以构成集成电路一部分。
所述实施例涉及对称的隧道二极管。然而另一方面,电极1和电极2可用不同的材料,例如电极1用导电氧化物,电极2用金属。这样的隧道二极管的电流一电压特性曲线是对称的。
铁电体介质可与非铁电体材料组合。因此介质3可由一薄层铁电体材料和外加一薄的绝缘或半导体层组成。由此开关的电压电平可以受到影响,或开关的效果,即通过隧道二极管的电流值可以受影响。使铁电体介质与非铁电体介质组合也是可能的。用这种方法去完成隧道二极的更多的开关状态也是可能的。隧道二极管还可以用作隧道晶体管元件。为此目的,例如本发明的用MFM(M-电极1,F-铁电体介质,M-电极2)代表的隧道二极管与MIM(I代表绝缘介质)一起组合成一用M3FM2IM3代表的隧道晶体管,附加的介质和第三电极形成在本发明的隧道二极管上。本发明的隧道二极管的电极2(M2)同时是MIM的电极。由此构成隧道晶体管,其中发射极接点用M1即MFM的电极1构成,基极接点用M2即MFM的电极2构成,它同时构成MIM的电极,集电极接点用M3即MIM的另一电极构成。使本发明的隧道二极管与半导体P-或n-型区组合也是可能的。于是出现了一种MFPNM结构,它分别具有P和N即P-和n-型导电半导体材料。在这种情况下,电极1作为发射极接点,P-型区作为基区,n-型区作为集电区。上述隧道晶体管有存储功能,即它们能保持一定的开关状态。
Claims (8)
1.一种隧道二极管,它有二个金属导电电极,电极间有绝缘介质,对电子来说构成具有一势垒高度的势垒,此势垒有一厚度从而使电子在电压高于阈值电压时,能穿过势垒从一电极到另一电极,其特征在于介质包括:两层以上的不同铁电材料,这些不同的铁电材料在不同的开关电场下改变它们的残余极化的方向。
2.按照权利要求1所说的隧道二极管,其特征在于这些铁电体材料层的总厚度小于100。
3.按照权利要求1中任一权利要求的隧道二极管,其特征在于这些铁电体材料层的总厚度大于20。
4.按照权利要求1的隧道二极管,其特征在于不同铁电体材料的残余极化的最大分量的方向实质上垂直于导电电极。
5.按照权利要求1的隧道二极管,其特征在于不同铁电体材料层用外延法形成在金属导电电极上,且该导电电极包括单晶金属导电氧化物。
6.按照权利要求5所说的隧道二极管,其特征在于金属导电电极形成在单晶基底上。
7.按照以上权利要求中任一权利要求的隧道二极管,其特征在于在第一导电极上有包括交替的二层以上不同介质材料继而是一导电电极的叠层,且最后的导电电极形成为第二导电电极。
8.一种存储无件,它包括有两个金属导电电极的隧道二极管,电极间有对电子来说构成具有一势垒高度的势垒的绝缘介质,且此绝缘介质有一厚度使电子电压高于阈值电压时能从一电极穿过势垒到另一电极,其特征在于,该隧道二极管的介质包括两层以上的不同的铁电材料,在不同的开关电场下这些不同的铁电材料能改变它们的残余极化方向。
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BE9301369A BE1007865A3 (nl) | 1993-12-10 | 1993-12-10 | Tunnel schakelelement met verschillende blijvende schakeltoestanden. |
BE09301369 | 1993-12-10 |
Publications (2)
Publication Number | Publication Date |
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CN1109639A CN1109639A (zh) | 1995-10-04 |
CN1041364C true CN1041364C (zh) | 1998-12-23 |
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CN94113094A Expired - Fee Related CN1041364C (zh) | 1993-12-10 | 1994-12-09 | 隧道二极管和具有这种隧道二极管的存储元件 |
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US (1) | US5541422A (zh) |
EP (1) | EP0657936B1 (zh) |
JP (1) | JP3950179B2 (zh) |
KR (1) | KR950021729A (zh) |
CN (1) | CN1041364C (zh) |
BE (1) | BE1007865A3 (zh) |
DE (1) | DE69428577T2 (zh) |
Families Citing this family (33)
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JPH06334140A (ja) * | 1992-12-16 | 1994-12-02 | Ricoh Co Ltd | 強誘電体材料および該材料を用いた半導体メモリ、光記録媒体ならびに微小変位制御素子 |
KR970076816A (ko) * | 1996-05-06 | 1997-12-12 | 김광호 | 누설 전류를 이용한 다진법 강유전체 랜덤 액세서 메모리 |
US6091077A (en) * | 1996-10-22 | 2000-07-18 | Matsushita Electric Industrial Co., Ltd. | MIS SOI semiconductor device with RTD and/or HET |
US6548843B2 (en) * | 1998-11-12 | 2003-04-15 | International Business Machines Corporation | Ferroelectric storage read-write memory |
US6693033B2 (en) | 2000-02-10 | 2004-02-17 | Motorola, Inc. | Method of removing an amorphous oxide from a monocrystalline surface |
AU2001264987A1 (en) * | 2000-06-30 | 2002-01-14 | Motorola, Inc., A Corporation Of The State Of Delware | Hybrid semiconductor structure and device |
US6555946B1 (en) | 2000-07-24 | 2003-04-29 | Motorola, Inc. | Acoustic wave device and process for forming the same |
US6638838B1 (en) | 2000-10-02 | 2003-10-28 | Motorola, Inc. | Semiconductor structure including a partially annealed layer and method of forming the same |
US6501121B1 (en) | 2000-11-15 | 2002-12-31 | Motorola, Inc. | Semiconductor structure |
DE10059357A1 (de) * | 2000-11-29 | 2002-06-13 | Forschungszentrum Juelich Gmbh | Verfahren zur Erzeugung eines Tunnelkontaktes sowie Vorrichtung umfassend Mittel zur Erzeugung eines Tunnelkontaktes |
US6673646B2 (en) * | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
US6709989B2 (en) | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
US6693298B2 (en) | 2001-07-20 | 2004-02-17 | Motorola, Inc. | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same |
US20030015708A1 (en) * | 2001-07-23 | 2003-01-23 | Primit Parikh | Gallium nitride based diodes with low forward voltage and low reverse current operation |
US6667196B2 (en) | 2001-07-25 | 2003-12-23 | Motorola, Inc. | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method |
US6639249B2 (en) | 2001-08-06 | 2003-10-28 | Motorola, Inc. | Structure and method for fabrication for a solid-state lighting device |
US6589856B2 (en) | 2001-08-06 | 2003-07-08 | Motorola, Inc. | Method and apparatus for controlling anti-phase domains in semiconductor structures and devices |
US6673667B2 (en) | 2001-08-15 | 2004-01-06 | Motorola, Inc. | Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials |
JP3902023B2 (ja) * | 2002-02-19 | 2007-04-04 | セイコーエプソン株式会社 | 圧電アクチュエータ、液滴噴射ヘッド、およびそれを用いた液滴噴射装置 |
DE10250357A1 (de) * | 2002-10-29 | 2004-05-19 | Infineon Technologies Ag | Ferroelektrische Speicherzelle |
DE10303316A1 (de) * | 2003-01-28 | 2004-08-12 | Forschungszentrum Jülich GmbH | Schneller remanenter Speicher |
US7759713B2 (en) * | 2006-03-06 | 2010-07-20 | Ut-Battelle, Llc | Ferroelectric tunneling element and memory applications which utilize the tunneling element |
US7548455B2 (en) | 2006-05-05 | 2009-06-16 | Rochester Institute Of Technology | Multi-valued logic/memory cells and methods thereof |
FR2946788B1 (fr) * | 2009-06-11 | 2016-11-11 | Thales Sa | Dispositif a resistance ajustable. |
US8586959B2 (en) * | 2010-04-28 | 2013-11-19 | Hewlett-Packard Development Company, L.P. | Memristive switch device |
TWI422042B (zh) * | 2010-11-26 | 2014-01-01 | Univ Nat Chiao Tung | 二極體元件及其製作方法 |
FR2973553B1 (fr) | 2011-03-31 | 2013-03-29 | Thales Sa | Procédé de mise en oeuvre d'une jonction tunnel ferroelectrique, dispositif comprenant une jonction tunnel ferroelectrique et utilisation d'un tel dispositif |
KR101458566B1 (ko) | 2013-05-21 | 2014-11-07 | 재단법인대구경북과학기술원 | 정류소자 및 그의 제조 방법 |
US9318315B2 (en) * | 2013-07-15 | 2016-04-19 | Globalfoundries Inc. | Complex circuit element and capacitor utilizing CMOS compatible antiferroelectric high-k materials |
JP6273384B2 (ja) * | 2014-08-19 | 2018-01-31 | サビック グローバル テクノロジーズ ビー.ブイ. | マルチレベル動作を有する不揮発性強誘電体メモリセル |
JP6813844B2 (ja) * | 2016-09-30 | 2021-01-13 | 国立研究開発法人産業技術総合研究所 | トンネル接合素子及び不揮発性メモリ素子 |
CN110707148B (zh) * | 2019-09-02 | 2021-08-17 | 华南师范大学 | 外延晶片、外延晶片制造方法、二极管及整流器 |
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US5206788A (en) * | 1991-12-12 | 1993-04-27 | Ramtron Corporation | Series ferroelectric capacitor structure for monolithic integrated circuits and method |
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1993
- 1993-12-10 BE BE9301369A patent/BE1007865A3/nl not_active IP Right Cessation
-
1994
- 1994-12-05 EP EP94203528A patent/EP0657936B1/en not_active Expired - Lifetime
- 1994-12-05 DE DE69428577T patent/DE69428577T2/de not_active Expired - Lifetime
- 1994-12-09 KR KR1019940033406A patent/KR950021729A/ko not_active Application Discontinuation
- 1994-12-09 CN CN94113094A patent/CN1041364C/zh not_active Expired - Fee Related
- 1994-12-09 JP JP30643494A patent/JP3950179B2/ja not_active Expired - Fee Related
- 1994-12-12 US US08/353,844 patent/US5541422A/en not_active Expired - Lifetime
Non-Patent Citations (1)
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IBM TECHNICAL DIS LOCURE BULLETIN VOL,13. NO.8 1971.1.8 l.esaki et al "polar switch" * |
Also Published As
Publication number | Publication date |
---|---|
JPH07202227A (ja) | 1995-08-04 |
CN1109639A (zh) | 1995-10-04 |
EP0657936A1 (en) | 1995-06-14 |
US5541422A (en) | 1996-07-30 |
JP3950179B2 (ja) | 2007-07-25 |
DE69428577D1 (de) | 2001-11-15 |
DE69428577T2 (de) | 2002-06-27 |
BE1007865A3 (nl) | 1995-11-07 |
KR950021729A (ko) | 1995-07-26 |
EP0657936B1 (en) | 2001-10-10 |
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