CN110707148B - 外延晶片、外延晶片制造方法、二极管及整流器 - Google Patents
外延晶片、外延晶片制造方法、二极管及整流器 Download PDFInfo
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Abstract
本申请提供一种外延晶片、外延晶片制造方法、二极管及整流器,其中,外延晶片中包括Si基底层;形成于所述Si基底层的绝缘层;形成于所述绝缘层远离所述Si基底层的一面的氮化物半导体层;其中,所述绝缘层的厚度构造成在正向偏置电压下,该绝缘层可以允许电子和空穴通过量子隧穿从该绝缘层一侧穿至另一侧与相应的空穴和电子复合,从而允许正向电流流动。在反向偏向下,该绝缘层可以阻碍自由电子和空穴的形成,从而阻塞反向电流。如此,使外延晶片具有了仅允许电流单向通过的特性,可以被制作成如二极管等于整流器件。
Description
技术领域
本申请涉及半导体器件技术领域,具体而言,涉及一种外延晶片、外延晶片制造方法、二极管及整流器。
背景技术
二极管是一种半导体电子器件,其在正向偏置电压下允许电流流动,而在反向偏置电压下阻塞电流。通常,二极管可以为电子管、固态设备或者机械设备。二极管最重要的应用场景是电流整流器,其可以将交流电转换为电脑、移动电话、电视机或其他日通电器所需的直流电。
在现代电子产品中,固态电流整流器件无处不在。固态电流整流器件可以是P-N结二极管或者金属半导体结二极管(即,肖特基二极管)。在各种设计中,最常用的是P-N结二极管。
对于P-N结二极管,N型半导体(掺杂施主杂质)和P型半导体(掺杂受主杂质)接触。在N型半导体中,自由电子是多数载流子,空穴是少数载流子。在P型半导体中,空穴是多数载流子,自由电子是少数载流子。因此,P-N结二极管被归为双极器件。N型半导体与P型半导体接触后,自由电子从。N型半导体移动至P型半导体。相应地,空穴可以看作从P型半导体移动至N型半导体。这导致了与载流子的流动相反的电势,直到流动停止在平衡状态。这个过程确定了载流子耗尽区域的内建电压。在正向外部偏置电压下,负外部电动势施加到N型半导体,正外部电动势施加到P型半导体。在负外部电动势与正外部电动势间的电势差接近内建电压时,自由电子从N型半导体移动到P型半导体中,在那里与空穴复合。相应地,空穴可以看作从P型半导体移动到N型半导体中,并在那里与自由电子复合。随着外部施加的偏置电压呈指数增加,这产生了大的正向电流成,电流方向是由多数载流子决定的。导通电压取决于使用的半导体的能隙,对于SiP-N结二极管,导通电压通常是0.7V。在反向偏置电压下,只有少数载流子从半导体移动到另一半导体。由于只有很少的少数载流子,反向电流很小。因此,利用允许大的正向电流通过而阻塞反向电流的特性可以实现整流,即仅允许一个方向上的电流流动。
肖特基二极管的工作于此不同,肖特基二极管是使用键合到N型半导体的金属电极构成的纯多数载流子器件,因此肖特基二极管被归为单极器件。对于肖特基二极管,在正向偏置电压下,电子从半导体流向金属,导致电流随偏置电压的阶跃增长。电流取决于在金属半导体界面处形成的肖特基势垒。导通电压通常约为0.3-0.5V,具体取决于所使用的金属。在负向偏置电压下,电流被肖特基势垒阻塞,并且在半导体中形成随偏置电压的增加而延伸的耗尽区。由于没有P型半导体材料,因此肖特基二极管不存在少数载流子。
目前,P-N结二极管和肖特基二极管是仅有的固态电流整流器件,它们都基于有形成半导体到半导体结或半导体到金属结建立能量势垒。
发明内容
本申请的目的之一在于提供一种工作原理与P-N结二极管及肖特基二极管不同的二极管、用于制造该二极管的外延晶片及其制造方法、以及使用该二极管的整流器。
第一方面,本申请提供一种外延晶片,所述外延晶片包括:
Si基底层;
形成于所述Si基底层的绝缘层;
形成于所述绝缘层远离所述Si基底层的一面的氮化物半导体层;
其中,所述绝缘层的厚度构造成允许自由电子通过量子隧穿穿过该绝缘层。
可选地,在上述外延晶片中,所述绝缘层为SiNx薄膜层。
可选地,在上述外延晶片中,所述绝缘层的厚度为1到4纳米。
可选地,在上述外延晶片中,所述绝缘层的厚度为2到3纳米。
可选地,在上述外延晶片中,所述氮化物半导体层为GaN和InN混合制成InGaN层。
可选地,在上述外延晶片中,所述InGaN层中,In含量在30%到80%之间。
可选地,在上述外延晶片中,所述InGaN层的导带与所述Si基底层的价带对齐。
可选地,在上述外延晶片中,InGaN层的厚度在50纳米到2微米之间。
可选地,在上述外延晶片中,所述InGaN层为具有均匀In含量的均匀层或者具有不同In含量的异质结构层。
可选地,在上述外延晶片中,所述InGaN层中InN与GaN的含量比例为46:54。
可选地,在上述外延晶片中,所述Si基底层为P型Si(111)晶片。
第二方面,本申请提供一种外延晶片制造方法,所述方法包括:
提供一Si基底层;
在所述Si基底层的表面形成绝缘层;
在所述绝缘层远离所述Si基底层的一面上形成氮化物半导体层;
其中,所述绝缘层的厚度构造成允许自由电子通过量子隧穿穿过该绝缘层。
可选地,在上述外延晶片制造方法中,所述绝缘层为SiNx薄膜层;形成所述SiNx薄膜层的方式包括分子束外延。
可选地,在上述外延晶片制造方法中,所述绝缘层的厚度为1到4纳米。
可选地,在上述外延晶片制造方法中,所述绝缘层的厚度为2到3纳米。
可选地,在上述外延晶片制造方法中,所述氮化物半导体层为GaN和InN混合制成InGaN层;形成所述InGaN层的方式包括分子束外延。
可选地,在上述外延晶片制造方法中,所述InGaN层中In含量在30%到80%之间。
可选地,在上述外延晶片制造方法中,所述提供一Si基底层包括:
提供一P型Si(111)晶片作为所述Si基底层。
第三方面,本申请提供一种二极管,所述二极管由本申请提供所述外延晶片制成。
第四方面,本申请提供一种整流器,所述整流器包括本申请提供的所述二极管。
本申请提供的方案至少具有以下有益效果:
本申请提供的外延晶片、外延晶片制造方法、二极管及整流器,在Si基底层和氮化物半导体层之间加入了绝缘层,在正向偏置电压下,该绝缘层可以允许电子通过量子隧穿从该绝缘层一侧穿至另一侧与空穴复合,从而允许正向电流流动;在反向偏向下,该绝缘层可以阻碍自由电子和空穴的形成,从而阻塞反向电流。如此,使外延晶片具有了仅允许电流单向通过的特性,可以被制作成如二极管等用于整流器件。
附图说明
为了更清楚地说明本申请实施例的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,应当理解,以下附图仅示出了本申请的某些实施例,因此不应被看作是对范围的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的外延晶片的结构示意图;
图2为绝缘层氮化形成时间为1分钟和5分钟时二极管的电流-电压曲线示意图;
图3为绝缘层氮化形成时间为10分钟和20分钟时二极管的电流-电压曲线示意图;
图4为本申请实施例提供的整流器的电路示意图;
图5为本申请实施例提供的外延晶片制造方法的流程示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本申请一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此,以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围,而是仅仅表示本申请的选定实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步定义和解释。
请参照图1,图1为本实施例提供的一种外延晶片的示意图,该外延晶片至少包括Si基底层11、绝缘层12及氮化物半导体层13。
所述绝缘层12形成于所述Si基底层11的表面,所述氮化物半导体层13形成于所述绝缘层12远离与所述Si基底层11接触的一面。在本实施例中,所述绝缘层12足够薄以允许自由电子的有效地进行量子隧穿,但是足够厚以阻碍自由电子-空穴的产生。相应地,空穴也可以视作能够通过量子隧穿穿过所述绝缘层12。
可选地,在本实施例中,所述绝缘层12可以为形成在上述Si基底层11表面的SiNx薄膜层。SiNx薄膜层可以通过氮化Si基底层11的表面的方式形成。SiNx薄膜层可以通过例如分子束外延生长的方式形成于所述Si基底层11上,并且SiNx薄膜层可以允许在其上生成如InGaN层的氮化物半导体层13。
可选地,在本实施例中,所述绝缘层12的厚度可以为1到4纳米,例如,可以是2到3纳米,以确保电子和空穴可以通过量子隧穿穿过该绝缘层12。
可选地,在本实施例中,所述氮化物半导体层13可以为InGaN层。InGaN层的In含量在30%和80%之间,可以确保Si的价带与InGaN的导带的能带对齐(即Si层的价带与InGaN层的导带对齐)发生在该组分范围内。
可选地,在本实施例中,所述InGaN层中InN与GaN的含量比例为46:54。
由于在Si基底层11上生长的InGaN层中存在固有的晶体缺陷,这种晶体缺陷可以作为供体使InGaN层在没有刻意掺杂的情况下自然地充当N型半导体。因此,在本实施例中,可以将InGaN层作为N型半导体层,将所述Si基底层11作为P型半导体层。其中,所述Si基底层11可以为P型Si(111)晶片。
可选地,在本实施例中,InGaN层的厚度在50纳米到2微米之间,以保证使用本实施例提供的外延晶片制造的平面器件的制造兼容性。
可选地,在本实施例中,所述InGaN层为具有均匀In含量的均匀层,所述InGaN层也可以为具有任何设计和形态的不同In含量的异质结构层,例如平面层,波纹层,纳米线网络或纳米柱。对于所述半导体异质结构,不同成分和/或不同材料的半导体薄膜依次沉积在单个Si基底层11上。由于半导体异质结构可以限制中间层内的电子和空穴,因此通过设置不同的异质结构可以定制InGaN层的电子特性。换句话说,在本实施例中,可以定制InGaN层的电子特性,以便调整由所述外延晶片制成的二极管的电流整流行为。
本实施例还提供一种使用上述外延晶片制造的二极管。
为方便理解本申请提供的方案,下面通过一个例子说明本申请所提供的二极管的工作原理。
以制造所述二极管的外延晶片中,Si基底层11为P型半导体,InGaN层为N型半导体为例。在Si基底层11的价带与InGaN层的导带对齐的情况下,电流不会面对任何势垒,在正向偏置电压和反向偏置电压下均允许电流流动。在能带未对齐的情况下,电流的流动将受到势垒影响。
对于Si基底层11和InGaN层之间没有绝缘层12的情形,当施加正向偏置电压时(即在InGaN层施加负电位),自由电子从InGaN层被驱向到Si-InGaN结与空穴复合,空穴从Si基底层被趋向到Si-InGaN结与电子复合,从而形成正向电流。在能带对齐的情况下,电子和空穴复合,从而产生正向电流。换句话说,正向电流是由电子和空穴复合产生的电流。
当施加反向偏置电压时(即在InGaN层施加正电位),电子被驱离Si-InGaN结,产生自由电子和空穴,从而产生反向电流。完美能带对齐的Si-InGaN结的反向电流呈欧姆特性,即反向电流与施加的电压的呈线性关系。
在本实施例中,在所述Si基底层11和所述InGaN层之间加入了绝缘层12,所述绝缘层12允许自由电子和空穴可以通过量子隧穿穿过该绝缘层12。所述绝缘层12的加入不会改变所述Si基底层11和InGaN层的能带对齐,这是由它们各自的电子亲和力决定的。自由电子和空穴位于所述绝缘层12的不同侧,来自所述InGaN层的自由电子仍然可以隧穿穿过所述绝缘层12与所述Si基底层11的空穴复合,相应地,所述Si基底层11的空穴也可以视作能够穿过所述绝缘层12与InGaN层的自由电子复合。这种自由电子和空穴的移动就产生正向电流。虽然绝缘层12的加入导致增加了隧道电阻,隧道电阻导致正向电流随所施加偏置电压的平方根呈指数增长,当所述绝缘层12的厚度保持很小(约为几纳米)时,相应的导通电压可以保持很低。
反向电流的情况不同,反向电流是基于电子被驱离Si-InGaN结产生的自由电子和空穴而形成的(即电子逃离原子的约束成为自由电子并产生空穴)。与自由电子和空穴复合不同,自由电子和空穴的产生必须在Si-InGaN结处同时发生,并且由于电荷守恒,自由电子和空穴必须贡献同等地的电流。因此,加入到Si-InGaN结的所述绝缘层12会强烈地阻碍了自由电子和空穴的产生,即反向电流被阻止。
在本实施例中,对于绝缘层12的厚度存在折衷,其足够薄以允许自由电子的有效地进行量子隧穿,但是足够厚以保证能阻碍Si-InGaN结处的自由电子和空穴产生。如此,在该Si-InGaN结,正向电流被允许,反向电流被阻止,使得该Si-InGaN结具有了整流电流-电压特性。
发明人进行了相关实验,以证实由本实施例提供外延晶片制成的二极管的高性能。
请参照图2和图3,示出了不同的绝缘层12氮化形成时间下,本实施例提供的二极管的电流-电压曲线。其中,横坐标为在InGaN层施加的电压值,施加正向偏置电压时电压值为负,施加反向偏置电压时电压值为正。
图2分别示出了绝缘层12氮化形成时间为1分钟和5分钟时的二极管电流-电压曲线。可以看出氮化形成时间为1分钟和5分钟时,二极管的电流-电压曲线接近欧姆特性,其中电流-电压曲线通过零点,在较大电压下具有大的斜率。这是由于氮化形成时间过短,形成的绝缘层12过薄导致的。氮化形成时间为1分钟时,电流-电压特性不完全是欧姆特性,是因为实验条件有限未能实现完美的能带对齐导致的。
图3示出了绝缘层12氮化形成时间为10分钟和20分钟时的电流-电压曲线。可以看出,在-0.5V的正向偏置电压是正向电流明显的导通电压,氮化形成时间20分钟的导通电压稍大于氮化形成时间10分钟的导通电压。从图3可以看出,10分钟和20分钟的氮化形成时间形成的绝缘层12,其厚度可以在正向偏置电压下允许隧穿电流,并足够厚能在反向偏置电压下阻止反向电流。
从图2到图3可以看出,随着绝缘层12氮化形成时间增加(即绝缘层12厚度增加),二极管的电流-电压特性成欧姆特性转变为了高度整流特征。
本实施例还提供一种整流器,该整流器包括由上述外延晶片制成的二极管10。该整流器可以是但不仅限于半波整流电路、全波整流电路、桥式整流等。
请参照图4,以半波整流电路为例,所述整流器还可以包括变压器20、电容器40和负载电阻30。交流电(通常是正弦波交流电)输入至变压器20,变压器20可以调节电压。调节后的电压被传递到二极管10。只有当提供正极性电压时(即,当二极管10处于正向偏置电压时),电流才流入负载电阻30。电容器40通过脉动电流的正半波充电,在对应的负半波时间的间隔期间,释放电能到负载电阻30中。以这种方式,脉动电流被平滑或平均地整流为单向,在负载电阻30处提供单向的输出电压。
请参照图5,本实施例还提供一种制造上述外延晶片的方法,该方法可以包括以步骤:
步骤S510,提供一Si基底层。
步骤S520在所述Si基底层的表面形成绝缘层。
步骤S530在所述绝缘层远离所述Si基底层的一面上形成氮化物半导体层。
其中,所述绝缘层的厚度构造成允许自由电子通过量子隧穿穿过该绝缘层。相应地,空穴也可以视为能够通过量子隧穿穿过所述绝缘层。
可选地,在步骤S510中,可以提供一P型Si(111)晶片作为所述Si基底层。
可选地,步骤S520形成所述绝缘层之前,可能需要对所述Si基底层进行预处理,例如进行超声波清洗或高温加热,其具体步骤是本领域技术人员公知的,在此不再赘述。
可选地,在步骤S520中,可以通过表面氮化的方法在Si基底层上形成SiNx薄膜层作为所述绝缘层。所述绝缘层的厚度可以为1到4纳米,例如,可以是2到3纳米。
需要说明的是,在本实施例的其他实施方式中,也可以使用其他任何沉积方法形成所述绝缘层,例如通过化学气相沉积、溅射、蒸发等,由此绝缘层可以由任何绝缘材料形成,例如SiOx、SiNx、SiNOx或其他金属氮化物和氧化物。
可选地,在步骤S530中,所述氮化物半导体层为GaN和InN混合制成InGaN层;形成所述InGaN层的方式包括分子束外延。例如,所述InGaN层可以在300至600℃的温度下生长。InGaN层以可以每小时0.1至1微米的速率生长至50nm至2微米的厚度。所述InGaN层中In含量在30%到80%之间。
通常,外延生长意味着在所述Si基底层上生长满足某些要求并且与所述Si基底层具有良好限定的晶体学关系的单晶层,同时将原始晶片向外扩展到一定程度。外延生长是制造单晶薄膜的技术,这是一种在适当的Si基底层上沿着Si基底层的材料的晶轴方向在适当的Si基底层上逐层生长薄膜的方法。该技术具有以下优点:使用中的Si基底层的低温,对光束通量强度的容易且精确的控制,以及随着光源的变化快速调节膜和层的成分,成分和掺杂浓度的能力。利用这种技术,可以制造厚度为几微米的单晶薄膜,并且可以通过交替生长具有不同组分并掺杂有不同方法的薄膜来形成具有量子微结构的超薄层状材料。上述外延生长方法可以是分子束外延,金属有机气相外延或化学气相沉积方法。分子束外延是一种外延制膜方法,也是一种特殊的真空镀膜工艺。金属有机气相外延和化学气相沉积依赖于气源传递和热解反应,同时进行合成和分解。当氢携带金属有机化合物蒸气和非金属氢化物在生长室内加热的Si基底层上时,发生一系列化学反应并在Si基底层上产生外延层。
若需要由本实施例提供外延晶片制造半导体器件,可以在所述InGaN层上沉积金属触点,例如采用光刻、金属沉积或剥离等方式形成。所述金属可以是Al、Au或Ni等。可以使用相同的金属蒸发背面触点。退火在200至400℃下进行5至10分钟以形成欧姆接触。上述层结构被蚀刻成的,如0.01x0.01平方厘米至0.1x0.1平方厘米。金属线可以粘合到InGaN层上的金属触点和背面触点。
以上所述,仅为本申请的各种实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应所述以权利要求的保护范围为准。
工业实用性
本申请提供的外延晶片、外延晶片制造方法、二极管及整流器,在Si基底层和氮化物半导体层之间加入了绝缘层,在正向偏置电压下,该绝缘层可以允许电子和空穴通过量子隧穿从该绝缘层一侧穿至另一侧与相应的空穴和电子复合,从而允许正向电流流动;在反向偏向下,该绝缘层可以阻碍自由电子和空穴的形成,从而阻塞反向电流。如此,使外延晶片具有了仅允许电流单向通过的特性,可以被制作成如二极管等用于整流器件。
Claims (17)
1.一种外延晶片,其特征在于,所述外延晶片包括:
Si基底层,其中所述Si基底层为P型Si晶片;
形成于所述Si基底层的绝缘层;
形成于所述绝缘层远离所述Si基底层的一面的氮化物半导体层;
其中,所述绝缘层的厚度为1到4纳米,所述绝缘层的厚度使得在正向偏置电压下,允许电子通过量子隧穿从该绝缘层一侧穿至另一侧与空穴复合,从而允许正向电流流动;在反向偏向下,该绝缘层可以阻碍自由电子和空穴的形成,从而阻塞反向电流,其中所述氮化物半导体层为N型InGaN层,并且所述InGaN层的导带与所述Si基底层的价带对齐。
2.根据权利要求1所述的外延晶片,其特征在于,所述绝缘层为SiNx薄膜层。
3.根据权利要求1所述的外延晶片,其特征在于,所述绝缘层的厚度为2到3纳米。
4.根据权利要求1所述的外延晶片,其特征在于,所述氮化物半导体层为GaN和InN混合制成InGaN层。
5.根据权利要求4所述的外延晶片,其特征在于,所述InGaN层中,In含量在30%到80%之间。
6.根据权利要求4所述的外延晶片,其特征在于,InGaN层的厚度在50纳米到2微米之间。
7.根据权利要求4所述的外延晶片,其特征在于,所述InGaN层为具有均匀In含量的均匀层或者具有不同In含量的异质结构层。
8.根据权利要求4所述的外延晶片,其特征在于,所述InGaN层中InN与GaN的含量比例为46:54。
9.根据权利要求1所述的外延晶片,其特征在于,所述Si基底层为P型Si(111)晶片。
10.一种根据权利要求1所述的外延晶片的制造方法,其特征在于,所述方法包括:
提供一Si基底层;
在所述Si基底层的表面形成绝缘层;
在所述绝缘层远离所述Si基底层的一面上形成氮化物半导体层。
11.根据权利要求10所述的外延晶片制造方法,其特征在于,所述绝缘层为SiNx薄膜层;形成所述SiNx薄膜层的方式包括分子束外延。
12.根据权利要求10所述的外延晶片制造方法,其特征在于,所述绝缘层的厚度为2到3纳米。
13.根据权利要求10所述的外延晶片制造方法,其特征在于,所述氮化物半导体层为GaN和InN混合制成InGaN层;形成所述InGaN层的方式包括分子束外延。
14.根据权利要求13所述的外延晶片制造方法,其特征在于,所述InGaN层中In含量在30%到80%之间。
15.根据权利要求10所述的外延晶片制造方法,其特征在于,所述提供一Si基底层包括:
提供一P型Si(111)晶片作为所述Si基底层。
16.一种二极管,其特征在于,所述二极管由权利要求1-9任意一项所述的外延晶片制成。
17.一种整流器,其特征在于,所述整流器包括权利要求16所述的二极管。
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