CN104133095A - Digital-oscilloscope serial-bus I<2>C triggering method - Google Patents
Digital-oscilloscope serial-bus I<2>C triggering method Download PDFInfo
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- CN104133095A CN104133095A CN201410320950.2A CN201410320950A CN104133095A CN 104133095 A CN104133095 A CN 104133095A CN 201410320950 A CN201410320950 A CN 201410320950A CN 104133095 A CN104133095 A CN 104133095A
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Abstract
The invention discloses a digital-oscilloscope serial-bus I<2>C triggering method which includes triggering of a synchronous comparator, triggering of source election, I<2>C asynchronous triggering, triggering hold-off, synchronous triggering, dual-slope expansion, and interpolation counting. An I<2>C asynchronous triggering method includes start, stop, resetting, loss confirmation, E<2>PROM read data, 7bit addressing read-write data and 10bit addressing read-write data. Compared with the prior art, the method has obvious advantages of having rich triggering methods and multiple kinds of functions and being capable of carrying out operations of channel selection, polarity selection, qualifier selection, and address and data value setting and the like; and the method is realized in an FPGA so that a hardware circuit part is saved and the whole machine is high in utilization rate and extremely high in triggering precision and accuracy and according to set conditions, the format of an I<2>C protocol and the positions of trigger points are displayed in the format of pictures in a simple and clear manner.
Description
Technical field
The present invention relates to digital oscilloscope triggering method field, specifically a kind of digital oscilloscope universal serial bus I
2c triggering method.
Background technology
Existing digital oscilloscope triggers type and mainly contains edge, pulsewidth, TV and power supply triggering etc., these several triggering types can meet most application scenario, but in some specific fields, such as universal serial bus, these trigger type and can not meet the demands, for example, for universal serial bus I
2c, in research and development designs application very extensive, be almost seen everywhere.The application of universal serial bus triggering method on digital oscilloscope, will bring great convenience to R&D worker.
Document 1: patent of invention, CN1710429A, wear dagger-axe, a kind of oscilloscope condition triggering method based on finite state machine, 2005.12.21, proposed a kind of triggering method based on finite state machine, system provides four kinds of conditions to user: automatically, edge, overtime, forbid, user can arrange arbitrarily trigger condition, just can realize the polytypes such as edging trigger, pulsewidth triggering, glitch trigger, overtime triggering, delayed trigger.This method has very strong versatility, but does not relate to this specific area of universal serial bus, triggers type perfect not enough.
Document 2: patent of invention, CN102012444A, Su Wangding, He Ruixiong, oscillograph and utilize the method for this oscillograph test serial bus signal, 2011.4.13, proposed a kind of serial bus signal method of testing, detected universal serial bus with picked up signal, and give oscillograph by channel; Oscillograph obtains channel signal, the sequential of identification signal, and show on oscillograph; This invention also provides a kind of oscillograph of testing serial bus signal.This method relates to the test of serial bus signal, but does not have to design for the universal serial bus of particular types, and practicality is not strong.
Summary of the invention
The object of this invention is to provide a kind of digital oscilloscope universal serial bus I
2c triggering method, is being used I to solve
2the problem running into during C communication, can be widely used in all kinds digital oscilloscope.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of digital oscilloscope universal serial bus I
2c triggers, and comprises that triggering synchronous comparer, trigger source are selected, I
2the asynchronous triggering of C, triggering hold-off, synchronous triggering, double slanted expansion, interpolation counting, is characterized in that: can be according to the condition of user's setting, to the I satisfying condition
2c bus, I
2the asynchronous triggering part of C produces asynchronous triggering enable signal.
Described universal serial bus I
2c triggers, and it is characterized in that: digital oscilloscope can be at I
2the beginning of C, stop, restarting, lose confirmation, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger.
Described universal serial bus I
2c triggers, and it is characterized in that: for realizing digital oscilloscope at I
2the beginning of C, stop and restarting on position triggering, in FPGA design, data line SDA is increased to one-level status register.
Described universal serial bus I
2c triggers, and it is characterized in that: for realizing digital oscilloscope at I
2the loss of C is confirmed, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger, two register COUNT and Compare are set in FPGA, the number of COUNT for adding up clock line SCL, Compare is set by the user, and comprises address and data.
Principle of the present invention is: digital oscilloscope universal serial bus I
2c triggers and comprises that triggering synchronous comparer, trigger source are selected, I
2the asynchronous triggering of C, triggering hold-off, synchronous triggering, double slanted expansion and interpolation counting.Signal, after analog channel is processed, enters trigger comparator, and triggering level compares, and produces the pulse signal that hopping edge is exceedingly fast.The output of trigger comparator offers trigger source and selects circuit, carries out trigger source selection and channel selecting.I
2the asynchronous triggering of C is core of the present invention, and the condition of setting according to user, to the I satisfying condition
2c bus, produces asynchronous triggering enable signal, can be at I
2the beginning of C, stop, restarting, lose confirmation, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger.After asynchronous triggering enable signal produces, and sampling major clock carries out synchronously, and generation synchronous triggering signal, gives double slanted expanded circuit, and signal is carried out to broadening, carries out interpolation counting so that follow-up.Interpolation counting comprises smart interpolation counting and thick interpolation counting, for time between calculating sampling point and trigger point accurately.Triggering hold-off is in the special time after asynchronous trigger signal occurs, and does not allow to produce triggering again.
Compared with prior art, its remarkable advantage is in the present invention:
1, abundant I
2c triggering mode;
2, there is the several functions such as channel selecting, polarity selection, qualifier selection, address and data value setting;
3, in FPGA, realize, complete machine utilization factor is high, and has high triggering precision and accuracy;
4,, according to imposing a condition, with the form of picture, demonstrate I
2the form of C agreement and position, trigger point, simple and clear.
Accompanying drawing explanation
Fig. 1 is the present invention trigger theory figure on starting position.
Fig. 2 is that the present invention is set up trigger theory figure in 7bit addressing read data bit.
Fig. 3 is triggering system block diagram of the present invention.
Embodiment
In the present invention, the universal serial bus I of digital oscilloscope
2c triggers, and comprises that triggering synchronous comparer, trigger source are selected, I
2the asynchronous triggering of C, triggering hold-off, synchronous triggering, double slanted expansion, interpolation counting, is characterized in that: can be according to the condition of user's setting, to the I satisfying condition
2c bus, I
2the asynchronous triggering part of C produces asynchronous triggering enable signal.
Digital oscilloscope universal serial bus I of the present invention
2c triggers, can be at I
2the beginning of C, stop, restarting, lose confirmation, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger.
Digital oscilloscope universal serial bus I of the present invention
2c triggers, for realizing digital oscilloscope at I
2the beginning of C, stop and restarting on position triggering, in FPGA design, data line SDA is increased to one-level status register.
Digital oscilloscope universal serial bus I of the present invention
2c triggers, for realizing digital oscilloscope at I
2the loss of C is confirmed, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger, two register COUNT and Compare are set in FPGA, the number of COUNT for adding up clock line SCL, Compare is set by the user, and comprises address and data.
Signal is after analog channel is carried out signal condition, enter trigger comparator, it is high-speed a, high bandwidth, highly sensitive voltage comparator, and triggering level is compared, produce the pulse signal that hopping edge is exceedingly fast, the ADCMP553 that the present invention selects AD company to produce.
The output of trigger comparator offers trigger source and selects circuit, carries out trigger source selection and channel selecting, I
2c has two lines, and SDA and SCL need to use two passages, and the SCL of selector channel, and selection is arbitrarily trigger source passage.
I
2the asynchronous triggering of C is core of the present invention, according to I
2the protocol format of C signal, by I
2c triggers and is divided at I
2the beginning of C, stop and restarting on position trigger and lose confirm, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger two large classes.I
2the asynchronous triggering of C realizes in FPGA, and complete machine utilization factor is high, and has high triggering precision.
In conjunction with Fig. 1, be universal serial bus I
2c is trigger theory figure on starting position.The present invention adopts 125M clock to sample, and guarantees abundant sampled point, realizes high triggering accuracy.When SCL is high level, SDA changes low level into by high level, and I is described
2c starts condition and occurs, and oscillograph triggers on starting position.Under this triggering mode, need to judge that SDA changes low level into by high level, there is negative edge, now need to consider the situation of FPGA and placement-and-routing comprehensive in the later stage, when adopting VHDL design, SDA must be used as to general data line and treat, therefore can not use " if (sda'event and sda='0') " such statement to judge the generation of SDA negative edge, otherwise can introduce unnecessary clock, affect design result.When SCL is high level, for there is negative edge on judgement data line SDA, need to, for data line SDA increases one-level status register, adopt d type flip flop, by judging adjacent two state value SDA and data, when SDA=0 and data=1 condition meet, negative edge occurs, if triggered, enables enable=1, and asynchronous triggering occurs, if condition does not meet, come back to beginning.
Universal serial bus I
2c triggers and triggers on starting position stopping, restarting on position, and design philosophy is the same.
In conjunction with Fig. 2, be universal serial bus I
2c is set up trigger theory figure in 7bit addressing read data bit.Universal serial bus I
2the frame format of the 7bit addressing read data of C is: ﹣ 7 bit address ﹣ control bits in start bit are read ﹣ acknowledgement bit ﹣ 8 bit data, if all place values all match with setting value in pattern, oscillograph will trigger on the 17th SCL clock edge behind frame start bit.7bit addressing read data triggering mode, has the several functions such as polarity selection, qualifier selection, address and data value setting.In FPGA design, need to arrange two registers, digit counter COUNT and user's setting value Compare.Work as I
2after C starts to occur, the number of COUNT for adding up clock line SCL, Compare is set by the user, and comprises address and data two parts.In order to differentiate the data that send from SDA, need, through going here and there and changing, by N d type flip flop, to be formed, convert parallel data value to.When COUNT=17, value value and Compare value are compared, if equated, and trigger and enable enable=1, asynchronous triggering occurs, if unequal, empties COUNT and value value, comes back to and judges I
2c beginning.
Universal serial bus I
2c is losing confirmation, E
2pROM read data, 7bit addressing are write data, 10bit addressing and are read and write data on position and trigger and be set up triggering in 7bit addressing read data bit, and design philosophy is the same.
I
2after the asynchronous triggering enable signal of C produces, carry out synchronously with sampling major clock, produce synchronous triggering signal, give double slanted expanded circuit, signal is carried out to broadening, so that follow-up, carry out interpolation counting, comprise smart interpolation counting and thick interpolation counting, for time between calculating sampling point and trigger point accurately.Trigger hold-off and be user after asynchronous trigger signal occurs in the fixed time, do not allow to produce again triggering.According to imposing a condition, the form with picture in Software for Design demonstrates I
2the form of C agreement and position, trigger point, simple and clear.
Claims (4)
1. a digital oscilloscope universal serial bus I
2c triggers, and comprises that triggering synchronous comparer, trigger source are selected, I
2the asynchronous triggering of C, triggering hold-off, synchronous triggering, double slanted expansion, interpolation counting, is characterized in that: can be according to the condition of user's setting, to the I satisfying condition
2c bus, I
2the asynchronous triggering part of C produces asynchronous triggering enable signal.
2. universal serial bus I according to claim 1
2c triggers, and it is characterized in that: digital oscilloscope can be at I
2the beginning of C, stop, restarting, lose confirmation, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger.
3. universal serial bus I according to claim 1 and 2
2c triggers, and it is characterized in that: for realizing digital oscilloscope at I
2the beginning of C, stop and restarting on position triggering, in FPGA design, data line SDA is increased to one-level status register.
4. universal serial bus I according to claim 1 and 2
2c triggers, and it is characterized in that: for realizing digital oscilloscope at I
2the loss of C is confirmed, E
2on PROM read data, 7bit addressing read and write data, 10bit addressing reads and writes data position, trigger, two register COUNT and Compare are set in FPGA, the number of COUNT for adding up clock line SCL, Compare is set by the user, and comprises address and data.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101571555A (en) * | 2009-06-10 | 2009-11-04 | 东南大学 | Triggering method for serial peripheral interface bus signal |
| CN101630299A (en) * | 2009-05-27 | 2010-01-20 | 东南大学 | Analysis and trigger method of I2C serial bus signal |
| EP2533022A1 (en) * | 2011-06-10 | 2012-12-12 | Hexagon Technology Center GmbH | Extremely precise synchronised measuring value recording |
| CN103580656A (en) * | 2013-10-11 | 2014-02-12 | 中国电子科技集团公司第四十一研究所 | Triggering vibration real-time correction circuit and method in random sampling process |
-
2014
- 2014-07-07 CN CN201410320950.2A patent/CN104133095A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630299A (en) * | 2009-05-27 | 2010-01-20 | 东南大学 | Analysis and trigger method of I2C serial bus signal |
| CN101571555A (en) * | 2009-06-10 | 2009-11-04 | 东南大学 | Triggering method for serial peripheral interface bus signal |
| EP2533022A1 (en) * | 2011-06-10 | 2012-12-12 | Hexagon Technology Center GmbH | Extremely precise synchronised measuring value recording |
| CN103580656A (en) * | 2013-10-11 | 2014-02-12 | 中国电子科技集团公司第四十一研究所 | Triggering vibration real-time correction circuit and method in random sampling process |
Non-Patent Citations (2)
| Title |
|---|
| 戚瑞民: "数字存储示波器的设计研究", 《中国优秀硕士学位论文全文数据库》 * |
| 杨万渝: "混合信号分析仪串行总线协议触发与分析模看设计", 《中国优秀硕士学位论文全文数据库》 * |
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Application publication date: 20141105 |