CN104111870A

CN104111870A - Interrupt processing device and method

Info

Publication number: CN104111870A
Application number: CN201410323056.0A
Authority: CN
Inventors: 章建钦
Original assignee: Fujian Star Net Communication Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2014-07-08
Filing date: 2014-07-08
Publication date: 2014-10-22
Anticipated expiration: 2034-07-08
Also published as: CN104111870B

Abstract

The embodiment of the invention provides an interrupt processing device and method. The interrupt processing device and method are applied to the technical field of interrupt control, can save hardware resources, and can reduce hardware cost. The interrupt processing device comprises a block random access memory, an interrupt flag bit write-in module, an interrupt flag bit output module, an interrupt flag bit read-out module and an interrupt flag bit removal module, wherein the block random access memory at least comprises m memory cell groups; the interrupt flag bit write-in module is used for writing interrupt flag bit information of any function module in the memory cell group corresponding to the function module; the interrupt flag bit output module is used for generating an interrupt event processing request and sending the interrupt event processing request to a processor; the interrupt flag bit read-out module is used for obtaining the interrupt flag bit information of the memory cell group corresponding to the function module and sending the interrupt flag bit information to the processor; the interrupt flag bit removal module is used for removing effective information corresponding to an interrupt source. The interrupt processing device is used for processing an interrupt event.

Description

A kind of interrupt processing device and interruption processing method

Technical field

The present invention relates to interrupt control technique field, relate in particular to a kind of interrupt processing device and interruption processing method.

Background technology

In control system, processor is usually responded and is needed the anomalous event of processor emergency treatment to process request by interruption, and described interruption is that finger processor temporarily stops the program of current execution then carries out program and the implementation of processing new situation.

In a control system, conventionally there are a plurality of functional modules, each functional module comprises a plurality of interrupt source, each interrupt source has an interrupt flag bit corresponding with it, at present, the interrupt flag bit of interrupt source is normally stored by interrupt flag register, the corresponding interrupt flag register of functional module normally, example, when control system comprises m functional module, when each functional module comprises n interrupt source, this control system comprises m interrupt flag register, each interrupt flag register comprises n single-bit register, described in each, single-bit register is used for storing the interrupt flag bit of corresponding interrupt source.

When certain interrupt source needs processor to interrupt the anomalous event of processing, first need interrupt flag bit corresponding to set, make interrupt source generation anomalous event described in described interrupt identification bit-identify, then interrupt flag register can converge the information of interrupt flag bit, and notification processor interrupts processing.Processor receives after the notice of interrupting processing, first inquire about this interruption processing notice and come from which interrupt flag register, after getting corresponding interrupt flag register, by reading this interrupt flag register judgement, be which interrupt source need to interrupt processing, and then call corresponding Interrupt Subroutine and process, after finishing dealing with, this interrupt flag bit is removed.

But in prior art, if the functional module in control system is more, the interruption that needs a plurality of interrupt flag registers just can complete whole control system is processed, each interrupt flag register needs a set module and a dump block etc., when the functional module in control system is more, many cover interrupt control circuits need to be set and just can complete the processing to the interrupt event of each functional module, every cover interrupt control circuit all needs to take certain hardware resource, and processor is when a plurality of interrupt flag register of access, also need to use MUX, the number of interrupt flag register is larger, the hardware resource that MUX takies is more.When therefore the functional module in control system is more, the tricks of the interrupt control circuit needing is more, the hardware resource that interrupt control circuit is taken is more, MUX has also taken more hardware resource simultaneously, and then it is more to make whole interruption process the hardware resource taking, and has increased hardware cost.

Summary of the invention

Embodiments of the invention provide a kind of interrupt processing device and interruption processing method, can save hardware resource, reduce hardware cost.

For achieving the above object, embodiments of the invention adopt following technical scheme:

On the one hand, provide a kind of interrupt processing device, for the interrupt source of m functional module is processed, m is more than or equal to 2, and described functional module comprises at least one interrupt source; Described interrupt processing device comprises:

Piece random access memory, at least comprises m storage unit group, and each storage unit group is for storing the interrupt flag bit information of a functional module, and described interrupt flag bit information comprises the interrupt flag bit of all interrupt sources that described functional module comprises;

Interrupt flag bit writing module, for by the interrupt flag bit information of functional module described in any one, writes in storage unit group corresponding to described functional module;

Interrupt flag bit output module, for write the interrupt flag bit information of described storage unit group according to described interrupt flag bit writing module, generate interrupt event and process request, and described interrupt event is processed to request and send to processor, so that described processor is processed request according to described interrupt event, obtain the sign of functional module corresponding to described interrupt event request, according to the sign of described functional module, generate interrupt event processing instruction, described interrupt event processing instruction comprises the sign of described functional module;

Interrupt flag bit is read module, the described interrupt event processing instruction sending for receiving described processor, the sign of the functional module comprising according to described interrupt event processing instruction, obtain the interrupt flag bit information of storage unit group storage corresponding to described functional module, and described interrupt flag bit information is sent to processor; So that described processor determines that from described interrupt flag bit information described functional module exists the interrupt source of interrupt event, and processes the interrupt event of described interrupt source, after finishing dealing with, generate interrupt flag bit zero clearing indication;

Interrupt identification bit clear module, the described interrupt identification bit clear indication information sending for receiving described processor, described interrupt identification bit clear indication comprises the sign of interrupt source, according to the sign of described interrupt source, removes effective information corresponding to described interrupt source.

Optionally, described random access memory comprises first interface and the second interface, and described first interface is for writing the interrupt flag bit information of any one functional module, and described the second interface is for reading the interrupt flag bit information of any one functional module.

Optionally, described interrupt flag bit writing module comprises the first write data unit, and the first write address unit and first is write and enabled unit;

Described the first write address unit is for according to the sign of any one interrupt source, obtains the memory address of storage unit group corresponding to the functional module at described interrupt source place;

Described the first write data unit is for obtaining the interrupt flag bit information of described functional module;

Described first writes and enables unit and write enable command for generating first, described first writes enable command is used to indicate described random access memory according to the memory address of storage unit group corresponding to described functional module, and the interrupt flag bit information of described functional module is written in storage unit group corresponding to described functional module.

Optionally, described interrupt flag bit output module comprises the first detecting unit, generation unit and transmitting element;

Whether the interrupt flag bit information of the described functional module that described the first detecting unit writes for detection of described first interface indicates described functional module to have interrupt event;

When described generation unit indicates described functional module to have interrupt event for described interrupt flag bit information being detected when described the first detecting unit, generate interrupt event and process request;

Described transmitting element sends to processor for described interrupt event is processed to request, so that described processor is processed request according to described interrupt event, obtains the sign of functional module corresponding to described interrupt event request.

Optionally, described random access memory also comprises m mask bit storage sets, the corresponding functional module of mask bit storage sets described in each, described shielding storage sets is for storing the mask bit information of corresponding functional module, described mask bit information comprises the mask bit of all interrupt sources that described functional module comprises, when the described mask bit of any one interrupt source is effective in described functional module, represent that the interrupt event of described interrupt source does not deal with;

Described the first detecting unit is also for when described interrupt flag bit information being detected and indicate described functional module to have interrupt event, and whether the mask bit that detects the interrupt source that described interrupt event is corresponding is effective;

Described generation unit is specifically for indicating described functional module to have interrupt event when described interrupt flag bit information, and the mask bit of interrupt source corresponding to described interrupt event is when invalid, generates interrupt event and processes request.

Optionally, described interrupt flag bit is read module and is comprised: read address location and reading data unit;

The described address location of reading, for according to the sign of described functional module, obtains the memory address of storage unit group corresponding to described functional module;

Described reading data unit, for according to described memory address, obtains the interrupt flag bit information of the described functional module of storing in described memory address.

Optionally, described interrupt identification bit clear module comprises that the second write data unit, the second write address unit and second write and enable unit;

Described the second write address unit is for the sign of the described interrupt source that indication comprises according to described interrupt identification bit clear, obtains the memory address of storage unit group corresponding to the functional module at described interrupt source place;

Described the second write data unit is for according to the indication of described interrupt identification bit clear, obtains the new interrupt flag bit information of the interrupt source that described functional module comprises;

Described second writes and enables unit, for second, write enable command, described second writes enable command is used to indicate described random access memory according to the memory address of storage unit group corresponding to described functional module, and the new interrupt flag bit information of the interrupt source that described functional module is comprised is stored in storage unit group corresponding to described functional module.

Optionally, described interrupt identification bit clear module also comprises the second detecting unit;

Whether the memory address of the storage unit group that described functional module that the memory address of the storage unit group that the functional module at the described interrupt source place that described the second detecting unit obtains for detection of current described the second write address unit is corresponding is obtained with current described the first write address unit is corresponding is consistent;

When if the memory address that the memory address that current described the second write address unit obtains is obtained with described the first write address unit is consistent, the sign of the described interrupt source that described interrupt identification bit clear module comprises described interrupt identification bit clear indication sends to described interrupt flag bit writing module, so that described interrupt flag bit writing module obtains the interrupt flag bit information of described functional module according to the sign of described interrupt source.

On the one hand, provide a kind of interruption processing method, be applied to interrupt processing device, for the interrupt source of m functional module is processed, m is more than or equal to 2, and described functional module comprises at least one interrupt source; Described interruption processing method comprises:

Receive the interrupting information that the first interrupt source that the first functional module comprises sends, described interrupting information comprises the sign of described the first interrupt source;

According to the sign of described the first interrupt source, obtain the first interrupt flag bit information of the interrupt source that described the first functional module comprises, information corresponding to the first interrupt source described in described the first interrupt flag bit information represents to interrupt effectively;

In storage unit group corresponding to the first functional module described in piece random access memory, write described the first interrupt flag bit information, wherein, described random access memory at least comprises m storage unit group, and each storage unit group is for storing the first interrupt flag bit information of the interrupt source that a functional module comprises;

When described the first interrupt flag bit information in writing described random access memory indicates described the first functional module to have interrupt event, generate interrupt event and process request;

Described interrupt event is processed to request and send to processor, so that described processor is processed the sign of the first functional module corresponding to request according to interrupt event described in described interrupt event processing acquisition request, according to the sign of described the first functional module, generate interrupt event processing instruction, described interrupt event processing instruction comprises the sign of described the first functional module;

Receive the described interrupt event processing instruction that described processor sends;

The sign of described the first functional module comprising according to described interrupt event processing instruction, obtains the first interrupt flag bit information of storage unit group storage corresponding to described the first functional module;

Described the first interrupt flag bit information is sent to described processor, so that described processing is according to described the first interrupt flag bit information, determine that described the first functional module exists described first interrupt source of interrupt event, and process the described interrupt event of described the first interrupt source, after finishing dealing with, generate interrupt flag bit zero clearing indication;

Receive the described interrupt identification bit clear indication information that described processor sends, described interrupt identification bit clear indication information comprises the sign of described the first interrupt source;

According to described interrupt identification bit clear indication information, remove the effective information of interruption corresponding to the first interrupt source in the described first interrupt flag bit information of described random access memory storage.

Optionally, described according to the sign of described the first interrupt source, the first interrupt flag bit information of obtaining the interrupt source that described the first functional module comprises comprises:

According to the sign of described the first interrupt source, obtain the memory address of described the first functional module corresponding storage unit group in described random access memory;

According to described memory address, obtain the second interrupt flag bit information of current storage in storage unit group corresponding to described the first functional module;

According to the sign of described the second interrupt flag bit information and described the first interrupt source, obtain described the first interrupt flag bit information.

Optionally, describedly in storage unit group corresponding to the first functional module described in piece random access memory, write described the first interrupt flag bit information and comprise:

According to the memory address of storage unit group corresponding to described the first functional module, in storage unit group corresponding to the first functional module described in piece random access memory, write described the first interrupt flag bit information.

Optionally, the sign of described described the first functional module comprising according to described interrupt event processing instruction, the first interrupt flag bit information of obtaining storage unit group storage corresponding to described the first functional module comprises:

According to the sign of described the first functional module, obtain the memory address of described the first functional module corresponding storage unit group in described random access memory;

According to described memory address, obtain the first interrupt flag bit information of current storage in storage unit group corresponding to described the first functional module.

Optionally, described according to described interrupt identification bit clear indication information, the effective information of interruption corresponding to the first interrupt source in the described first interrupt flag bit information of described random access memory storage of removing comprises:

According to described memory address, obtain the first interrupt flag bit information of current storage in storage unit group corresponding to described the first functional module;

According to the sign of described the first interrupt flag bit information and described the first interrupt source, obtain the 3rd interrupt flag bit information, it is invalid that information corresponding to the first interrupt source described in described the 3rd interrupt flag bit information represents to interrupt;

According to described memory address, described the 3rd interrupt flag bit information is write to storage unit group corresponding to described the first functional module in described random access memory.

The interrupt processing device that the embodiment of the present invention provides and interruption processing method, if control system comprises at least two functional modules, while there is interrupt event in the interrupt source of the functional module comprising in control system, by the interrupt flag bit information of the interrupt source of each functional module in piece random access memory storage control system, then by interrupt flag bit writing module, complete the operation of the interrupt flag bit information write-in block random access memory of any one functional module, by interrupt flag bit, read the operation that module completes the interrupt flag bit information that reads any one functional module from piece random access memory, by interrupt identification bit clear module, complete the clear operation of the interrupt flag bit information of any one functional module, make described interrupt processing device can complete by a set of interrupt control circuit the processing of all interrupt events in control system, compared to prior art, this interrupt processing device does not need, for each functional module, the storage that corresponding interrupt flag register completes interrupt flag bit is set, and then do not need, for each interrupt flag register, independent interrupt control circuit is set, and in the process of underway disconnected processing, do not need MUX, thereby saved hardware resource, reduced hardware cost.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

The structural representation of a kind of interrupt processing device that Fig. 1 provides for the embodiment of the present invention;

The structural representation of a kind of random access memory that Fig. 2 provides for the embodiment of the present invention;

The structural representation of a kind of interrupt flag bit writing module that Fig. 3 provides for the embodiment of the present invention;

The structural representation of a kind of interrupt flag bit output module that Fig. 4 provides for the embodiment of the present invention;

The structural representation of the another kind of piece random access memory that Fig. 5 provides for the embodiment of the present invention;

Fig. 6 reads the structural representation of module for a kind of interrupt flag bit that the embodiment of the present invention provides;

The structural representation of a kind of interrupt identification bit clear module that Fig. 7 provides for the embodiment of the present invention;

The structural representation of the another kind of interrupt identification bit clear module that Fig. 8 provides for the embodiment of the present invention;

The process flow diagram of a kind of interruption processing method that Fig. 9 provides for the embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.

The embodiment of the present invention provides a kind of interrupt processing device 10, and for the interrupt source of m functional module is processed, m is more than or equal to 2, and described functional module comprises at least one interrupt source, and as shown in Figure 1, described interrupt processing device 10 comprises:

Piece random access memory (Block Random Access Memory, Block RAM) 101, at least comprise m storage unit group, each storage unit group is for storing the interrupt flag bit information of a functional module, and described interrupt flag bit information comprises the interrupt flag bit of all interrupt sources that described functional module comprises.

During by interrupt flag bit register-stored interrupt flag bit, an interrupt identification bit register can only be stored the interrupt flag bit of a functional module or an interrupt source, each interrupt identification bit register needs a set of control circuit to complete the writing, read or remove of interrupt flag bit information, and takies hardware resource more.During by piece random access memory 101 storage interrupt flag bit, the interrupt flag bit information of all interrupt sources that in control system, each functional module comprises can be stored in a piece random access memory, therefore only need a set of control circuit can complete writing, reading or removing the interrupt flag bit information of a plurality of functional modules.

In actual applications, the bit wide of described random access memory 101 and the degree of depth all can arrange according to actual needs, example, in the embodiment of the present invention, control system comprises m functional module, suppose that each functional module comprises at most n interrupt source, this control system comprises m * n interrupt source altogether, the degree of depth of the piece random access memory 101 that this control system needs can be m, bit wide can be n, this piece random access memory 101 comprises m * n bit, a bit is used for storing the interrupt flag bit of an interrupt source, the degree of depth be the bit wide of i from the 0 all bits to (n-1) as a storage unit group, described i is for being more than or equal to 0, be less than the integer of m, this piece random access memory 101 comprises m storage unit group.

During practical application, can model functional module and storage unit group between corresponding relation, make each functional module have the storage unit group corresponding with it, for example, the first functional module and the second functional module are any one functional module in described control system, the first functional module comprises n interrupt source, and the bit wide that degree of depth is 1 can be used as a storage unit group from 0 bit to (n-1), is used for storing the interrupt flag bit of all interrupt sources of the first functional module; The second functional module comprises j interrupt source, described j is less than n, the bit wide that degree of depth is 2 can be used as another storage unit group from 0 bit to (n-1), be used for storing the interrupt flag bit of all interrupt sources of the second functional module, but can predetermine the degree of depth and be 2 bit wide and from 0 bit to (j-1), be used for storing the interrupt flag bit of all interrupt sources of the second functional module, remaining (n-j) individual bit can be idle, can process for other, the embodiment of the present invention does not limit this yet.

Example, suppose that in the embodiment of the present invention, control system comprises 4 functional modules, be respectively the first functional module, the second functional module, the 3rd functional module, the 4th functional module, wherein the first functional module comprises three interrupt sources, is respectively the first interrupt source, the second interrupt source, the 3rd interrupt source; The second functional module comprises two interrupt sources, is respectively the 4th interrupt source, the 5th interrupt source; The 3rd functional module comprises three interrupt sources, is respectively the 6th interrupt source, the 7th interrupt source, the 8th interrupt source; The 4th functional module comprises four interrupt sources, is respectively the 9th interrupt source, the tenth interrupt source, the 11 interrupt source and the 12 interrupt source.It is 4 that piece random access memory can arrange the degree of depth, bit wide is also 4, comprise altogether 16 bits, the degree of depth is that the bit of 1 bit wide from 0 to 3 is as the first storage unit group, for storing the interrupt identification information of the first functional module, wherein the bit of bit wide from 0 to 2 is respectively used to store the interrupt flag bit of the first interrupt source, the second interrupt source and the 3rd interrupt source, and the bit that bit wide is 3 is idle; The degree of depth is that the bit of 2 bit wide from 0 to 3 is as the second storage unit group, for storing the interrupt identification information of the second functional module, wherein the bit of bit wide from 0 to 1 is respectively used to store the interrupt flag bit of the 4th interrupt source, the 5th interrupt source, and bit wide is 2 and 3 bit free time; The degree of depth is that the bit of 3 bit wide from 0 to 3 is as the 3rd storage unit group, for storing the interrupt identification information of the 3rd functional module, wherein the bit of bit wide from 0 to 2 is respectively used to store the interrupt flag bit of the 6th interrupt source, the 7th interrupt source, the 8th interrupt source, and the bit that bit wide is 3 is idle; The degree of depth is that the bit of 4 bit wide from 0 to 3 is as the 4th storage unit group, for storing the interrupt identification information of the 4th functional module, wherein the bit of bit wide from 0 to 3 is respectively used to store the interrupt flag bit of the 9th interrupt source, the tenth interrupt source, the 11 interrupt source and the 12 interrupt source.

Interrupt flag bit writing module 102, for by the interrupt flag bit information of functional module described in any one, writes in storage unit group corresponding to described functional module.

Example, can be according to the sign of any one interrupt source, obtain the memory address of storage unit group corresponding to the functional module at this interrupt source place, according to this memory address, obtain storage unit group corresponding to this functional module interrupt flag bit information of storage now, then described in the interrupt flag bit information of storage, interrupt flag bit corresponding to interrupt source is set to effectively now, obtain the current interrupt flag bit information of this functional module, then according to the memory address of storage unit group corresponding to this functional module, the current interrupt flag bit information of this functional module is write in storage unit group corresponding to this functional module.

Interrupt flag bit output module 103, for write the interrupt flag bit information of described storage unit group according to described interrupt flag bit writing module 102, generate interrupt event and process request, and described interrupt event is processed to request and send to processor, so that described processor is processed request according to described interrupt event, obtain the sign of functional module corresponding to described interrupt event request, according to the sign of described functional module, generate interrupt event processing instruction, described interrupt event processing instruction comprises the sign of described functional module.

Optionally, interrupt flag bit output module 103 can be when interrupt flag bit writing module 102 writing described interrupt flag bit information, obtain this interrupt flag bit information, whether then judge in this interrupt flag bit information has interrupt identification bit representation to interrupt effectively, in this interrupt flag bit information, there is interrupt identification bit representation to interrupt when effective, generate interrupt event and process request.Or after interrupt flag bit writing module 102 is by interrupt flag bit information write-in block random access memory 101, interrupt flag bit output module 103 obtains interrupt flag bit information from described random access memory 101 canned datas, whether then judge in this interrupt flag bit information has interrupt identification bit representation to interrupt effectively, in this interrupt flag bit information, there is interrupt identification bit representation to interrupt when effective, generate interrupt event and process request.Concrete, the process that interrupt flag bit output module 103 obtains interrupt flag bit information can arrange as the case may be, and the embodiment of the present invention does not limit this.

Optionally, in interrupt flag bit output module 103, can also comprise a functional module interrupt register, described functional module interrupt register comprises that m is deposited position, each deposits a corresponding functional module, when detecting, interrupt flag bit output module 103 in obtained interrupt flag bit information, has interrupt identification bit representation to interrupt when effective, suppose that functional module corresponding to this interrupt flag bit information is the first functional module, interrupt flag bit output module 103 can functional module interrupt register in the position of depositing corresponding to the first functional module be set to effectively, when processor is processed request according to interrupt event, while judging the interrupt event that current existence need to process, can be by reading the information of preserving in described functional module interrupt register, obtain the sign of functional module corresponding to described interrupt event request, according to the sign of described functional module, generate interrupt event processing instruction, described interrupt event processing instruction comprises the sign of described functional module.

Or, described interrupt event is processed request and is comprised the sign of described interrupt source or the sign of functional module, after processor receives described interrupt event processing request, can obtain by the sign of described interrupt source the sign of described functional module, or directly obtain the sign of described functional module.

Interrupt flag bit is read module 104, the described interrupt event processing instruction sending for receiving described processor, the sign of the functional module comprising according to described interrupt event processing instruction, obtain the interrupt flag bit information of storage unit group storage corresponding to described functional module, and described interrupt flag bit information is sent to processor; So that described processor exists the interrupt source of interrupt event in definite described functional module from described interrupt flag bit information, and processes the interrupt event of described interrupt source, after finishing dealing with, generate interrupt flag bit zero clearing indication.

Example, the sign of the functional module comprising according to interrupt event processing instruction, obtain the memory address of this functional module corresponding stored unit group, then according to this memory address, obtain the interrupt flag bit information of this functional module corresponding stored unit group storage in piece random access memory 101, then this interrupt flag bit information is sent to processor, so that processor judges in this interrupt flag bit information that interrupt identification bit representation corresponding to which interrupt source is specifically effective, then process the interrupt event of this interrupt source.

Interrupt identification bit clear module 105, the described interrupt identification bit clear indication information sending for receiving described processor, described interrupt identification bit clear indication comprises the sign of interrupt source, according to the sign of described interrupt source, removes effective information corresponding to described interrupt source.

After processor is finished dealing with the interrupt event of interrupt source, can send interrupt identification bit clear indication information to interrupt identification bit clear module 105, after interrupt identification bit clear module 105 receives this interrupt identification bit clear indication information, the sign of the interrupt source first comprising according to this interrupt identification bit clear indication information, obtain the present interrupt flag bit information of storing of storage unit group corresponding to functional module at this interrupt source place, then according to the sign of this interrupt source, in the interrupt flag bit information of described present storage interrupt flag bit corresponding to this interrupt source be set to invalid, obtain new interrupt flag bit information, then described new interrupt flag bit information is write in storage unit group corresponding to described functional module.

So, if control system comprises at least two functional modules, while there is interrupt event in the interrupt source of the functional module comprising in control system, by the interrupt flag bit information of the interrupt source of each functional module in piece random access memory storage control system, then by interrupt flag bit writing module, complete the operation of the interrupt flag bit information write-in block random access memory of any one functional module, by interrupt flag bit, read the operation that module completes the interrupt flag bit information that reads any one functional module from piece random access memory, by interrupt identification bit clear module, complete the clear operation of the interrupt flag bit information of any one functional module, make described interrupt processing device can complete by a set of interrupt control circuit the processing of all interrupt events in control system, compared to prior art, this interrupt processing device does not need, for each functional module, the storage that corresponding interrupt flag register completes interrupt flag bit is set, and then do not need, for each interrupt flag register, independent interrupt control circuit is set, and in the process of underway disconnected processing, do not need MUX, thereby saved hardware resource, reduced hardware cost.

It should be noted that, described interrupt processing device can be applied to FPGA (Field-Programmable Gate Array, field programmable gate array) etc. comprise in the chip of piece random access memory, also can be at IC (integrated circuit, integrated circuit) in circuit, add piece random access memory that the interrupt processing device that the embodiment of the present invention provides is set, complete the processing of the interrupt event of IC circuit.

Example, as described in Figure 2, described random access memory 101 comprises first interface 1011 and the second interface 1012, described first interface 1011 is for writing the interrupt flag bit information of any one functional module, and described the second interface 1012 is for reading or write the interrupt flag bit information of any one functional module.Described first interface 1011 comprises the first input data line 1011a, the first output data line 1011b, the first address wire 1011c and first writes enable line 1011d, described the second interface 1012 comprises the second input data line 1012a, the second output data line 1012b, the second address wire 1012c and second writes enable line 1012d.

Concrete, write enable line 1011d and receive while writing enable command when first, the data that the first interface 1011 of piece random access memory 101 can receive the first input data line 1011a are stored in the address that the first address wire 1011c receives, or the address that can receive according to the first address wire 1011c, sends canned data in this address by the first output data line 1011b.Same, write enable line 1012d and receive while writing enable command when second, the data that the second interface 1012 of piece random access memory 101 can receive the second input data line 1021a are stored in the address that the second address wire 1012c receives, or the address that can receive according to the second address wire 1012c, sends canned data in this address by the second output data line 1012b.

Further, as shown in Figure 3, described interrupt flag bit writing module 102 comprises that the first write data unit 1021, the first write address unit 1022 and first are write and enables unit 1023.

Wherein, described the first write address unit 1022 is for according to the sign of any one interrupt source, obtains the memory address of storage unit group corresponding to the functional module at described interrupt source place.

Optionally, can be in described the first write address unit 1022 during initialization hold function module table corresponding to memory address in advance, due to the corresponding storage unit group of each functional module, there is a unique memory address in each storage unit group, therefore an also corresponding memory address of each functional module, described functional module with the corresponding table record of memory address the corresponding relation of each functional module and memory address.After interrupt flag bit writing module 102 receives the interrupting information that the some interrupt source of some functional modules sends, described interrupting information comprises the sign of described interrupt source, the first write address unit 1022 can be according to the sign of described interrupt source and described functional module table corresponding to memory address, obtains the memory address of storage unit group corresponding to the functional module at described interrupt source place.

Described the first write data unit 1021 is for obtaining the interrupt flag bit information of described functional module.

Example, after the first write address unit 1022 gets the memory address of storage unit group corresponding to the functional module at described interrupt source place, the first write data unit 1021 can be according to described memory address, obtain the interrupt flag bit information of the present storage of storage unit group storage corresponding to the functional module at described interrupt source place, then the first write data unit 1021 is according to the sign of described interrupt source, described in the interrupt flag bit information of described present storage, interrupt flag bit corresponding to interrupt source is set to effectively, obtain the current interrupt flag bit information of described functional module.

Concrete, the first write address unit 1022 can by described memory address, the first interface 1011 by piece random access memory 101 comprises the first address wire 1011c send to piece random access memory 101, the first output data line 1011b that then piece random access memory 101 can comprise by first interface 1011 by described memory address now the interrupt flag bit information of storage send to described the first write data unit 1021.

Described first writes and enables unit 1023 and write enable command for generating first, described first writes enable command is used to indicate described random access memory 101 according to the memory address of storage unit group corresponding to described functional module, and the interrupt flag bit information of described functional module is written in storage unit group corresponding to described functional module.

Optionally, first writes and enables first of the first interface 1011 of unit 1023 by piece random access memory 101 and write enable line 1011d and send described first and write enable command, and the address that then piece random access memory 101 receives according to the first address wire 1011c of first interface 1011 is stored in the current interrupt flag bit information of described functional module receiving on the first input data line 1011a of first interface 1011 in storage unit corresponding to described functional module.

Further, as shown in Figure 4, described interrupt flag bit output module 103 comprises the first detecting unit 1031, generation unit 1032 and transmitting element 1033.

Whether the interrupt flag bit information of the described functional module that wherein, described the first detecting unit 1031 writes for detection of described first interface 1011 indicates described functional module to have interrupt event.

Optionally, after getting the interrupt flag bit information of the current described functional module writing of described first interface 1011, described the first detecting unit 1031 can detect described interrupt flag bit information and whether have effective interrupt flag bit, if described interrupt flag bit information exists effective interrupt flag bit, there is interrupt event in functional module corresponding to described interrupt flag bit information.

Concrete, suppose that interrupt flag bit represents that for " 1 " interrupt flag bit is effective, interrupt flag bit is that " 0 " sign interrupt flag bit is invalid, the first detecting unit 1031 can detect described interrupt flag bit information and whether have not the interrupt flag bit for " 0 ", when described interrupt flag bit information existence is not the interrupt flag bit of " 0 ", illustrate that functional module corresponding to described interrupt flag bit information exists interrupt event.

Optionally, described the first detecting unit 1031 can comprise a plurality of output ports, described output port is connected with described functional module interrupt register, corresponding one of each output port is deposited position, when the interrupt flag bit information existence of functional module is not the interrupt flag bit of " 0 ", be that described functional module is while existing interrupt event, the position of depositing that described functional module is corresponding is set to " 1 ", when the interrupt flag bit information of functional module does not exist for the interrupt flag bit of " 1 ", be that described functional module is not while existing interrupt event, the position of depositing that described functional module is corresponding is set to " 0 ".

When described generation unit 1032 indicates described functional module to have interrupt event for described interrupt flag bit information being detected when described the first detecting unit 1031, generate interrupt event and process request.

Optionally, when described interrupt flag bit output module 103 can be worked as described interrupt flag bit information and indicated described functional module to have interrupt event, generate interrupt event and process request, or the information that described interrupt flag bit output module 103 can be preserved in detecting described functional module interrupt register, in functional module interrupt register, any one functional module deposits position effectively, be any one functional module while there is interrupt event, generate interrupt event and process request.

Described transmitting element 1033 sends to processor for described interrupt event is processed to request, so that described processor is processed request according to described interrupt event, obtains the sign of functional module corresponding to described interrupt event request.

Optionally, transmitting element 1033 can, by the line between interrupt flag bit output module 103 and processor, be processed request by described interrupt event and send to processor.

Further, described random access memory 101 can also comprise m mask bit storage sets, the corresponding functional module of mask bit storage sets described in each, described shielding storage sets is for storing the mask bit information of corresponding functional module, described mask bit information comprises the mask bit of all interrupt sources that described functional module comprises, when the described mask bit of any one interrupt source is effective in described functional module, represent that the interrupt event of described interrupt source does not deal with.

Optionally, as shown in Figure 5, the degree of depth of piece random access memory 101 can be m, bit wide can be 2n, described random access memory 101 comprises m * 2n bit, during initialization, the bit wide that the degree of depth can be set be i is the interrupt flag bit information as a functional module of a storage unit group storage from 0 bit to (n-1), from i0 to i, the bit of (n-1) can be used as the interrupt flag bit information that a storage unit group is stored a functional module, the bit of bit wide from n to (2n-1) stored the mask bit information of described functional module as a mask bit storage sets, from in to i, the bit of (2n-1) can be used as the mask bit information that a mask bit storage sets is stored described functional module, described mask bit information comprises the mask bit of all interrupt sources that described functional module comprises.Shown in figure 5, in Fig. 5, region 501 is a storage unit group, and the mask bit storage sets corresponding to corresponding functional module of 502Wei region, region 501 indications, stores the mask bit of n interrupt source at the most in described mask bit storage sets.

Whether effective described the first detecting unit 1031 also, for when described interrupt flag bit information being detected and indicate described functional module to have interrupt event, detect the mask bit that described interrupt event is corresponding.

Example, the first detecting unit 1031 can detect interrupt flag bit information and indicate the interrupt source that specifically has interrupt event in corresponding functional module, can also judge that whether mask bit corresponding to described interrupt source be effective, optionally, when mask bit corresponding to this interrupt source is " 1 ", represent that mask bit is effective, when mask bit corresponding to this interrupt source is " 0 ", represent that mask bit is invalid, when mask bit is effective, represent that processor can not deal with the interrupt event of this interrupt source.

Described generation unit 1032 is specifically for indicating described functional module to have interrupt event when described interrupt flag bit information, and the mask bit of interrupt source corresponding to described interrupt event is when invalid, generates interrupt event and processes request.

When detecting interrupt source, the first detecting unit 1031 there is interrupt event, and the mask bit of interrupt source corresponding to described interrupt event is when invalid, generation unit 1032 just can generate interrupt event and process request, when detecting interrupt source, the first detecting unit 1031 there is interrupt event, when but the mask bit of the interrupt source that described interrupt event is corresponding is effective, representing does not need to notify described interrupt event to processor, therefore if when other interrupt sources of functional module corresponding to this interrupt source do not have interrupt event, can not generate interrupt event and process request.

Need explanation, during initialization, in control system, mask bit corresponding to each interrupt source is all invalid, and in the operational process of control system, processor can arrange the mask bit of each interrupt source as the case may be.Example, if the interrupt event that processor is judged certain interrupt source according to actual conditions does not belong to emergency, do not need to process, can be set to effectively by mask bit corresponding to this interrupt source; If or the interrupt event that processor is judged this interrupt source according to actual conditions belongs to emergency, need to process, can mask bit corresponding to this interrupt source be set to invalid.

Further, as shown in Figure 6, described interrupt flag bit is read module 104 and is comprised: read address location 1041 and reading data unit 1042.

Wherein, described in read address location 1041 for according to the sign of described functional module, obtain the memory address of storage unit group corresponding to described functional module.

After processor receives interrupt event processing request, can process request according to interrupt event, the sign of obtaining the functional module that produces interrupt event, then generates interrupt event processing instruction, and described interrupt event processing instruction comprises the sign of described functional module.Then reading address location 1041 can be according to the sign of this functional module, obtain the memory address of storage unit group corresponding to this functional module, optionally, memory function module table corresponding to memory address in reading address location 1041 in advance, then read address location 1041 and can, according to the sign of functional module and functional module table corresponding to memory address, obtain the memory address of storage unit group corresponding to this functional module.

Described reading data unit 1042, for according to described memory address, obtains the interrupt flag bit information of the described functional module of storing in described memory address.

Example, reading data unit 1042 can send to piece random access memory 101 by the second address wire 1012c by the second interface 1012 of piece random access memory 101 by described memory address, after piece random access memory 101 receives this memory address, the second output data line 1012b that the interrupt flag bit information exchange of storage unit group corresponding to described memory address is crossed to the second interface 1012 sends to reading data unit 1042.

Further, as shown in Figure 7, described interrupt identification bit clear module 105 comprises that the second write data unit 1051, the second write address unit 1052 and second write and enable unit 1053.

Wherein, described the second write address unit 1052 is for the sign of the described interrupt source that indication comprises according to described interrupt identification bit clear, obtains the memory address of storage unit group corresponding to the functional module at described interrupt source place.

Optionally, can be in described the second write address unit 1052 during initialization hold function module table corresponding to memory address in advance, in the interrupt identification bit clear indication information that receives processor transmission, obtain the sign that described interrupt identification bit clear indication information comprises interrupt source, then according to the sign of described interrupt source and functional module table corresponding to memory address, obtain the memory address of storage unit group corresponding to the functional module at described interrupt source place.Concrete, first can obtain according to the sign of interrupt source the sign of functional module corresponding to described interrupt source, then according to the sign of described functional module and functional module table corresponding to memory address, obtain the memory address of storage unit group corresponding to the functional module at described interrupt source place.

Described the second write data unit 1051 is for according to the indication of described interrupt identification bit clear, obtains the new interrupt flag bit information of the interrupt source that described functional module comprises.

Optionally, after the second write address unit 1052 gets the memory address of storage unit group corresponding to described functional module, the second write data unit 1051 can be according to described memory address, obtain storage unit group corresponding to the described functional module interrupt flag bit information of storage now, then the second write data unit 1051 is according to the sign of described interrupt source, it is invalid that interrupt flag bit corresponding to interrupt source described in the interrupt flag bit information of described present storage is set to, obtain new interrupt flag bit information, for example, when the interrupt flag bit information of the present storage getting is " 10000 ", for " 1 ", represent that interrupt flag bit corresponding to described interrupt source is effective, the second write data unit 1051 can described interrupt flag bit information described in interrupt flag bit corresponding to interrupt source be set to " 0 ", obtain new interrupt flag bit information for " 00000 ".

Concrete, by described memory address, the second address wire 1012c by the second interface 1012 of piece random access memory 101 sends to piece random access memory 101 in the second write address unit 1052, the second output data line 1012b that then piece random access memory 101 can be by the second interface 1012 by storage unit group corresponding to described memory address now the interrupt flag bit information of storage send to the second write address unit 1052.

Described second writes and enables unit 1053, for second, write enable command, described second writes enable command is used to indicate described random access memory 101 according to the memory address of storage unit group corresponding to described functional module, and the new interrupt flag bit information of the interrupt source that described functional module is comprised is stored in storage unit group corresponding to described functional module.

Optionally, second writes and enables second of second interface 1012 of unit 1053 by piece random access memory 101 and write enable line 1012d and send described second and write enable command, then the address that piece random access memory 101 receives according to the second address wire 1012c of the second interface 1012, is stored in the new interrupt flag bit information of the described functional module receiving on the second input data line 1012a of the second interface 1012 in storage unit corresponding to described functional module.

Preferably, as shown in Figure 8, described interrupt identification bit clear module 105 also comprises the second detecting unit 1054.The memory address of the storage unit group that described functional module that the memory address of the storage unit group that the functional module at the described interrupt source place that described the second detecting unit 1054 obtains for detection of current described the second write address unit 1052 is corresponding is obtained with current described the first write address unit 1022 is corresponding.

Example, when the second write address unit 1052 carries out interrupt flag bit clear operation in interrupt identification bit clear module 105, the memory address of obtaining and current the first write address unit 1022 are when interrupt flag bit writing module 102 carries out interrupt flag bit write operation, the memory address of obtaining may be consistent, represent when functional module corresponding to this memory address carry out interrupt identification bit clear time, there is again interrupt event in the interrupt source of this functional module, need to carry out interrupt flag bit writes, at this moment interrupt flag bit writing module 102 has produced and has conflicted with the operation of interrupt identification bit clear module 105, cause operation cannot carry out or easily cause the loss of interrupt flag bit information.So interrupt identification bit clear module 105 can be before carrying out clear operation, whether the memory address of first obtaining by the second detecting unit 1054 current described the second write address unit 1052 of detection is consistent with the memory address that current described the first write address unit 1022 obtains.

When if the memory address that the memory address that current described the second write address unit 1052 obtains is obtained with described the first write address unit 1022 is consistent, the sign of the described interrupt source that described interrupt identification bit clear module 105 comprises described interrupt identification bit clear indication sends to described interrupt flag bit writing module 102, so that described interrupt flag bit writing module 102 obtains the interrupt flag bit information of described functional module according to the sign of described interrupt source.

Example, it is invalid that the indicated interrupt flag bit of sign of the interrupt source that the first write data unit 1021 interrupt identification bit clear modules 105 of interrupt flag bit writing module 102 send is set to, the interrupt source that described interrupting information comprises identifies indicated interrupt flag bit and is set to effectively, get the interrupt flag bit information of the functional module at described interrupt source place, then by first interface 1011, described interrupt flag bit information is stored in storage unit group corresponding to described functional module, completed writing and removing the interrupt flag bit information of this functional module simultaneously.If the interrupt source sign that the sign of the interrupt source that described interrupt identification bit clear module 105 sends comprises with described interrupting information is identical, interrupt flag bit is set to effectively operate and have right of priority.

The interrupt processing device that the embodiment of the present invention provides, if control system comprises at least two functional modules, while there is interrupt event in the interrupt source of the functional module comprising in control system, by the interrupt flag bit information of the interrupt source of each functional module in piece random access memory storage control system, then by interrupt flag bit writing module, complete the operation of the interrupt flag bit information write-in block random access memory of any one functional module, by interrupt flag bit, read the operation that module completes the interrupt flag bit information that reads any one functional module from piece random access memory, by interrupt identification bit clear module, complete the clear operation of the interrupt flag bit information of any one functional module, make described interrupt processing device can complete by a set of interrupt control circuit the processing of all interrupt events in control system, compared to prior art, this interrupt processing device does not need, for each functional module, the storage that corresponding interrupt flag register completes interrupt flag bit is set, and then do not need, for each interrupt flag register, independent interrupt control circuit is set, and in the process of underway disconnected processing, do not need MUX, thereby saved hardware resource, reduced hardware cost.

The embodiment of the present invention provides a kind of interruption processing method, is applied to interrupt processing device, and as shown in Figure 9, for the interrupt source of m functional module is processed, m is more than or equal to 2, and described functional module comprises at least one interrupt source; Described interruption processing method comprises:

The interrupting information that the first interrupt source that step 901, reception the first functional module comprise sends, described interrupting information comprises the sign of described the first interrupt source.

Described the first functional module is any one functional module in m functional module, suppose that described the first functional module comprises n interrupt source, the first interrupt source is any one in n interrupt source, the first interrupt source generation interrupt event when the first functional module, while needing processor to process, the first interrupt source generates interrupting information, and this interrupting information comprises the sign of the first interrupt source, and described interrupting information is sent to interrupt processing device.

Step 902, according to the sign of described the first interrupt source, obtain the first interrupt flag bit information of the interrupt source that described the first functional module comprises, information corresponding to the first interrupt source described in described the first interrupt flag bit information represents to interrupt effectively.

Example, interrupt processing device is after receiving the interrupting information of the first interrupt source transmission, first according to the sign of the first interrupt source, obtain the sign of first functional module at this first interrupt source place, then according to the sign of the first functional module, obtain the second interrupt flag bit information of current storage in storage unit group corresponding to the first functional module in piece random access memory, described the second interrupt flag bit information recording the first interrupt source while there is not interrupt event, the interrupt flag bit of each interrupt source in the first functional module.Then in the second interrupt flag bit information, interrupt flag bit corresponding to the first interrupt source is set to effectively, obtains the first interrupt flag bit information.

Step 903, in storage unit group corresponding to the first functional module described in piece random access memory, write described the first interrupt flag bit information, wherein, described random access memory at least comprises m storage unit group, and each storage unit group is for storing the first interrupt flag bit information of the interrupt source that a functional module comprises.

Example, the memory address corresponding according to the first functional module, by storage unit group corresponding to the first functional module described in the first interrupt flag bit information write-in block random access memory.

Concrete, suppose n=5, the first functional module comprises 5 interrupt sources, when the first interrupt source generation interrupt event, in the second interrupt flag bit information, interrupt flag bit corresponding to the first interrupt source is set to " 1 ", suppose that interrupt flag bit corresponding to the first interrupt source in the second interrupt flag bit information is first of the second interrupt flag bit information, the first interrupt flag bit information obtaining is " 10000 ".Interrupt processing device can be by storage unit group corresponding to the first functional module described in " 10000 " write-in block random access memory, and this storage unit group at least needs to comprise that 5 bits are for storing the interrupt flag bit information of 5 interrupt sources.

When step 904, described the first interrupt flag bit information in writing described random access memory indicate described the first functional module to have interrupt event, generate interrupt event and process request.

When interrupt processing device detects described the first interrupt flag bit information writing in described random access memory and comprises effective interrupt flag bit, described in this, the first interrupt flag bit information indicates described the first functional module to have interrupt event.Concrete, interrupt processing device detects described the first interrupt flag bit information writing in described random access memory and comprises while being not the interrupt flag bit of " 0 ", described in this, the first interrupt flag bit information indicates described the first functional module to have interrupt event, in the embodiment of the present invention, because interrupt event appears in the first interrupt source, therefore described the first interrupt flag bit information writing in described random access memory comprises not being the interrupt flag bit of " 0 ", indicate described the first functional module to have interrupt event, need to generate interrupt event and process request.

Step 905, described interrupt event is processed to request send to processor, so that described processor is processed the sign of the first functional module corresponding to request according to interrupt event described in described interrupt event processing acquisition request, according to the sign of described the first functional module, generate interrupt event processing instruction, described interrupt event processing instruction comprises the sign of described the first functional module.

Interrupt processing device can by and processor between line or communication protocol interface, interrupt event is processed to request and send to processor, after processor receives this interrupt event processing request, learnt that interrupt event needs to process, at this moment processor obtains the sign of the first functional module of interrupt event appearance, then according to the sign of described the first functional module, generate interrupt event processing instruction, described interrupt event processing instruction comprises the sign of described the first functional module.

Optionally, interrupt processing device can also comprise a functional module interrupt register, described functional module interrupt register comprises that m is deposited position, each deposits a corresponding functional module, when detecting in the first obtained interrupt flag bit information the first interrupt identification bit representation, interrupt processing device interrupts when effective, interrupt processing device can functional module interrupt register in the position of depositing corresponding to the first functional module be set to effectively, when processor is processed request according to interrupt event, while judging the interrupt event that current existence need to process, can be by reading the information of preserving in described functional module interrupt register, obtain the sign of the first functional module that current interrupt event is corresponding, according to the sign of described the first functional module, generate interrupt event processing instruction, described interrupt event processing instruction comprises the sign of described the first functional module.

Or described interrupt event is processed the sign that can also comprise the first functional module in request, processor is directly processed the sign of acquisition request the first functional module by interrupt event.

Step 906, receive the described interrupt event processing instruction that described processor sends.

The sign of step 907, described the first functional module of comprising according to described interrupt event processing instruction, obtains the first interrupt flag bit information of storage unit group storage corresponding to described the first functional module.

Interrupt processing device is after receiving the described interrupt event processing instruction of processor transmission, first obtain the sign of the first functional module that this interrupt event processing instruction comprises, then according to the sign of the first functional module, obtain the first interrupt flag bit information of storage unit group storage corresponding to described the first functional module, example, after getting the sign of the first functional module, the functional module that can preserve in advance with interrupt processing device according to the sign of the first functional module and the corresponding table of memory address, obtain the memory address of storage unit group corresponding to the first functional module, then according to this memory address, from piece random access memory, read the first interrupt flag bit information of storage unit group storage corresponding to the first functional module.

Step 908, described the first interrupt flag bit information is sent to described processor, so that described processing is according to described the first interrupt flag bit information, determine that described the first functional module exists described first interrupt source of interrupt event, and process the described interrupt event of described the first interrupt source, after finishing dealing with, generate interrupt flag bit zero clearing indication.

Interrupt processing device sends to processor by the first interrupt flag bit information, and whether processor can be effective according to each interrupt flag bit in the first interrupt flag bit information, determines the concrete interrupt source that produces interrupt event.Example, because the interrupt identification bit representation that the first interrupt source in the first interrupt flag bit information is corresponding is effective, processor can determine that what in the first functional module, have interrupt event is the first interrupt source, then can call the interrupt event that interrupt handling routine corresponding to the first interrupt source processed the first interrupt source.Concrete, the first interrupt flag bit information that interrupt processing device is read is " 10000 ", after this first interrupt flag bit information is sent to processor, processor judges that interrupt flag bit corresponding to the first interrupt source is for " 1 ", interrupt flag bit corresponding to other interrupt sources is " 0 ", determine in the first functional module and only have the first interrupt source to have interrupt event, then processor can call the interrupt event that interrupt handling routine corresponding to the first interrupt source processed the first interrupt source.

Step 909, receive the described interrupt identification bit clear indication information that described processor sends, described interrupt identification bit clear indication information comprises the sign of described the first interrupt source.

After processor is processed the interrupt event of the first interrupt source, an or interrupt identification bit clear indication information of generation, described in this, interrupt identification bit clear indication information comprises the sign of described the first interrupt source, the interrupt event that is used to indicate the first interrupt source is finished dealing with, need to remove interrupt flag bit corresponding to the first interrupt source, in order to avoid interrupt processing device still judges, have interrupt event.

Step 9010, according to described interrupt identification bit clear indication information, remove the effective information of interruption corresponding to the first interrupt source in the described first interrupt flag bit information of described random access memory storage.

After receiving the described interrupt identification bit clear indication information of described processor transmission, first obtain the sign of the first interrupt source, then according to the sign of the first interrupt source, obtain the sign of the first functional module, then according to the sign of the first functional module, obtain the first interrupt flag bit information of storing in storage unit group corresponding to the first functional module, then in this first interrupt flag bit information interrupt flag bit corresponding to the first interrupt source be set to invalid, obtain the 3rd interrupt flag bit information, then by storage unit group corresponding to the 3rd interrupt flag bit information write-in block random access memory the first functional module.

So, the interruption processing method that the embodiment of the present invention provides, if control system comprises at least two functional modules, when the interruption of control system is processed, by piece random access memory, complete the interrupt flag bit of the interrupt source of a plurality of functional modules is stored, then on the basis of piece random access memory, complete writing the interrupt flag bit of the interrupt source of all functions module, read and remove, based on writing of piece random access memory, read and remove, only need a set of interrupt control circuit to realize, compared to prior art, interruption processing method of the present invention do not need for each functional module setting with it corresponding interrupt identification bit register complete the storage of the interrupt flag bit of this functional module, and then need to many cover interrupt control circuits be set for each interrupt identification bit register and realize and writing, read and remove, and avoided use MUX, therefore, interruption processing method provided by the invention, can save hardware resource, and then reduce hardware cost.

Optionally, according to the sign of described the first interrupt source, while obtaining the first interrupt flag bit information of the interrupt source that described the first functional module comprises, can be first according to the sign of described the first interrupt source, obtain the memory address of described the first functional module corresponding storage unit group in described random access memory, then according to described memory address, obtain the second interrupt flag bit information of current storage in storage unit group corresponding to described the first functional module, and then can be according to the sign of described the second interrupt flag bit information and described the first interrupt source, obtain described the first interrupt flag bit information.

Optionally, can be in this interrupt processing device during initialization hold function module table corresponding to memory address in advance, due to the corresponding storage unit group of each functional module, there is a unique memory address in each storage unit group, therefore an also corresponding memory address of each functional module, described functional module with the corresponding table record of memory address the corresponding relation of each functional module and memory address.After interrupt processing device receives the interrupting information of the first interrupt source transmission, can be first according to the sign of described the first interrupt source, obtain the sign of the first functional module, then according to the sign of the first functional module and described functional module table corresponding to memory address, obtain the memory address of storage unit group corresponding to described the first functional module, piece random access memory can be according to this memory address, export the second interrupt flag bit information of the current storage of storage unit group corresponding to described memory address, described the second interrupt flag bit information recording the first interrupt source while there is not interrupt event, the interrupt flag bit of each interrupt source in the first functional module.Then in the second interrupt flag bit information, interrupt flag bit corresponding to the first interrupt source is set to effectively, obtains the first interrupt flag bit information.

Concrete, when being " 0 ", interrupt flag bit represents that this interrupt flag bit is invalid, when interrupt flag bit is " 1 ", represent that this interrupt flag bit is effective, suppose n=5, before the first interrupt source is interrupted, in the first functional module, each interrupt source is not interrupted, the second interrupt flag bit information is " 00000 ", when the first interrupt source generation interrupt event, in the second interrupt flag bit information, interrupt flag bit corresponding to the first interrupt source is set to " 1 ", suppose that interrupt flag bit corresponding to the first interrupt source in the second interrupt flag bit information is first of the second interrupt flag bit information, the the first interrupt flag bit information obtaining is " 10000 ".

Optionally, in storage unit group corresponding to the first functional module described in piece random access memory, write described the first interrupt flag bit information, concrete can, according to the memory address of storage unit group corresponding to described the first functional module, write described the first interrupt flag bit information in storage unit group corresponding to the first functional module described in piece random access memory.

Example, sign in described the first functional module comprising according to described interrupt event processing instruction, while obtaining the first interrupt flag bit information of storage unit group storage corresponding to described the first functional module, first can be according to the sign of described the first functional module, obtain the memory address of described the first functional module corresponding storage unit group in described random access memory, then according to described memory address, obtain the first interrupt flag bit information of current storage in storage unit group corresponding to described the first functional module.

Interrupt processing device is after receiving the described interrupt event processing instruction of processor transmission, first obtain the sign of the first functional module that this interrupt event processing instruction comprises, then according to the sign of the first functional module, the functional module of preserving in advance with interrupt processing device and the corresponding table of memory address, obtain the memory address of storage unit group corresponding to the first functional module, then interrupt processing device sends to piece random access memory by this memory address, piece random access memory can be according to this memory address, export the first interrupt flag bit information of storage unit group storage corresponding to this memory address.

Further, described random access memory also comprises m mask bit storage sets, the corresponding functional module of mask bit storage sets described in each, described shielding storage sets is for storing the mask bit information of corresponding functional module, described mask bit information comprises the mask bit of all interrupt sources that described functional module comprises, when the described mask bit of any one interrupt source is effective in described functional module, represent that the interrupt event of described interrupt source does not deal with.

And then before described generation interrupt event is processed request, interrupt processing device can also judge that whether mask bit corresponding to described the first interrupt source be effective, described the first interrupt flag bit information in writing described random access memory indicates described the first functional module to have interrupt event, and when mask bit corresponding to described the first interrupt source is invalid, generates described interrupt event and process request.

Example, before generating interrupt event processing request, first judge that whether mask bit corresponding to the first interrupt source be effective, when mask bit corresponding to described the first interrupt source is effective, the interrupt event that the first interrupt source is described does not need to process, and interrupt processing device can generate interrupt event processing request and send to server; When mask bit corresponding to described the first interrupt source is invalid, illustrate that the interrupt event of the first interrupt source need to be processed, at this moment interrupt processing device need to generate interrupt event processing request and send to server.

Need explanation, during initialization, in control system, mask bit corresponding to each interrupt source is all invalid, and in the operational process of control system, processor can arrange the mask bit of each interrupt source as the case may be.Example, if the interrupt event that processor is judged the first interrupt source according to actual conditions does not belong to emergency, do not need to process, can be set to effectively by mask bit corresponding to the first interrupt source; If or the interrupt event that processor is judged the first interrupt source according to actual conditions belongs to emergency, need to process, can mask bit corresponding to the first interrupt source be set to invalid.

Example, according to described interrupt identification bit clear indication information, while removing the effective information of interruption corresponding to the first interrupt source in the described first interrupt flag bit information of described random access memory storage, can be first according to the sign of described the first interrupt source, obtain the memory address of described the first functional module corresponding storage unit group in described random access memory, then according to described memory address, obtain the first interrupt flag bit information of current storage in storage unit group corresponding to described the first functional module, according to the sign of described the first interrupt flag bit information and described the first interrupt source, obtain the 3rd interrupt flag bit information, it is invalid that information corresponding to the first interrupt source described in described the 3rd interrupt flag bit information represents to interrupt, and then according to described memory address, described the 3rd interrupt flag bit information is write to storage unit group corresponding to described the first functional module in described random access memory.

After interrupt processing device gets interrupt identification bit clear indication information, first obtain the sign of the first interrupt source, then according to the sign of the first interrupt source, obtain the sign of the first functional module, and according to the sign of the first functional module and pre-stored functional module table corresponding to memory address, obtain memory address corresponding to described the first functional module, according to this memory address, obtain the first interrupt flag bit information of storage unit group storage corresponding to the first functional module, in described the first interrupt flag bit information, interrupt identification bit representation corresponding to the first interrupt source is effective, then in the first interrupt flag bit information interrupt flag bit corresponding to the first interrupt source be set to invalid, obtain the 3rd interrupt flag bit information, then the 3rd interrupt flag bit information is written in the storage unit group of the first functional module correspondence in piece random access memory.

Concrete, the first interrupt flag bit information that interrupt processing device gets is " 10000 ", wherein interrupt flag bit corresponding to the first interrupt source is " 1 ", represent that this interrupt flag bit is effective, then interrupt flag bit corresponding to interrupt processing device the first interrupt source is set to " 0 ", represent that the first interrupt source has not existed interrupt event, the 3rd interrupt flag bit information obtaining is " 00000 ", then described the 3rd interrupt flag bit information " 00000 " is write in storage unit group corresponding to the first functional module.

The interruption processing method that the embodiment of the present invention provides, if control system comprises at least two functional modules, when the interruption of control system is processed, by piece random access memory, complete the interrupt flag bit of the interrupt source of a plurality of functional modules is stored, then on the basis of piece random access memory, complete writing the interrupt flag bit of the interrupt source of all functions module, read and remove, based on writing of piece random access memory, read and remove, only need a set of interrupt control circuit to realize, compared to prior art, interruption processing method of the present invention do not need for each functional module setting with it corresponding interrupt identification bit register complete the storage of the interrupt flag bit of this functional module, and then need to many cover interrupt control circuits be set for each interrupt identification bit register and realize and writing, read and remove, and avoided use MUX, therefore, interruption processing method provided by the invention, can save hardware resource, and then reduce hardware cost.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.

Claims

1. an interrupt processing device, is characterized in that, for the interrupt source of m functional module is processed, m is more than or equal to 2, and described functional module comprises at least one interrupt source; Described interrupt processing device comprises:

2. interrupt processing device according to claim 1, is characterized in that,

Described random access memory comprises first interface and the second interface, and described first interface is for writing the interrupt flag bit information of any one functional module, and described the second interface is for reading the interrupt flag bit information of any one functional module.

3. interrupt processing device according to claim 1 and 2, is characterized in that,

Described interrupt flag bit writing module comprises the first write data unit, and the first write address unit and first is write and enabled unit;

4. interrupt processing device according to claim 2, is characterized in that,

Described interrupt flag bit output module comprises the first detecting unit, generation unit and transmitting element;

5. interrupt processing device according to claim 4, is characterized in that,

Described random access memory also comprises m mask bit storage sets, the corresponding functional module of mask bit storage sets described in each, described shielding storage sets is for storing the mask bit information of corresponding functional module, described mask bit information comprises the mask bit of all interrupt sources that described functional module comprises, when the described mask bit of any one interrupt source is effective in described functional module, represent that the interrupt event of described interrupt source does not deal with;

6. according to the interrupt processing device described in claim 1,2,4 or 5 any one claims, it is characterized in that,

Described interrupt flag bit is read module and is comprised: read address location and reading data unit;

7. interrupt processing device according to claim 6, is characterized in that,

Described interrupt identification bit clear module comprises that the second write data unit, the second write address unit and second write and enable unit;

8. interrupt processing device according to claim 7, is characterized in that,

Described interrupt identification bit clear module also comprises the second detecting unit;

9. an interruption processing method, is applied to interrupt processing device, it is characterized in that, for the interrupt source of m functional module is processed, m is more than or equal to 2, and described functional module comprises at least one interrupt source; Described interruption processing method comprises:

10. interruption processing method according to claim 9, is characterized in that, described according to the sign of described the first interrupt source, and the first interrupt flag bit information of obtaining the interrupt source that described the first functional module comprises comprises:

11. interruption processing method according to claim 10, is characterized in that, describedly in storage unit group corresponding to the first functional module described in piece random access memory, write described the first interrupt flag bit information and comprise:

12. according to the interruption processing method described in claim 10 or 11, it is characterized in that, the sign of described described the first functional module comprising according to described interrupt event processing instruction, the first interrupt flag bit information of obtaining storage unit group storage corresponding to described the first functional module comprises:

13. according to the interruption processing method described in claim 9 to 11 any one claim, it is characterized in that, described according to described interrupt identification bit clear indication information, the effective information of interruption corresponding to the first interrupt source in the described first interrupt flag bit information of described random access memory storage of removing comprises: