CN102495816A - Quick interrupt graded processing device and method - Google Patents
Quick interrupt graded processing device and method Download PDFInfo
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- CN102495816A CN102495816A CN2011103628428A CN201110362842A CN102495816A CN 102495816 A CN102495816 A CN 102495816A CN 2011103628428 A CN2011103628428 A CN 2011103628428A CN 201110362842 A CN201110362842 A CN 201110362842A CN 102495816 A CN102495816 A CN 102495816A
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Abstract
The invention provides a quick interrupt graded processing device and a method. The quick interrupt graded processing device comprises an interrupt event memory device, an interrupt generating device, an interrupt identification memory device and an interrupt convergence device, wherein the interrupt event memory device is used for storing interrupt events generated by interrupt sources, the interrupt generating device is used for converting the interrupt events of the same interrupt source into 1 bit interrupt identification, the interrupt identification memory device is used for storing all the generated interrupt identifications, the interrupt convergence device is used for compressing the interrupt identifications in a graded manner, storing the compressed interrupt identifications and leading the compressed interrupt identifications to be processed by a CPU (central processing unit), N stages of interrupt convergence device units cascade to form the interrupt convergence device, structures of the interrupt convergence device units are identical, n represents the bit width of data read and written by the CPU, and S represents the total amount of the interrupt source of a circuit system. By the aid of the device and the method, after the CPU receives an interrupt request, only an interrupt identification needs to be searched reversely so as to find a corresponding interrupt event, the corresponding interrupt source can be quickly positioned, processing time is shortened, and the occupancy rate of the CPU is reduced.
Description
Technical field
The present invention relates to data communication technology field, particularly the Interrupt Process device and method.
Background technology
Interruption is meant the reaction that CPU makes phylogenetic certain incident, and processor can temporarily stop the current a certain task of carrying out, and this task is temporarily preserved.Turn to and carry out corresponding handling procedure to this incident.The task of preserving before turning back to again after handling continues to handle.
Interrupt Process generally comprises interrupt request and Interrupt Process process, and CPU receives interrupt request it is responded, and possibly cause that the incident of interrupt request is referred to as interrupt source.CPU obtains need finding corresponding interrupt source after the interrupt requests just can carry out corresponding alignment processing, and system needs as soon as possible interrupt event is formed interrupt source and is notified to CPU and handles.
Usually, as shown in fig. 1, system produces several interrupt sources, and CPU scans a plurality of interrupt sources after receiving interrupt request, check that which interrupt source this request comes from, and handles then.
Now; What the development of technical merit brought is that the system design complicacy is increasingly high; Number that interrupts and reason are also more and more; For example in the middle of the OAM processing capacity in PTN equipment, the entry number that OAM need support is 32768 and arrives 65536 even, and each clauses and subclauses all need independently produce variety of event and need report CPU and handle.
Interruption in the middle of these OAM handle; Major part all can relate to the connectedness of data service, so, necessarily require these interruptions all must be processed; Can not lose; And the connective interruption of OAM can relate to the operation that professional protection is switched, the requirement to the speed of CPU response on all free.
According to the method shown in Fig. 1, after CPU receives interrupt request, need in 65536 interrupt sources, search out the unit that actual generation is interrupted, make the expense of software become big, CPU usage increases, and need expend the too much time.
Summary of the invention
The technical matters that the present invention will solve is: a kind of quick interruption hierarchical processing device and method is provided, makes CPU to locate interrupt source fast, faster processing time has been saved CPU usage.
The present invention solves the problems of the technologies described above the technical scheme of being taked to be: a kind of quick interruption hierarchical processing device, and it is characterized in that: it comprises:
The interrupt event memory storage is used to store the interrupt event that interrupt source produces;
The interruption generating device is used for the interrupt event of same interrupt source is converted into the interrupt identification of 1bit;
The interrupt identification memory storage is used to store all interrupt identifications of generation; And
Interrupt converging device, be used for interrupt identification is carried out implements spatial scalable compression and storage, and transfer to CPU and handle;
Interrupting converging device is formed by the cascade of N level; The structure that each grade interrupts converging device is identical;
n is the CPU bit wide that reads and writes data, and S is the sum of interrupt source in the Circuits System;
Wherein interrupt source is the set from all unit that generation interrupt event demand is arranged in the Circuits System, and encodes according to certain characteristic; Interrupt event is produced by interrupt source, form by a plurality of bits, wherein specific bit put 1 the representative defined should report interrupt event.
Press such scheme, it also comprises interrupt event mask bit device, comprises all interrupt events of answering beyond the reporting terminal incident, is used for comparing with all interrupt events of interrupt event memory storage, only should report interrupt event to pass to the interruption generating device.
Press such scheme, described interruption generating device comprises: be used for interrupting the interruption generating scanner that event storage uninterruptedly scans; Shift register with the interrupt identification that is used to control a n bit of n interrupt source generation of every scanning.
Press such scheme, the bit wide of described interrupt identification memory storage is n, and the address degree of depth is more than or equal to S/n.
Press such scheme, described each grade interrupts converging device and comprises: be used for converging scanner to what the interrupt identification that upper level produces uninterruptedly scanned; Be used for the interrupt identification that the corresponding levels are scanned and carry out n: the interruption compression set of 1 compression; Store the interrupt identification through overcompression at the corresponding levels with being used to, offer the interruption compressing ram of CPU as the foundation of classification inquiry interrupt source.
A kind of quick interruption hierarchical processing method, it is characterized in that: it may further comprise the steps:
1) stores the interrupt event that all interrupt sources produce;
2) interrupt event of same interrupt source is converted into the interrupt identification of 1bit;
3) all interrupt identifications of storage generation;
4) interrupt identification is carried out implements spatial scalable compression and storage, and transfer to CPU and handle; The process of each grade compression memory is identical; Progression
n is the CPU bit wide that reads and writes data, and S is the sum of interrupt source in the Circuits System;
Wherein interrupt source is the set from all unit that generation interrupt event demand is arranged in the Circuits System, and encodes according to certain characteristic; Interrupt event is produced by interrupt source, form by a plurality of bits, wherein specific bit put 1 the representative defined should report interrupt event.
It also stores all interrupt events of answering beyond the reporting terminal incident, is used for comparing with all interrupt events of storage, should report the interrupt event shielding beyond the interrupt event.
Said step 2) uninterruptedly scan interrupting event storage, n interrupt source of every scanning produces the interrupt identification of a n bit.
The process of described each grade compression memory comprises: the interrupt identification that upper level is produced uninterruptedly scans; The interrupt identification that the corresponding levels are scanned also carries out n: 1 compression; The storage interrupt identification through overcompression at the corresponding levels offers the foundation of CPU as classification inquiry interrupt source.
Beneficial effect of the present invention is:
1, through adopting these apparatus and method,, CPU only needs the reverse find interrupt identification after receiving interrupt request and then searches corresponding interrupt event to get final product, can locate interrupt source fast, faster processing time has been saved CPU usage.
2, through increasing interrupt event mask bit device, can be only with reporting interrupt event to produce interrupt identification, the occupancy of further having practiced thrift CPU.
Description of drawings
Fig. 1 is traditional Interrupt Process mode.
Fig. 2 is the overall construction drawing of the embodiment of the invention.
Fig. 3 is the storage mode of interrupt event memory storage.
Fig. 4 is the interruption generating structure drawing of device.
Fig. 5 is for adding the structural drawing of interrupt event mask bit.
Fig. 6 is interrupt identification storage synoptic diagram.
Fig. 7 is for interrupting the converging device structural drawing.
Fig. 8 is CPU inquiry interrupt event flow process.
Embodiment
According to accompanying drawing and specific embodiment the present invention is further set forth below.
Fig. 2 is the overall construction drawing of the embodiment of the invention, and it comprises: the interrupt event memory storage is used to store the interrupt event that interrupt source produces; The interruption generating device is used for the interrupt event of same interrupt source is converted into the interrupt identification of 1bit; The interrupt identification memory storage is used to store all interrupt identifications of generation; And the interruption converging device, be used for interrupt identification is carried out implements spatial scalable compression and storage, and transfer to CPU and handle.
Interrupting converging device is formed by the cascade of N level; The structure that each grade interrupts converging device is identical; Consider the bit wide that CPU reads and writes data; All interruptions are through the interruption converging device of certain progression, finally can pool the read and write data final packed data of bit wide of a coupling CPU, and with this data step-by-step with obtain final interrupting information; Therefore
n is the CPU bit wide that reads and writes data, and S is the sum of interrupt source in the Circuits System.With cpu data bit wide 16bit in the present embodiment is example; Total interrupt source is S, and the progression N that interrupts converging can obtain through following formula:
N is 16 in the present embodiment, and total interrupt source is 64K, and interrupting converging device is 3 grades of cascades.
Wherein interrupt source is the set from all unit that generation interrupt event demand is arranged in the Circuits System, and encodes according to certain characteristic; Interrupt event is produced by interrupt source, form by a plurality of bits, wherein specific bit put 1 the representative defined should report interrupt event.
Fig. 3 is the storage mode of interrupt event memory storage, and line number is the sum of interrupt source, all interrupt events that the same interrupt source of each row storage produces.
Fig. 4 is the interruption generating structure drawing of device, comprises being used for the interruption generating scanner that the interruption event storage is uninterruptedly scanned and being used to control the shift register that 16 interrupt sources of every scanning produce the interrupt identification of a 16bit.As shown in Figure 5; Can also add interrupt event mask bit device; Comprise all interrupt events of answering beyond the reporting terminal incident; Be used for all interrupt events of interrupt event memory storage relatively, only should report interrupt event to pass to the interruption generating device, whether need report CPU and handle in order to control various interrupt events.
The interrupt identification memory storage is used to store the interrupt identification of each interrupt source; The bit wide of this RAM is 16bit, and the address degree of depth is S/16, and storage order is as shown in Figure 6; Any 1bit of arbitrary address among the RAM; By RAM (addr, d [n]) expression, represent among interrupt source addr * 16+n and produced interrupt event.
Interrupt the converging device effect and be extracting all interrupt identifications and carry out compression memory according to 16: 1 ratio of compression; As shown in Figure 7; Contain a plurality of converging devices in the total system; Below, interrupting converging device with the first order is that example is introduced, and comprises the interrupt scanning device, interrupts compression set, interrupts the compression memory device.
The interrupt scanning device is to be driven by counter, and interrupt identification is uninterruptedly scanned, and considers that CPU obtains the operation of interruption, and native system adopts the design of an address of 2 clock period scanning.Address space is S/16, and wherein S is the sum of interrupt source in the Circuits System, and the scan period that the first order is interrupted convergence module is (S/16) * 2f
ClkF wherein
ClkBe clock frequency.The scan period that the N level is interrupted convergence module is (S/16
N) * 2f
Clk, to interrupt convergence module with 3 grades of this designs and calculate, the T.T. of interrupt scanning at different levels does
Interrupting compression set is made up of a shift register; The uninterrupted interrupt identification that scans that receives, in the interrupt identification storage owing to upper level, an address is 16bit; With its interrupting information through 1 1bit of logical and operation boil down to; And send in the middle of the shift register, 16 addresses of every scanning promptly form the packed data of a 16bit.
Interrupt the interrupt identification of compression memory device storage through overcompression, offer the foundation of CPU as classification inquiry interrupt source, the data bit width that each grade interrupts compression memory all is 16bit, and the address degree of depth is S/16
N+1, in this memory storage arbitrarily bit RAM (addr, d [n]) value be 1, represent the [(addr * 16+n) * 16 of interval in the pairing interrupt source
N, (addr * 16+n+1) * 16
N] contain interrupt identification between among the interval, wherein, N is the progression of current interruption converging device, is example with the present embodiment, the first order, the second level, the address degree of depth that the third level is interrupted compression memory is respectively 256,16,1.
The interruption collecting system of cascade by this way, CPU are when inquiry, and from beginning to look near the interruption compression memory of CPU one side, each grade interrupts the foundation that compression memory can be searched upper level interruption compression memory as CPU.Finally can obtain final interrupt source through the inquiry of N+1 level.Thereby acquisition interrupt event.In the present embodiment, CPU can locate interrupt source through 4 inquiries.
Below, will the operator scheme of CPU be described, understand this design to improving the advantage that the CPU processing speed is brought like Fig. 8 with help.Converge with three grades of interruptions and to be example.
CPU checks that at first interrupting compression memory 3, a bits is 1 after obtaining interrupt request, the address that can obtain to interrupt compression memory 2 is a;
Further, check the address b that interrupts in the compression memory 2, find that the x bit is 1 among a of address, then obtain interrupting the address b=a * 16+x of compression memory 1 according to formula;
Further, check the address b that interrupts in the compression memory 1, find that the y bit is 1 among the b of address, can obtain interrupt identification address stored c=b * 16+y;
Further, check the address c in the interrupt identification storage, find that the z bit is 1 among the c of address, can obtain the s=c * 16+z that is numbered of interrupt source.
Can know that through above-mentioned analysis no matter the some interrupt events that produced in 65536 interrupt source, CPU can search the definite actual interrupt source of orienting through 4 steps, thereby has improved the treatment effeciency of CPU.
Claims (9)
1. one kind interrupts the hierarchical processing device fast, and it is characterized in that: it comprises:
The interrupt event memory storage is used to store the interrupt event that interrupt source produces;
The interruption generating device is used for the interrupt event of same interrupt source is converted into the interrupt identification of 1bit;
The interrupt identification memory storage is used to store all interrupt identifications of generation; And
Interrupt converging device, be used for interrupt identification is carried out implements spatial scalable compression and storage, and transfer to CPU and handle;
Interrupting converging device is formed by the cascade of N level; The structure that each grade interrupts converging device is identical;
; N is the CPU bit wide that reads and writes data, and S is the sum of interrupt source in the Circuits System;
Wherein interrupt source is the set from all unit that generation interrupt event demand is arranged in the Circuits System, and encodes according to certain characteristic; Interrupt event is produced by interrupt source, form by a plurality of bits, wherein specific bit put 1 the representative defined should report interrupt event.
2. quick interruption hierarchical processing device according to claim 1; It is characterized in that: it also comprises interrupt event mask bit device; Comprise all interrupt events of answering beyond the reporting terminal incident; Be used for comparing, only should report interrupt event to pass to the interruption generating device with all interrupt events of interrupt event memory storage.
3. quick interruption hierarchical processing device according to claim 1 and 2, it is characterized in that: described interruption generating device comprises: be used for interrupting the interruption generating scanner that event storage uninterruptedly scans; Shift register with the interrupt identification that is used to control a n bit of n interrupt source generation of every scanning.
4. quick interruption hierarchical processing device according to claim 3; It is characterized in that: the bit wide of described interrupt identification memory storage is n, and the address degree of depth is more than or equal to
.
5. quick interruption hierarchical processing device according to claim 3 is characterized in that: described each grade interrupts converging device and comprises: be used for converging scanner to what the interrupt identification that upper level produces uninterruptedly scanned; The interruption compression set that is used for the interrupt identification that the corresponding levels are scanned and carries out the n:1 compression; Store the interrupt identification through overcompression at the corresponding levels with being used to, offer the interruption compressing ram of CPU as the foundation of classification inquiry interrupt source.
6. one kind interrupts hierarchical processing method fast, and it is characterized in that: it may further comprise the steps:
1) stores the interrupt event that all interrupt sources produce;
2) interrupt event of same interrupt source is converted into the interrupt identification of 1bit;
3) all interrupt identifications of storage generation;
4) interrupt identification is carried out implements spatial scalable compression and storage, and transfer to CPU and handle; The process of each grade compression memory is identical; Progression
; N is the CPU bit wide that reads and writes data, and S is the sum of interrupt source in the Circuits System;
Wherein interrupt source is the set from all unit that generation interrupt event demand is arranged in the Circuits System, and encodes according to certain characteristic; Interrupt event is produced by interrupt source, form by a plurality of bits, wherein specific bit put 1 the representative defined should report interrupt event.
7. quick interruption hierarchical processing method according to claim 6; It is characterized in that: it also stores all interrupt events of answering beyond the reporting terminal incident; Be used for comparing, should report the interrupt event shielding beyond the interrupt event with all interrupt events of storage.
8. according to claim 6 or 7 described quick interruption hierarchical processing methods, it is characterized in that: said step 2) uninterruptedly scan interrupting event storage, n interrupt source of every scanning produces the interrupt identification of a n bit.
9. quick interruption hierarchical processing method according to claim 8, it is characterized in that: the process of described each grade compression memory comprises: the interrupt identification that upper level is produced uninterruptedly scans; The interrupt identification that the corresponding levels are scanned also carries out the n:1 compression; The storage interrupt identification through overcompression at the corresponding levels offers the foundation of CPU as classification inquiry interrupt source.
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| CN201110362842.8A CN102495816B (en) | 2011-11-16 | 2011-11-16 | Quick interrupt graded processing device and method |
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| CN201110362842.8A CN102495816B (en) | 2011-11-16 | 2011-11-16 | Quick interrupt graded processing device and method |
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| CN102495816B CN102495816B (en) | 2014-12-24 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120284443A1 (en) * | 2010-03-18 | 2012-11-08 | Panasonic Corporation | Virtual multi-processor system |
| CN104111870A (en) * | 2014-07-08 | 2014-10-22 | 福建星网锐捷网络有限公司 | Interrupt processing device and method |
| CN110083447A (en) * | 2019-04-26 | 2019-08-02 | 宁波三星医疗电气股份有限公司 | A kind of interruption processing method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US3905025A (en) * | 1971-10-27 | 1975-09-09 | Ibm | Data acquisition and control system including dynamic interrupt capability |
| CN1786933A (en) * | 2005-12-02 | 2006-06-14 | 北京中星微电子有限公司 | Apparatus and method of multi-grade interrupt applicant |
| CN101634939A (en) * | 2008-07-24 | 2010-01-27 | 中兴通讯股份有限公司 | Fast addressing device and method thereof |
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2011
- 2011-11-16 CN CN201110362842.8A patent/CN102495816B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3905025A (en) * | 1971-10-27 | 1975-09-09 | Ibm | Data acquisition and control system including dynamic interrupt capability |
| CN1786933A (en) * | 2005-12-02 | 2006-06-14 | 北京中星微电子有限公司 | Apparatus and method of multi-grade interrupt applicant |
| CN101634939A (en) * | 2008-07-24 | 2010-01-27 | 中兴通讯股份有限公司 | Fast addressing device and method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120284443A1 (en) * | 2010-03-18 | 2012-11-08 | Panasonic Corporation | Virtual multi-processor system |
| US8725921B2 (en) * | 2010-03-18 | 2014-05-13 | Panasonic Corporation | Virtual multi-processor system |
| CN104111870A (en) * | 2014-07-08 | 2014-10-22 | 福建星网锐捷网络有限公司 | Interrupt processing device and method |
| CN104111870B (en) * | 2014-07-08 | 2017-05-24 | 福建星网锐捷网络有限公司 | Interrupt processing device and method |
| CN110083447A (en) * | 2019-04-26 | 2019-08-02 | 宁波三星医疗电气股份有限公司 | A kind of interruption processing method and system |
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