CN110851259B - Interrupt control method, interrupt controller, computer device and storage medium - Google Patents
Interrupt control method, interrupt controller, computer device and storage medium Download PDFInfo
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Abstract
The invention discloses an interrupt control method, an interrupt controller, computer equipment and a storage medium, wherein the method comprises the following steps: receiving an interrupt signal input by at least one interrupt source; judging whether a received interrupt signal set is matched with a preset processor interrupt triggering condition, wherein the interrupt signal set comprises a plurality of received interrupt signals and an interrupt event occurrence sequence; and if the interrupt trigger condition is matched with the preset interrupt trigger condition of the processor, sending an interrupt signal to the processor. The interrupt control method provided by the embodiment of the invention can be used for counting the received interrupt signals by the interrupt controller before sending the interrupt signals to the processor, and sending the interrupt signals to the processor when the generated interrupt signals meet the preset processor interrupt triggering conditions such as sequence, quantity, combination and the like, so that the use amount of processor resources can be reduced. Meanwhile, the condition of sending the interrupt signal to the processor can be flexibly configured and triggered, and the usability is high.
Description
Technical Field
The present invention relates to computer technologies, and in particular, to an interrupt control method and an interrupt controller.
Background
In modern Chip systems (SoC), a Chip often needs to integrate rich input/output (I/O) devices, complex buses, various special Processing circuits, and general purpose ip (intelligent performance) units in addition to a Central Processing Unit (CPU) or a Microcontroller (MCU). The interrupt output of these rich and numerous peripheral circuits is much larger than the number of interrupt interfaces of the CPU or MCU.
At present, the interrupt controller usually adopts a fixed priority or a hardware configurable priority, the programmability and the expandability of the fixed priority mode are poor, and the hardware configurable priority mode brings extra time delay under the switching of different priority modes. The continuously evolving software application requirements require that the system control hardware has greater flexibility, so that the control requirements under different application scenes are met. It is obvious that the current interrupt mechanism occupies a large amount of processor resources, has poor programmability, and is unable to expand the interrupt processing method of various interrupt inputs, which is called the problem to be solved urgently.
Disclosure of Invention
The invention provides an interrupt control method, an interrupt controller, a computer device and a storage medium, which can reduce the use amount of processor resources, provide more flexible programmability and expand interrupt processing supporting a plurality of interrupt inputs.
In a first aspect, an embodiment of the present invention provides an interrupt control method, including:
receiving an interrupt signal input by at least one interrupt source;
judging whether a received interrupt signal set is matched with a preset processor interrupt triggering condition, wherein the interrupt signal set comprises a plurality of received interrupt signals and interrupt event occurrence sequences;
and if the interrupt trigger condition is matched with the preset interrupt trigger condition of the processor, sending an interrupt signal to the processor.
In a second aspect, an embodiment of the present invention further provides an interrupt controller, including:
an event source input distributor for receiving an interrupt signal of at least one interrupt source input;
the event combiner is used for determining an event combination according to the event signal;
and the event output selector is used for judging whether the event combination is matched with a preset processor interrupt trigger condition, wherein the preset processor interrupt trigger condition comprises a preset event combination.
The interrupt buffer is used for buffering the interrupt event sent to the CPU and clearing the interrupt event after the CPU program finishes processing the interrupt.
In a third aspect, an embodiment of the present invention further provides a computer device, including a memory, a processor, an interrupt controller, and a computer program stored in the memory and operable on the interrupt controller, where the interrupt controller is connected to at least one input device; the interrupt controller is connected with the processor; the interrupt controller implements the interrupt control method as shown in the first aspect when executing the program.
In a fourth aspect, the present invention further provides a storage medium containing computer-executable instructions, which when executed by an interrupt controller in a computer, are configured to perform the interrupt control method according to the first aspect.
The interrupt control scheme provided by the embodiment of the invention can judge whether a received interrupt signal set is matched with a preset processor interrupt trigger condition or not after receiving an interrupt signal input by at least one interrupt source, wherein the interrupt signal set comprises a plurality of received interrupt signals and interrupt event sequences; and when the received interrupt signal set is matched with a preset processor interrupt triggering condition, sending an interrupt signal to the processor. Compared with the existing method that all interrupt signals of input and output equipment are sent to a processor (such as a CPU or an MCU), the interrupt control method provided by the embodiment of the invention can be used for counting the received interrupt signals by the interrupt controller before sending the interrupt signals to the processor, sending the interrupt signals to the processor when the generated interrupt signals meet the preset interrupt triggering conditions of the processor in sequence, quantity, combination and the like, and further avoiding the operation of counting, comparing and the like on a plurality of interrupt signals by the processor, so that the use amount of processor resources can be reduced. Meanwhile, the user can flexibly configure the conditions for triggering the sending of the interrupt signals to the processor by editing the interrupt triggering conditions of the processor, can expand the interrupt processing supporting multiple interrupt inputs and has strong usability.
Drawings
FIG. 1 is a flow chart diagram of an interrupt control method according to a first embodiment of the present invention;
FIG. 2 is a flow chart diagram of an interrupt control method according to a second embodiment of the present invention;
FIG. 3 is a flow chart diagram of an interrupt control method according to a third embodiment of the present invention;
FIG. 4 is a block diagram of an interrupt controller according to a fourth embodiment of the present invention;
FIG. 5 is a block diagram of another interrupt controller according to a fourth embodiment of the present invention;
fig. 6 is a schematic structural diagram of a computer device in the fifth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Currently, in real-time systems, there are very stringent requirements on event processing time. For complex interrupt event processing combination sequences, frequent in and out interrupts bring more additional time overhead to the system. For example: the system will respond D after "interrupt event a- > N interrupt events B- > interrupt event C". Then the CPU time taken for the whole sequence processing is: event a interrupt entry time + event a record time + event a interrupt exit time + N × (event B interrupt entry time + event B record time + event B interrupt exit time) + event C interrupt entry time + response D processing time + event C interrupt exit time. Removing the processing event of the response event and the recording time of the interrupt event, if the entry and exit time of all the interrupts are considered similar, the CPU time overhead caused by the interrupts is: (N +2) × (interrupt entry time + interrupt exit time). For very important and critical CPU resources, too much processing power for executing interrupt processing obviously reduces the overall processing efficiency of the CPU. The embodiment of the invention provides an interrupt control method, which is used for monitoring and detecting a combined event of a trigger event by an interrupt controller before sending an interrupt signal to a CPU (central processing unit), and sending the interrupt signal to the CPU when the event combination needing to trigger the CPU interrupt occurs, wherein the time for the CPU to process the interrupt event is only one interrupt processing period (one interrupt entering and exiting time), so that the CPU is greatly reduced. The specific scheme is described by the following examples.
Example one
Fig. 1 is a flowchart illustrating an interrupt control method according to an embodiment of the present invention, where the embodiment is applicable to a system on chip and can be executed by a chip processor or an electronic device having a chip, and the method specifically includes the following steps:
The interrupt signal is triggered by the external module, and the interrupt signal sent by the external module can be acquired through the interface.
The preset processor interrupt trigger condition may be pre-configured by a programmer. As the number of received interrupt signals increases, a sequence of events is formed in the set of interrupt signals in chronological order. The event is determined by an interrupt signal. When the sequence of events is the same as the preset processor interrupt trigger condition, a match is determined and step 130 is performed. If the event sequence is not the same as the predetermined processor interrupt trigger condition, it is determined that the event sequence does not match the predetermined processor interrupt trigger condition, and step 140 is performed.
And step 130, if the interrupt trigger condition is matched with the preset interrupt trigger condition of the processor, sending an interrupt signal to the processor.
And if the received interrupt signal set is matched with a preset processor interrupt triggering condition, informing the processor to carry out interrupt processing once. Further, if the processor needs to know the conditions that triggered the interrupt, a preset processor interrupt trigger condition or its identification may be sent to the processor. Optionally, the processor may configure the interrupt controller according to the interrupt condition, and the interrupt controller detects and controls the interrupt condition.
And 140, if the processor interrupt trigger condition is not matched with the preset processor interrupt trigger condition, returning to execute the step 110 and the step 120 until the processor interrupt trigger condition is matched with the preset processor interrupt trigger condition.
If the interrupt sequence does not match the preset interrupt triggering condition of the processor, the current triggered interrupt sequence does not reach the condition that the processor can not interrupt, and the interrupt signal is continuously acquired.
Furthermore, the interrupt event sent to the CPU of the processor is cached, and the interrupt event is cleared after the CPU program finishes processing the interrupt.
The interrupt controller buffers interrupt events sent to the processor CPU prior to sending an interrupt signal to the processor. After sending the interrupt signal to the processor, to avoid redundant storage, the interrupt event may be cleared after the processor has processed the interrupt event.
The interrupt control method provided by the embodiment of the invention can judge whether a received interrupt signal set is matched with a preset interrupt trigger condition of a processor or not after receiving an interrupt signal input by at least one interrupt source, wherein the interrupt signal set comprises a plurality of received interrupt signals and interrupt event sequences; and when the received interrupt signal set is matched with a preset processor interrupt triggering condition, sending an interrupt signal to the processor. Compared with the existing method that all interrupt signals of input and output equipment are sent to a processor (such as a CPU or an MCU), the interrupt control method provided by the embodiment of the invention can be used for counting the received interrupt signals by the interrupt controller before sending the interrupt signals to the processor, sending the interrupt signals to the processor when the generated interrupt signals meet the preset interrupt triggering conditions of the processor in sequence, quantity, combination and the like, and further avoiding the operation of counting, comparing and the like on a plurality of interrupt signals by the processor, so that the use amount of processor resources can be reduced. Meanwhile, the user can flexibly configure the conditions for triggering the sending of the interrupt signals to the processor by editing the interrupt triggering conditions of the processor, can expand the interrupt processing supporting multiple interrupt inputs and has strong usability.
Example two
Fig. 2 is a schematic flow chart of an interrupt control method according to a second embodiment of the present invention, which is used to further describe the above embodiment, and includes:
Wherein the set of interrupt signals includes a plurality of received interrupt signals and a sequence of interrupt event occurrences.
Optionally, a preprocessing operation is performed according to an input event represented by the first interrupt signal to obtain an event signal, the preprocessing operation includes an edge detection operation, a polarity inversion operation, or a pulse-to-level conversion operation, and the event type represented by the event signal includes: a bypass output event, a rising edge event, a falling edge event, a pulse level transition event, or a level event.
A rising edge event may indicate a point in time at which the beginning of a certain event occurs, and a falling edge event may indicate a point in time at which the end of a certain event occurs. The pulse time may be buffered by converting the pulse to a level.
The input events are subjected to edge detection, polarity inversion, pulse-to-level conversion and the like, and six different output event signals can be output by each input event signal: bypass outputs, rising edge events, falling edge events, rising/falling edge events, pulse level transition events, and level events. Level events may also configure level polarities.
After the event signals are determined, the event signals are combined according to a time sequence to obtain an event combination in step 220.
And step 250, if the interrupt trigger condition of the processor is matched with the preset interrupt trigger condition of the processor, sending an interrupt signal to the processor.
The interrupt control method provided by the embodiment of the invention can determine the event combination according to the received interrupt signal, and determine whether to send the interrupt signal to the processor or not based on the matching condition of the event combination and the preset interrupt trigger condition of the processor. Compared with the situation that whether the event combination interruption is triggered or not needs to be summarized and compared by the processor at present, the embodiment of the invention can summarize the received interruption signals and form the event combination before the interruption signals are sent to the processor, thereby avoiding summarizing the event combination by the processor, reducing the load of the processor and improving the utilization rate of the processor.
EXAMPLE III
Fig. 3 is a schematic flow chart of an interrupt control method according to a third embodiment of the present invention, which is used to further describe the above embodiment, and includes:
Wherein the set of interrupt signals includes a plurality of received interrupt signals and a sequence of interrupt event occurrences.
Optionally, a preprocessing operation is performed according to an input event represented by the first interrupt signal to obtain an event signal, the preprocessing operation includes an edge detection operation, a polarity inversion operation, or a pulse-to-level conversion operation, and the event type represented by the event signal includes: a bypass output event, a rising edge event, a falling edge event, a pulse level transition event, or a level event.
In step 330, between the start event and the end event, the preset event or time is counted, and the occurrence number and duration of the preset event can be obtained.
and step 360, judging whether the event combination is matched with a preset processor interrupt triggering condition or not, wherein the event combination comprises at least one comparison event.
The interrupt control method provided by the embodiment of the invention can count the repeatedly triggered events, further can accurately count the triggering times of the events when the event combination comprises the events triggered for multiple times, and sends an interrupt signal to the processor when the event combination meets the preset interrupt triggering conditions of the processor, thereby improving the usability and the efficiency of the processor.
Example four
Fig. 4 is a schematic structural diagram of an interrupt controller according to a fourth embodiment of the present invention, where the interrupt controller is applied to a system on chip and used for sending an interrupt signal to a Central Processing Unit (CPU) or a Microcontroller Unit (MCU). The interrupt controller includes an event source input distributor 41, a judgment module 42, and an interrupt handler 43. Wherein:
an event source input distributor 41 for receiving an interrupt signal of at least one interrupt source input;
the judging module 42 is configured to judge whether a received interrupt signal set matches a preset processor interrupt trigger condition, where the interrupt signal set includes a plurality of received interrupt signals;
and the interrupt processor 43 is configured to send an interrupt signal to the processor if the interrupt trigger condition matches a preset processor interrupt trigger condition.
Further, as shown in fig. 5, the determining module 42 includes: an event source generator 421, an event combiner 422, and an event output selector 423, wherein,
the event source generator 421 is configured to determine an event signal according to a first interrupt signal, where the first interrupt signal is any one of interrupt signals in an interrupt signal set;
the event combiner 422 is configured to determine an event combination according to the event signal;
the event output selector 423 is configured to determine whether the event combination matches a preset processor interrupt trigger condition, where the preset processor interrupt trigger condition includes the preset event combination.
Further, the event output selector 423 is configured to perform a preprocessing operation according to an input event represented by the first interrupt signal, so as to obtain an event signal, where the preprocessing operation includes an edge detection operation, a polarity inversion operation, or a pulse-to-level conversion operation, and the event type represented by the event signal includes: a bypass output event, a rising edge event, a falling edge event, a pulse level transition event, or a level event.
Further, the determining module 42 further includes an event counter 424, configured to count a preset event or time between the start event and the end event, so as to obtain the occurrence frequency and duration of the preset event;
when the counting result is matched with the preset counting result, outputting a comparison event;
accordingly, the event output selector 423 is configured to determine whether an event combination including at least one comparison event matches a preset processor interrupt trigger condition.
Further, the determining module 42 further includes an interrupt buffer 425;
the interrupt buffer 425 is used to buffer the interrupt events sent to the CPU and to clear the interrupt events after the CPU program has finished processing the interrupt.
Further, an embodiment of the present invention further provides a method for programming an interrupt controller, where the method includes:
configuring the event source input distributor 41, the judgment module 42 and the interrupt handler 43, so that the event source input distributor 41 determines an event signal according to a first interrupt signal, where the first interrupt signal is any one interrupt signal in an interrupt signal set; the event combiner 422 determines an event combination from the event signals; the event output selector 423 determines whether the event combination matches a preset processor interrupt trigger condition, where the preset processor interrupt trigger condition includes a preset event combination.
The interrupt controller has programmability and expandability. The preset processor interrupt triggering conditions and the like can be edited according to actual use requirements so as to be suitable for different devices and improve usability.
The interrupt control device provided in the embodiment of the present invention can determine, by the determining module 42, whether a received interrupt signal set is matched with a preset processor interrupt trigger condition after the event source input distributor 41 receives an interrupt signal input by at least one interrupt source, where the interrupt signal set includes a plurality of received interrupt signals and an interrupt event sequence; the interrupt handler 43 sends an interrupt signal to the processor when the received set of interrupt signals matches a preset processor interrupt trigger condition. Compared with the existing method that all interrupt signals of input and output equipment are sent to a processor (such as a CPU or an MCU), the interrupt control method provided by the embodiment of the invention can be used for counting the received interrupt signals by the interrupt controller before sending the interrupt signals to the processor, sending the interrupt signals to the processor when the generated interrupt signals meet the preset interrupt triggering conditions of the processor in sequence, quantity, combination and the like, and further avoiding the operation of counting, comparing and the like on a plurality of interrupt signals by the processor, so that the use amount of processor resources can be reduced. Meanwhile, the user can flexibly configure the conditions for triggering the sending of the interrupt signals to the processor by editing the interrupt triggering conditions of the processor, can expand the interrupt processing supporting multiple interrupt inputs and has strong usability.
The interrupt controller provided by the embodiment of the invention can execute the interrupt control method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
In one implementation of an embodiment of the invention, the interrupt controller may be implemented by:
the event source input dispatcher 41 may receive N (N >1) interrupt source inputs, and since the count output J (J >1) of the event counter 424 may also be fed back as an interrupt event input, the event source input dispatcher 41 receives (N + J) events in total. And distributes these events to M (M ═ N + J) event source generators 421. The event source input distributor 41 is integrated with M (N + J) 1-out selectors, and the output of each selector is programmable.
The event source generator 421 performs operations such as edge detection, polarity inversion, and pulse-to-level conversion on the input event, and each interrupt source generator can output 6 different output event signals according to the input event signal: bypass outputs, rising edge events, falling edge events, rising/falling edge events, pulse level transition events, and level events. Level events may also configure level polarities. The number of events after passing event source generator 421 is thus 6 × M.
The event combiner 422 may integrate P (P >1) two-input logic and gates and Q (Q >1) two-input logic or gates according to requirements, where an input of each and or gate may be selected as any one of the 6 × M events, so as to complete the combined output of different events, and the combiner has (P + Q) events as common inputs.
The event output selector 423 receives the outputs of the event source generator 421 and the event combiner 422, and outputs (6 × M + P + Q) event selections to the K interrupt handlers 43 and the J event counters 424. Each output may be any one of (6 × M + P + Q) events, so that (K + J) 1-out (6 × M + P + Q) selectors need to be integrated in the event output selector 423, and the output of each selector is programmable.
The event counter 424 counts input pulse events (cnt _ pulse) or level events (cnt _ level) within the time of a start event (cnt _ start) and an end event (cnt _ stop), which may also be controlled to start and end using internal registers, and which may also include internally selectable constant 1 events. When the counting value reaches the comparison register, a comparison event is output, and the value of the comparison register is programmable and controllable. The counting mode comprises a single mode and a repeated mode: in a single mode, when the comparison register is counted, locking is carried out, a comparison event is output, and the counter can start the next counting operation only by resetting software; in the repeat mode, when the counter counts to the comparison register, the repeat count is automatically cleared, so that a plurality of comparison events are repeatedly output.
The number of interrupt handlers 43 corresponds one-to-one to the number of interrupt inputs of the CPU or MCU, and each interrupt handler may have a different number of event inputs. Assuming that Ki interrupt inputs of the interrupt handler i are provided, Ki AND gates in the interrupt handler i perform independent enabling control on Ki events, and when any enabling event occurs (the rising edge is effective), outputting an interrupt to the CPU/MCU. When software enters an interrupt service program, the software can flexibly define the interrupt priority, and a plurality of interrupt events are processed according to the priority defined by the software as shown in the following figure.
The interrupt controller as described above employs a flexible programmable and modular design that makes it adaptable to different systems. The method can be applied to the following four scenes through software configuration:
1. a single level or pulse event triggers an interrupt, which directly selects the output of the interrupt source generator to the interrupt controller.
2. A single level or pulse event count interrupt, which uses an event counter to count single events, triggering an interrupt when a certain comparison value is reached.
3. And triggering the interrupt by a multi-event occurrence sequence, and adopting an interrupt combiner to combine a plurality of events and outputting the combined operation to an interrupt controller in the scene. For example, the occurrence of the sequence of events A- > B- > C triggers only one interrupt to CPU, the event A is converted into a level event level (A) through a pulse-to-level converter in an interrupt source generator, the event B is converted into a pulse event pulse (B) through the interrupt source generator, and the level (A) event and the pulse (B) event are subjected to AND operation in an interrupt combiner to output the A- > B event. By the same method, the A- > B event and the event C are respectively input to an interrupt source generator to generate a corresponding level event and a corresponding pulse event, and then the level event and the pulse event are sent to another interrupt combiner to carry out logic and operation, and an event triggered by an A- > B-C sequence is output to an interrupt processor.
4. The count within the two event windows is interrupted. For example, if an interrupt is triggered to the CPU 5 times in the event of the event A and the event B, the interrupt source generator is used for converting the event A and the event B into pulse events (A) and (B), and for one interrupt counter, the pulse event (A) and the pulse event (B) are used for counting the starting condition and the ending condition of counting, and an interrupt event triggered after 5 times in the interval is marked as A- > 5C- > B and is output to the interrupt handler.
Scenario 1 is a normal interrupt controller function, scenarios 2, 3 and 4 are complex interrupt scenarios that the present invention can handle, thereby greatly reducing CPU processing time, and scenario 4 can be used for a system enable monitoring function in cooperation with a timer in the system. Through the interrupt combination function and the cascade function of the interrupt controller provided by the embodiment of the invention, more complex interrupt sequences after various combinations of the 4 scenes can be processed.
EXAMPLE five
Fig. 5 is a schematic structural diagram of a computer apparatus according to a fifth embodiment of the present invention, as shown in fig. 5, the computer apparatus includes a processor 50, a memory 51, an input device 52, and an output device 53; the number of processors 50 in the computer device may be one or more, and one processor 50 is taken as an example in fig. 5; the processor 50, the memory 51, the input device 52 and the output device 53 in the computer apparatus may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 5.
The memory 51 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the interrupt control method in the embodiment of the present invention (for example, the event source input distributor 41, the judgment module 42, the interrupt handler 43, the event source generator 421, the event combiner 422, and the event output selector 423, the event counter 424, and the interrupt buffer 425). The processor 50 executes various functional applications and data processing of the computer device by executing software programs, instructions and modules stored in the memory 51, that is, implements the above-described interrupt control method.
The memory 51 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the interrupt, and the like. Further, the memory 51 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 51 may further include memory located remotely from the processor 50, which may be connected to a computer device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 52 is operable to receive input numeric or character information and to generate key signal inputs relating to user settings and function controls of the computer apparatus. The output device 53 may include a display device such as a display screen.
EXAMPLE six
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a method for interrupt control, the method including:
receiving an interrupt signal input by at least one interrupt source;
judging whether a received interrupt signal set is matched with a preset processor interrupt triggering condition, wherein the interrupt signal set comprises a plurality of received interrupt signals and an interrupt event occurrence sequence;
and if the interrupt trigger condition is matched with the preset interrupt trigger condition of the processor, sending an interrupt signal to the processor.
Further, determining whether the received interrupt signal set matches a preset processor interrupt trigger condition includes:
determining an event signal according to a first interrupt signal, wherein the first interrupt signal is any one interrupt signal in an interrupt signal set;
determining an event combination according to the event signal;
and judging whether the event combination is matched with a preset processor interrupt triggering condition, wherein the preset processor interrupt triggering condition comprises a preset event combination.
Further, determining the event signal according to the first interrupt signal includes:
performing a preprocessing operation according to an input event represented by the first interrupt signal to obtain an event signal, wherein the preprocessing operation comprises an edge detection operation, a polarity inversion operation or a pulse-to-level conversion operation, and the event type represented by the event signal comprises: a bypass output event, a rising edge event, a falling edge event, a pulse level transition event, or a level event.
Further, after determining the event signal according to the first interrupt signal, the method further includes:
counting preset events or time between a starting event and an ending event to obtain the occurrence frequency and duration of the preset events;
when the counting result is matched with the preset counting result, outputting a comparison event;
correspondingly, whether the event combination is matched with a preset processor interrupt trigger condition is judged, and the preset processor interrupt trigger condition comprises a preset event combination and comprises the following steps:
and judging whether the event combination is matched with a preset processor interrupt triggering condition or not, wherein the event combination comprises at least one comparison event. Of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the above method operations, and may also perform related operations in the interrupt control method provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods of the embodiments of the present invention.
It should be noted that, in the embodiment of the above search apparatus, each included unit and module are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. An interrupt control method, comprising:
receiving an interrupt signal input by at least one interrupt source, and determining an event signal according to the interrupt signal;
determining an event sequence according to the event signals according to the time sequence, wherein the event sequence represents the event sequence and the event number which are triggered in sequence according to the time sequence; the number of the events is the number of continuous triggers of the same event;
judging whether the event sequence is matched with a preset processor interrupt trigger condition, wherein the preset processor interrupt trigger condition is a preset event sequence configured by a programmer in advance;
and if the interrupt trigger condition is matched with the preset interrupt trigger condition of the processor, sending an interrupt signal to the processor.
2. The interrupt control method of claim 1, wherein determining an event signal based on the interrupt signal comprises:
performing preprocessing operation according to an input event represented by the interrupt signal to obtain an event signal, wherein the preprocessing operation comprises edge detection operation, polarity inversion operation or pulse-to-level conversion operation, and the event type represented by the event signal comprises: a bypass output event, a rising edge event, a falling edge event, a pulse level transition event, or a level event.
3. The interrupt control method of claim 1, further comprising, after determining an event signal based on the interrupt signal:
counting preset events or time between a starting event and an ending event to obtain the occurrence frequency and duration of the preset events;
when the counting result is matched with the preset counting result, outputting a comparison event;
correspondingly, the determining whether the event sequence matches a preset processor interrupt trigger condition includes:
and judging whether the event sequence is matched with a preset processor interrupt triggering condition or not, wherein the event sequence comprises at least one comparison event.
4. An interrupt controller, comprising: the event source input distributor, the judgment module and the interrupt processor; the judging module is used and comprises: an event source generator, an event combiner and an event output selector;
the event source input distributor is used for receiving an interrupt signal of at least one interrupt source input;
the event source generator is used for determining an event signal according to the interrupt signal;
the event combiner is used for determining an event sequence according to the event signals according to a time sequence, wherein the event sequence represents an event sequence and an event number which are sequentially triggered according to the time sequence; the number of the events is the number of continuous triggers of the same event;
the event output selector is used for judging whether the event sequence is matched with a preset processor interrupt trigger condition, and the preset processor interrupt trigger condition is a preset event sequence preset by a programmer;
and the interrupt processor is used for sending an interrupt signal to the processor if the interrupt trigger condition of the processor is matched with the preset interrupt trigger condition of the processor.
5. The interrupt controller of claim 4, wherein the determining module further comprises an interrupt buffer;
the interrupt buffer is used for buffering the interrupt event sent to the CPU and clearing the interrupt event after the CPU program finishes processing the interrupt.
6. A programming method of an interrupt controller according to claim 4 or 5, comprising:
configuring an event source input distributor, a judgment module and an interrupt handler so that an event source generator determines an event signal according to the interrupt signal; the event combiner determines an event sequence according to the event signals according to the time sequence, wherein the event sequence represents the event sequence and the event number which are triggered sequentially according to the time sequence, and the event number is the number triggered continuously by the same event; and the event output selector judges whether the event sequence is matched with a preset processor interrupt trigger condition, wherein the preset processor interrupt trigger condition is a preset event sequence preset by a programmer.
7. A computer device comprising a memory, a processor, and further comprising an interrupt controller and a computer program stored on the memory and executable on the interrupt controller, the interrupt controller being connected to at least one input device; the interrupt controller is connected with the processor; the interrupt controller implements the interrupt control method as claimed in any one of claims 1 to 3 when executing the program.
8. A storage medium containing computer-executable instructions for performing the interrupt control method of any one of claims 1 to 3 when executed by an interrupt controller in a computer.
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| CN100578480C (en) * | 2007-07-12 | 2010-01-06 | 华为技术有限公司 | Interrupt processing method and device |
| CN101901165B (en) * | 2010-07-26 | 2013-04-10 | 清华大学 | Circuit structure of interruption controller |
| CN104111870B (en) * | 2014-07-08 | 2017-05-24 | 福建星网锐捷网络有限公司 | Interrupt processing device and method |
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