CN103886913A - SRAM (Static Random Access Memory) reading time self-testing circuit and method - Google Patents
SRAM (Static Random Access Memory) reading time self-testing circuit and method Download PDFInfo
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Abstract
The invention relates to an SRAM (Static Random Access Memory) reading time self-testing circuit and method. The self-testing circuit comprises an SRAM to be tested, a two-way selector, a delayed scanning circuit, a latch, a comparer, a counter, a first phase inverter and a second phase inverter; one delayed scanning circuit, one comparer and one counter are additionally arranged to automatically scan the delayed time and rapidly find appropriate delayed time, and the output oscillation period of a ring oscillator can be measured to obtain the SRAM reading time value. Frequent manual operation intervention is avoided during testing, the testing efficiency is high, and besides, with a combination of a fixed delaying unit and a plurality of selectable time delaying units, the layout area is reduced under a condition of ensuring a large measurement range.
Description
[technical field]
The present invention relates to the sequence testing circuit field of static RAM (SRAM), relate in particular to a kind of circuit and method of testing of being carried out to quick self-test the time of reading of SRAM.
[background technology]
SRAM is a kind of common random access memory, is widely used in integrated circuit fields.Reading the time (tACC:AccessTime) is the important time sequence parameter index of weighing SRAM performance, when what its characterized is read operation from clock signal (CLK) rising edge to the effective time delay of output data (Q).
The test of storer at present generally depends on interior self-built test (BIST) circuit.BIST is a kind of design for Measurability technology of widespread use, and it realizes the high speed test of storer automatically by hardware circuit built-in on chip.Although it has realized the robotization of test, it can only prove that SRAM function is normal, and the cycle length of SRAM, (Cycle Time) was not more than test clock cycle.Therefore by traditional BIST circuit can obtain SRAM cycle length parameter but cannot measure it and read the time.
The circuit of the time of reading of another test SRAM as shown in Figure 1, comprise No. two selector switchs (MUX0), multiple different delay circuit (DEL0, DEL1, DEL2,), MUX (MUX1), phase inverter (INV0, INV1) and the latch (DFF) for SRAM output data are sampled.This circuit is by the time of the reading tACC of the delay acquisition SRAM to be measured between test input clock signal clk and clock signal clk _ DEL of latch DFF.Use this circuit to test in two steps: first, the enable signal OSC_EN of No. two selector switch MUX0 is ' 0 ', CLK signal through MUX0, delay circuit one of them, become signal OSC_OUT after MUX1 and INV0, OSC_OUT signal becomes signal CLK_DEL again after INV1.Thereby the CLK_DEL signal that can select artificially different delay circuit generations to have different delayed time by the enable signal DEL_SEL of MUX is sampled to data output Q as the clock signal of latch DFF.By the different delay circuit of continuous trial, until it is can sampled result QX correct to measure latch.Secondly, the enable signal OSC_EN of No. two selector switch MUX0 is ' 1 ', make No. two selector switchs (MUX0), selected delay circuit, MUX (MUX1) and phase inverter (INV0) form a ring oscillator, can obtain signal CLK by the cycle of measurement oscillator signal OSC_OUT is reading the time of SRAM to the time delay of CLK_DEL.The shortcoming of this circuit is: 1. the process of measuring is more loaded down with trivial details, needs tester ceaselessly to change delay circuit and selects signal DEL_SEL until find suitable time delay to make the latch result of latch correct, and whole test process relatively expends time in; 2. in order to obtain larger measurement range and measuring accuracy, must place a large amount of delay circuits, cause the waste of chip area.
[summary of the invention]
The present invention proposes a kind of SRAM and read time self testing circuit and method of testing, to solve the defect of prior art described in background technology.Thereby by finding fast suitable time delay to the autoscan of delay time, and obtain the time value that reads of SRAM oscillation period by the output of measure annular oscillator.
To achieve these goals, the present invention adopts following technical scheme:
A kind of SRAM reads time self testing circuit, comprises SRAM to be measured, Yi Ge No. bis-selector switch MUX, delayed sweep circuit DEL_TRIM, latch DFF, a comparator C OMPARATOR, counter COUNTER, the first phase inverter and second phase inverter;
Described SRAM to be measured is connected to Input Address signal A, enable signal WEN, input chip enable signal CEN, input clock signal CLK, input data D and output data Q are write in input;
Described No. two selector switch MUX are for the switching of test circuit pattern, its Enable Pin is connected to test mode select signal OSC_EN, its input end A is connected to the output terminal of the first phase inverter, its input end B is connected to input clock signal CLK, and its output terminal is connected to the input end I of delayed sweep circuit DEL_TRIM;
In the time that test mode select signal OSC_EN is effective, the input end A of No. two selector switch MUX is connected to its output terminal, otherwise its input end B is connected to its output terminal;
The control end C of described delayed sweep circuit DEL_TRIM is connected to the terminal count output of counter COUNTER, and its output terminal Z is connected to the input end of the first phase inverter, its input end to the time delay between output terminal by the signal deciding that is connected to control end;
The output terminal of described the first phase inverter is connected to the input end A of MUX and the input end of the second phase inverter;
The output terminal of described the second phase inverter is connected to the clock end of latch DFF;
Described latch DFF is responsible for the output data of SRAM to sample, its clock end is connected to the output terminal of the second phase inverter, its input data terminal is connected to the output data terminal Q of SRAM, and its output data terminal QX is connected to the first data terminal of comparator C OMPARATOR;
Described comparator C OMPARATOR carries out the sampled data be responsible for when read operation latch and the output data of SRAM compare and generate a pulse signal in the asynchronous next clock period of comparative result at SRAM, its clock end is connected to input clock signal CLK, its control end is connected to input and writes enable signal WEN, input chip enable signal CEN, test mode select signal OSC_EN, and the second data terminal of comparator C OMPARATOR is connected to the output data terminal Q of SRAM;
The clock end of described counter COUNTER is connected to the output terminal of comparator C OMPARATOR, and its carry end is connected to output carry signal OVERFLOW, and its reset terminal is connected to input reset signal CNT_RST.
The present invention further improves and is: in the time that counter COUNTER overflows, OVERFLOW is effective.
The present invention further improves and is: delayed sweep circuit DEL_TRIM comprises adjustable delay circuit DEL_STEP and constant time lag circuit DEL_FIX; The control end C of delayed sweep circuit DEL_TRIM is connected to the control end C of adjustable delay circuit DEL_STEP, and its input end I is connected to the input end I of constant time lag circuit DEL_FIX, and its output terminal Z is connected to the output terminal Z of adjustable delay circuit DEL_STEP; The output terminal Z of constant time lag circuit DEL_FIX is connected to the input end I of adjustable delay circuit DEL_STEP; Wherein constant time lag circuit DEL_FIX has constant time lag, and adjustable delay circuit DEL_STEP has multiple optional time delays, and they adopt and are connected in series.
The present invention further improves and is:, the time delay tDT=tDTmin+N*tDS of adjustable delay circuit DEL_STEP, wherein tDTmin is time delay minimum value, tDS is tunable steps; The time delay tD0=tDF+tDT of delayed sweep circuit DEL_TRIM, wherein tDF is the time delay of constant time lag circuit DEL_FIX, tDT is the time delay of adjustable delay circuit DEL_STEP; Further, can obtain tD0=tDF+tDTmin+N*tDS, the count value that wherein N is counter, meeting N is natural number and 0≤N≤M; M is total step-length of counter.
The present invention further improves and is: adjustable delay circuit is made up of decoding scheme and time delay chain.
The present invention further improves and is: in the time of the rising edge of input clock signal CLK: if input chip enable signal CEN is ' 0 ', input is write enable signal WEN for ' 1 ' time, SRAM to be measured carries out write operation, and input data D is deposited in the corresponding storage unit of address A; If input chip enable signal input chip enable signal CEN is ' 0 ', input is write enable signal WEN for ' 0 ' time, SRAM to be measured carries out read operation, by the data reading of the corresponding storage unit of address A and export output data Q to, wherein from input clock signal CLK rising edge, to output data Q, the time delay is effectively reading the time of SRAM to be measured.
The present invention further improves and is: counter COUNTER is a counter that is 1 from 0 to M step-length, and M is natural number; Its clock signal is CLK_ERR, and its count output signal is DEL_CODE, and its carry signal is OVERFLOW, and its reset signal is CNT_RST; If CNT_RST is ' 1 ', DEL_CODE is 0; If CNT_RST is ' 0 ',, in the time of CLK_ERR rising edge, counting adds 1.
SRAM reads a method of testing for time self testing circuit, comprises the following steps:
The first step, it is invalid that test mode select signal OSC_EN is set to, and by CNT_RST signal, counter COUNTER is resetted;
Second step, carries out normal read-write operation to SRAM, and in the time of each read operation, test circuit uses the clock signal producing through time delay that the output data Q of SRAM to be measured is sampled and compared, until sampling is correct or counter COUNTER overflows;
The 3rd step, test mode select signal OSC_EN is set to effectively, and No. two selector switch MUX, delayed sweep circuit DEL_TRIM and the first phase inverter form a ring oscillator, by measuring the concussion cycle of this ring oscillator, can be calculated reading the time of SRAM.
With respect to prior art, advantage of the present invention is:
1. save the test duration; The selection of multiple delay units completes automatically by test circuit, thereby only just need to once test and can scan and find suitable time delay size all delay units, has avoided manually-operated intervention, and testing efficiency is high.
2. save arrangement space; Adopt constant time lag unit and there is the array mode of unit of multiple optional time delays, ensureing, under the prerequisite of larger measurement range, compared with prior art, to have saved chip area.
[brief description of the drawings]
Fig. 1 is that the SRAM of prior art reads time test circuit schematic diagram.
Fig. 2 is that SRAM of the present invention reads time test circuit schematic diagram.
Fig. 3 is the schematic diagram of delayed sweep circuit of the present invention.
Fig. 4 is the schematic diagram of adjustable delay circuit of the present invention.
Fig. 5 is the schematic diagram of comparer of the present invention.
Fig. 6 is test waveform schematic diagram of the present invention.
[embodiment]
Below in conjunction with accompanying drawing, embodiments of the present invention are described further.
Referring to Fig. 2, SRAM of the present invention reads time self testing circuit and comprises: comprise SRAM I7 to be measured, No. two selector switch I0, delayed sweep circuit I 1, latch I4, comparer I5, counter I6, the first phase inverter I2 and the second phase inverter I3.
The output terminal of No. two selector switch I0 connects the input port I of delayed sweep circuit I 1, the delivery outlet Z of delayed sweep circuit I 1 connects the input end of the first phase inverter I2, the output terminal of the first phase inverter I2 connects the first input end of the input end He Er road selector switch I0 of the second phase inverter I3, and the output terminal of the second phase inverter I3 connects the clock end of latch I4; The output terminal of latch I4 connects comparer I5; Comparer I5 linkage counter I6; Counter I6 connects the control end C of delayed sweep circuit I 1; The data output end of SRAM I7 connects latch I4 and comparer I5.Input clock signal CLK connects the second input end of No. two selector switch I0; The outer signal of comparer I5 has: enable signal WEN, input chip enable signal CEN, input clock signal CLK and test mode select signal OSC_EN are write in input; Test mode select signal OSC_EN connects the Enable Pin of No. two selector switch I0; The outer signal of counter I6 has: reset signal CNT_RST.
The outer signal that SRAM I7 connects has: enable signal WEN, input chip enable signal CEN, input clock signal CLK, input data D and output data Q are write in Input Address signal A, input.In the time of the rising edge of CLK: if CEN is ' 0 ', WEN while being ' 1 ', SRAM carries out write operation, and D is deposited in the corresponding storage unit of address A; If CEN is ' 0 ', WEN while being ' 0 ', SRAM carries out read operation, and by the data reading of the corresponding storage unit of address A and export Q to, wherein from CLK rising edge to Q, the time delay is effectively reading the time of SRAM.
No. two selector switch I0 are responsible for the switching of test circuit pattern, its Enable Pin is connected to from external test mode select signal OSC_EN, its input end A is connected to the output terminal of the first phase inverter I2, its input end B is connected to clock signal clk, and its output terminal is connected to the input end I of delayed sweep circuit I 1.
The output terminal Z of delayed sweep circuit I 1 is connected to the input end of the first phase inverter I2, and its control end C is connected to the count output signal DEL_CODE of counter I6.DEL_CODE signal deciding the input end of delayed sweep circuit I 1 to the time delay between output terminal.
The first phase inverter I2 is output as OSC_EN signal, and is connected to the input end A of No. two selector switch I0 and the input end of the second phase inverter I3.The second phase inverter I3 is output as clock signal clk _ DEL, and is connected to the clock end of latch I4.
The input data terminal of latch I4 is connected to the output data terminal of SRAM I7, and its output data terminal is connected to the first data terminal of comparer I5.In the time of the rising edge of CLK_DEL, latch I4 samples to the output data Q of SRAM I7, and sampled result is QX.
The clock end of comparer I5 is connected to CLK, and its control end is connected to WEN, CEN, OSC_EN, and its first data terminal is connected to QX, and its second data terminal is connected to Q.In the time that SRAM carries out read operation, the output data Q that comparer I5 is responsible for sampled result QX to latch I4 and SRAM compares and generates a pulse signal CLK_ERR in the next clock period of asynchronous this read operation of comparative result, as the comparative result mark of this read operation.
Counter I6 is a counter that is 1 from 0 to M (M is natural number) step-length, and its clock signal is CLK_ERR, and its count output signal is DEL_CODE, and its carry signal is OVERFLOW, and its reset signal is CNT_RST.If CNT_RST is ' 1 ', DEL_CODE is 0; If CNT_RST is ' 0 ',, in the time of CLK_ERR rising edge, counting adds 1.
Based on above-described test circuit, a kind of SRAM of the present invention reads time test method and comprises the following steps:
The first step, is set to ' 0 ' by OSC_EN signal, and CNT_RST signal is set to ' 1 '.
In the time that OSC_EN is ' 0 ', the input end B of No. two selector switch I0 is connected to its output terminal.CLK signal forms a clock signal clk _ DEL through time delay after the time delay of No. two selector switch I0, delayed sweep circuit I 1, the first phase inverter I2 and the second phase inverter I3.
In the time that CNT_RST is ' 1 ', counter I6 resets, and DEL_CODE is that 0, OVERFLOW is ' 0 '.
Second step, is set to ' 0 ' by OSC_EN signal, and CNT_RST signal is set to ' 0 '.
Now can carry out normal read-write operation to SRAM, in the time of each read operation, latch I4 uses the CLK_DEL signal producing through time delay as clock, the output data Q of SRAM to be sampled.
Meanwhile comparer I5 can compare sampled result QX and Q, once the different comparer I5 of comparative result, the next clock period in this read operation is generated to a pulse signal CLK_ERR.
In the time that CNT_RST is ' 0 ', counter I6 can count.Once the rising edge of CLK_ERR signal arrives, count value DEL_CODE adds 1, and along with the increase of count value, the time delay of delayed sweep circuit I 1 will progressively increase, thereby realize the autoscan of time delay.Scanning result has two: 1. at count value DEL_CODE=N, (N is natural number, and 0≤N≤M) time, the comparative result CLK_ERR of comparer remains ' 0 ', counter I6 does not overflow and stops adding up, the delay of this state from CLK to CLK_DEL is exactly find the most approaching of test circuit and the time delay that is not less than the time of reading of SRAM I7, and proceeds the measurement of the 3rd step; 2. counter I6 overflows, and OVERFLOW signal is ' 1 ', and in this state, comparer I5 will quit work, and represents that the time of reading of SRAM has exceeded the maximal value of measurement range, test end.
The 3rd step, is set to ' 1 ' by OSC_EN signal, and CNT_RST signal is set to ' 0 '.
In the time that OSC_EN is ' 1 ', the input end A of No. two selector switch I0 is connected to its output terminal, and No. two selector switch I0, delayed sweep circuit I 1 and the first phase inverter I2 just can form a ring oscillator, and its output signal is OSC_OUT.By measuring the concussion cycle tOSC of OSC_OUT signal, can be calculated the time of the reading tACC=0.5*tOSC of SRAM.
Referring to Fig. 3, Fig. 3 is the schematic diagram of delayed sweep circuit of the present invention.Delayed sweep circuit I 1 comprises adjustable delay circuit DEL_STEP I10 and constant time lag circuit DEL_FIX I11.The control end C of delayed sweep circuit I 1 is connected to the control end C of adjustable delay circuit I10, and its input end I is connected to the input end I of constant time lag circuit I 11, and its output terminal Z is connected to the output terminal Z of adjustable delay circuit I10.The output terminal Z of constant time lag circuit I 11 is connected to the input end I of adjustable delay circuit I10.Wherein DEL_FIX I1 has constant time lag, and DEL_STEP has multiple optional time delays, and they adopt the mode being connected in series, and it doesn't matter for sequencing.
The time delay tDT=tDTmin+N*tDS of adjustable delay circuit I0, wherein tDTmin is time delay minimum value, tDS is tunable steps.The time delay tD0=tDF+tDT of delayed sweep circuit I 1, wherein tDF is the time delay of constant time lag circuit I 11, tDT is the time delay of adjustable delay circuit I10.Further, can obtain tD0=tDF+tDTmin+N*tDS, the count value that wherein N is counter, meeting N is natural number and 0≤N≤M.Therefore the coverage of the time delay tDT of adjustable delay circuit I0 is [tDF+tDTmin, tDF+tDTmin+M*tDS], and minimum precision is tDS.The SRAM that must ensure expection in the time that test circuit designs reads in the coverage that time tACC can be included in tDT and leaves surplus.
Referring to Fig. 4, Fig. 4 is the schematic diagram of adjustable delay circuit of the present invention.Adjustable delay circuit I10 is made up of decoding scheme and time delay chain.In this example, the control end of adjustable delay circuit is 2 inputs, respectively C<1> and C<0>, the adjustment (i.e. 0≤N≤M=3) of 4 kinds of different delayed time can be realized, the more control end of high-bit width can be selected in order to improve measurement coverage and measuring accuracy.In fact the implementation of adjustable delay circuit has multiplely, has just enumerated wherein a kind of here.
Decoding scheme is the code translator of 2 to 4, comprises phase inverter (I100, I101) and rejection gate (I102, I103, I104, I105).Phase inverter I100 is input as C<0>, is output as C0N signal and is connected to an input end of rejection gate I102 and I103.Phase inverter I101 is input as C<1>, is output as C1N signal and is connected to an input end of rejection gate I102 and I104.C<0> is connected to an input end of rejection gate I104 and I105.C<1> is connected to an input end of rejection gate I103 and I105.Rejection gate I102, I103, the output signal of I104 and I105 is respectively DEL_EN_3, DEL_EN_2, DEL_EN_1 and DEL_EN_0 are also connected to He Er road selector switch I107, I109, the Enable Pin of I111 and I113.According to input C<1> and C<0> signal, the output signal DEL_EN_3 of code translator, DEL_EN_2, in DEL_EN_1 and DEL_EN_0, only has one for ' 1 ', all the other are all ' 0 ', select 1 function thereby can realize 4.
Time delay chain comprises unit delay unit (I106, I108, I110, I112) He Er road selector switch (I107, I109, I111, I113), and the above delay unit He Er of unit road selector switch is corresponding one by one.The input end B of all No. two selector switchs is connected to the input I of adjustable delay circuit I10.The input end of the delay unit I106 of unit is connected to the input I of adjustable delay circuit I10, and its output terminal is connected to the input end A of No. two selector switch I107.The input end of the delay unit I108 of unit is connected to the output terminal of No. two selector switch I107, and its output terminal is connected to the input end A of No. two selector switch I109.The input end of the delay unit I110 of unit is connected to the output terminal of No. two selector switch I109, and its output terminal is connected to the input end A of No. two selector switch I111.The input end of the delay unit I112 of unit is connected to the output terminal of No. two selector switch I111, and its output terminal is connected to the input end A of No. two selector switch I113.The output terminal of No. two selector switch I113 is exactly the output Z of adjustable delay circuit I10.
When the Enable Pin of Dang Er road selector switch is ' 1 ', its input end B is connected to output terminal; Otherwise its input end A is connected to output terminal.Therefore that according to input control signal, decoding obtains and the Enable Pin corresponding Er of delay unit of unit road selector switch are for ' 1 ' time, and all units delay unit after this unit is by the time delay chain entering from input end I to output terminal Z.Be ' 0 ' such as working as C<1>, when C<0> is ' 1 ', it is ' 1 ' that decoding obtains DEL_EN_1, and time delay chain becomes No. two selector switch I111, delay unit I112 He Er road, unit selector switch I113.
Referring to Fig. 5, Fig. 5 is the schematic diagram of comparer of the present invention.Comparer comprise XOR gate I50 or door I52, Sheffer stroke gate I51, three input rejection gate I53, latch I54 and with door I55.Its input port has input clock CLK, two data Q and QX, SRAM control signal WEN and CEN, test circuit control signal OSC_EN and OVERFLOW, and its output port is comparative result CLK_ERR.
The input end of XOR gate I50 is connected respectively to input data Q and QX.Or the input end of door I52 is connected to respectively test circuit control signal OSC_EN and OVERFLOW.The input end of Sheffer stroke gate I51 connects respectively SRAM control signal WEN and CEN.The input of three input rejection gate I53 is connected to respectively I50, the output terminal of I51 and I52.The data terminal D of latch I54 is connected to the output terminal of I53, and its clock end CK is connected to CLK signal.Be connected to respectively output terminal Q and the CLK signal of I54 with the input end of door I55, its output terminal is CLK_ERR signal.
Only have when CEN be that ' 1 ', WEN is that ' 1 ', OSC_EN is ' 0 ', OVERFLOW while being ' 0 ', comparer can compare inputting data Q and QX, if Q is different with QX, EN is ' 1 ', otherwise EN is ' 0 '.And in the time of the rising edge of CLK, if EN for ' 1 ' the output signal of latch I54 will make the conducting with door I55, time clock of the upper appearance of CLK_ERR for ' 1 '.
Shown in Fig. 6 (a) and Fig. 6 (b), it is test waveform schematic diagram of the present invention.Wherein Fig. 6 (a) is test circuit autoscan and finds the process schematic diagram that reads the suitable time delay of time tACC with SRAM, and Fig. 6 (b) is the process schematic diagram of measuring tOSC oscillation period after formation oscillator.
In Fig. 6 (a), OSC_EN is ' 0 '.First, send read command READ (CEN=0, WEN=1) to test circuit, test circuit will carry out read operation sense data Q one time to SRAM I7.Now DEL_CODE=N-1, after the time delay of tDF+tDTmin+ (N-1) * tDS, latch I4 samples and obtains QX sense data.Then, send comparison command COMPARE (CEN=1, WEN=1) to test circuit, test circuit compares Q and QX.If comparative result is FAIL, i.e. data difference, pulse signal of the upper appearance of comparative result CLK_ERR, this signal rising edge makes counter I6 counting add 1, now DEL_CODE=N.Then constantly repeat above two orders until comparative result is PASS, CLK_ERR remains ' 0 ', and counting stops adding up, and represents that data Q is identical with QX, been scanned.In figure, for simplicity, suppose that comparative result is PASS in the time of DEL_CODE=N, the time of the reading tACC of SRAM is about tDF+tDTmin+N*tDS.
In Fig. 6 (b), OSC_EN is ' 1 '.When test circuit completes after scanning, OSC_EN is set to ' 1 '.The input end A of No. two selector switch I0 is connected to its output terminal, and No. two selector switch I0, delayed sweep circuit I 1 and the first phase inverter I2 just can form a ring oscillator, and its output signal is OSC_OUT.By measuring the concussion cycle tOSC of OSC_OUT signal, can be calculated the time of the reading tACC=0.5*tOSC of SRAM.
Claims (8)
1. a SRAM reads time self testing circuit, it is characterized in that, comprise SRAM to be measured, Yi Ge No. bis-selector switch MUX, delayed sweep circuit DEL_TRIM, latch DFF, a comparator C OMPARATOR, counter COUNTER, the first phase inverter (I2) and second phase inverter (I3);
Described SRAM to be measured is connected to Input Address signal A, enable signal WEN, input chip enable signal CEN, input clock signal CLK, input data D and output data Q are write in input;
Described No. two selector switch MUX are for the switching of test circuit pattern, its Enable Pin is connected to test mode select signal OSC_EN, its input end A is connected to the output terminal of the first phase inverter, its input end B is connected to input clock signal CLK, and its output terminal is connected to the input end I of delayed sweep circuit DEL_TRIM;
In the time that test mode select signal OSC_EN is effective, the input end A of No. two selector switch MUX is connected to its output terminal, otherwise its input end B is connected to its output terminal;
The control end C of described delayed sweep circuit DEL_TRIM is connected to the terminal count output of counter COUNTER, and its output terminal Z is connected to the input end of the first phase inverter, its input end to the time delay between output terminal by the signal deciding that is connected to control end;
The output terminal of described the first phase inverter is connected to the input end A of MUX and the input end of the second phase inverter;
The output terminal of described the second phase inverter is connected to the clock end of latch DFF;
Described latch DFF is responsible for the output data of SRAM to sample, its clock end is connected to the output terminal of the second phase inverter, its input data terminal is connected to the output data terminal Q of SRAM, and its output data terminal QX is connected to the first data terminal of comparator C OMPARATOR;
Described comparator C OMPARATOR carries out the sampled data be responsible for when read operation latch and the output data of SRAM compare and generate a pulse signal in the asynchronous next clock period of comparative result at SRAM, its clock end is connected to input clock signal CLK, its control end is connected to input and writes enable signal WEN, input chip enable signal CEN, test mode select signal OSC_EN, and the second data terminal of comparator C OMPARATOR is connected to the output data terminal Q of SRAM;
The clock end of described counter COUNTER is connected to the output terminal of comparator C OMPARATOR, and its carry end is connected to output carry signal OVERFLOW, and its reset terminal is connected to input reset signal CNT_RST.
2. a kind of SRAM according to claim 1 reads time self testing circuit, it is characterized in that, in the time that counter COUNTER overflows, OVERFLOW is effective.
3. a kind of SRAM according to claim 1 reads time self testing circuit, it is characterized in that, delayed sweep circuit DEL_TRIM comprises adjustable delay circuit DEL_STEP and constant time lag circuit DEL_FIX; The control end C of delayed sweep circuit DEL_TRIM is connected to the control end C of adjustable delay circuit DEL_STEP, and its input end I is connected to the input end I of constant time lag circuit DEL_FIX, and its output terminal Z is connected to the output terminal Z of adjustable delay circuit DEL_STEP; The output terminal Z of constant time lag circuit DEL_FIX is connected to the input end I of adjustable delay circuit DEL_STEP; Wherein constant time lag circuit DEL_FIX has constant time lag, and adjustable delay circuit DEL_STEP has multiple optional time delays, and they adopt and are connected in series.
4. a kind of SRAM according to claim 3 reads time self testing circuit, it is characterized in that, and the time delay tDT=tDTmin+N*tDS of adjustable delay circuit DEL_STEP, wherein tDTmin is time delay minimum value, tDS is tunable steps; The time delay tD0=tDF+tDT of delayed sweep circuit DEL_TRIM, wherein tDF is the time delay of constant time lag circuit DEL_FIX, tDT is the time delay of adjustable delay circuit DEL_STEP; Further, can obtain tD0=tDF+tDTmin+N*tDS, the count value that wherein N is counter, meeting N is natural number and 0≤N≤M; M is total step-length of counter.
5. a kind of SRAM according to claim 1 reads time self testing circuit, it is characterized in that, adjustable delay circuit is made up of decoding scheme and time delay chain.
6. a kind of SRAM according to claim 1 reads time self testing circuit, it is characterized in that, in the time of the rising edge of input clock signal CLK: if input chip enable signal CEN is ' 0 ', input is write enable signal WEN for ' 1 ' time, SRAM to be measured carries out write operation, and input data D is deposited in the corresponding storage unit of address A; If input chip enable signal input chip enable signal CEN is ' 0 ', input is write enable signal WEN for ' 0 ' time, SRAM to be measured carries out read operation, by the data reading of the corresponding storage unit of address A and export output data Q to, wherein from input clock signal CLK rising edge, to output data Q, the time delay is effectively reading the time of SRAM to be measured.
7. a kind of SRAM according to claim 1 reads time self testing circuit, it is characterized in that, counter COUNTER is a counter that is 1 from 0 to M step-length, and M is natural number; Its clock signal is CLK_ERR, and its count output signal is DEL_CODE, and its carry signal is OVERFLOW, and its reset signal is CNT_RST; If CNT_RST is ' 1 ', DEL_CODE is 0; If CNT_RST is ' 0 ',, in the time of CLK_ERR rising edge, counting adds 1.
8. a kind of SRAM described in claim 1 to 7 reads the method for testing of time self testing circuit, it is characterized in that, comprises the following steps:
The first step, it is invalid that test mode select signal OSC_EN is set to, and by CNT_RST signal, counter COUNTER is resetted;
Second step, carries out normal read-write operation to SRAM, and in the time of each read operation, test circuit uses the clock signal producing through time delay that the output data Q of SRAM to be measured is sampled and compared, until sampling is correct or counter COUNTER overflows;
The 3rd step, test mode select signal OSC_EN is set to effectively, and No. two selector switch MUX, delayed sweep circuit DEL_TRIM and the first phase inverter form a ring oscillator, by measuring the concussion cycle of this ring oscillator, can be calculated reading the time of SRAM.
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