CN103325422A - SRAM timing sequence test circuit and test method - Google Patents
SRAM timing sequence test circuit and test method Download PDFInfo
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- CN103325422A CN103325422A CN2013103031666A CN201310303166A CN103325422A CN 103325422 A CN103325422 A CN 103325422A CN 2013103031666 A CN2013103031666 A CN 2013103031666A CN 201310303166 A CN201310303166 A CN 201310303166A CN 103325422 A CN103325422 A CN 103325422A
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Abstract
The invention discloses a SRAM timing sequence test circuit and a test method. The test circuit comprises a SRAM memory cell and a test circuit unit. The test circuit unit comprises a first mode switching circuit connected with the SRAM memory cell, an edge signal trigger circuit connected with the first mode switching circuit and a second mode switching circuit connected with the edge signal trigger circuit. The first mode switching circuit has a first enable pin. The second mode switching circuit has a second enable pin. According to signal control difference of the first and second enable pins, a first annular oscillating circuit and a second annular oscillating circuit are respectively formed in the test circuit; and output oscillation periods of the two annular oscillating circuits are measured so as to accurately obtain time value of reading data of the SRAM memory cell. The test circuit provided by the invention can be completed by an automatic wiring tool, and has advantages of small measuring error, high precision and simple measurement.
Description
Technical field
The present invention relates to the element circuit field of static RAM (SRAM), especially relate to a kind of sequence testing circuit and method of testing that the sequential index parameter of SRAM is tested.
Background technology
Enter deep-submicron after the epoch in semiconductor technology, chip can be operated under the frequency of hundreds of MHz or upper GHz, and the frequency of operation of the SRAM that it is inner might be higher.But in chip testing, because the impact of packaging and testing board, the clock signal that external testing provides often can only reach tens or the frequency of at the most 100 MHz.
Under aforementioned background, general a large amount of built-in self-test (BIST) circuit that depend on of the now test of chip, the advantage of BIST circuit is not only the robotization of test, and because of the test access that does not need through the outside, so can realize high speed test.The BIST circuit of SRAM is called again memory built in self test of sram (MBIST) circuit, and its inside comprises test signal and produces circuit and SRAM output judgement comparator circuit.The MBIST circuit is tested SRAM under the control of chip internal high-frequency clock, if test is correct, prove that not only the SRAM function is correct, represent that also the SRAM clock period can be greater than test clock cycle, like this, the external world can obtain the test data of SRAM clock period.Yet except SRAM the clock period, it also is the important sequential index parameter of SRAM that the SRAM data read the time (being called for short Tcq), and by traditional MBIST circuit, this parameter can't measure.
Now measure the general employing of the Tcq circuit shown in Figure 1 of SRAM, comprise two road gate IM0, have delay circuit ID0, multi-channel gating device IM1, the first phase inverter I0 and the second phase inverter I1 of a plurality of delay units and the D-latch ID1 that is used for sampling, the clock synchronous input signal CK of SRAM and read data output signal DO are connected respectively to the input end of two road gate IM0 and D-latch ID1.This circuit is by the time-delay between the clock signal C K_DFF of measuring-signal CK and D-latch ID1, thereby the data that measure SRAM read time T cq.In conjunction with shown in Figure 2, concrete measuring principle is: when the enable signal OSCE of two road gates is logical zero, signal CK is through two road gate IM0, delay circuit ID0, become signal OSC_OUT behind multi-channel gating device IM1 and the first phase inverter I0, behind the phase-modulation of the second phase inverter, be converted to again the clock signal C K_DFF of D-latch, enable signal Delay_Sel by multi-channel gating device selects different delay units, the waveform that circuit produces during measurement as shown in Figure 2, be the SRAM reading out data time T cq that will measure from the time that the rising edge of measuring-signal CK plays output signal DO output data among the figure, behind delay unit of every selection, enable signal OSCE is set to logical one, so that two road gate IM0, selected delay unit, multi-channel gating device IM1 and the first phase inverter I0 form an annular oscillation circuit, the annular oscillation circuit output waveform as shown in Figure 3, measure the oscillation frequency of the output signal OSC_OUT of annular oscillation circuit, obtain signal CK to the time-delay of signal CK_DFF, measure until D-latch ID1 can be latched into correct data, the time-delay that measure this moment namely equals the Tcq of SRAM.
But the shortcoming that this circuit exists is: (1) relates to more manual layout design, expend time in more, efficient is lower, such as the precision for guaranteeing that Tcq measures, delay circuit ID0 needs manual finishing, otherwise because the circuit layout that automatic placement and routing's instrument generates postpones to have very large uncertainty, the precision that causes Tcq to measure is uncontrollable; (2) precision of Tcq measurement is lower, as measure the Tcq failure by delay cell Delay1, and measure the Tcq success by delay cell Delay2, just between the time delay of time delay of Delay1 and Delay2, the measuring error minimum is the poor of two time delays to Tcq so; (3) process of measurement Tcq is comparatively loaded down with trivial details, need to constantly adjust Delay_Sel until the correct output data that latch SRAM.And every time-delay access all will form separately annular oscillation circuit and measure its frequency to obtain the time delay of each, when the higher measuring accuracy of needs, often place a large amount of time-delay access, to guarantee that time-delay access had both covered larger reference time delay, cover again time-delay dot interlace as much as possible.
Summary of the invention
The object of the invention is to overcome the defective of prior art, a kind of SRAM sequence testing circuit and method of testing are provided, by measuring the output oscillation period of two annular oscillation circuits in the test circuit, accurately obtain the time value of SRAM storage unit reading out data.
For achieving the above object, the present invention proposes following technical scheme: a kind of SRAM sequence testing circuit, comprise SRAM storage unit and test circuit unit, described SRAM storage unit comprises address signal input end, clock signal input terminal and reading data signal output terminal, and described test circuit unit comprises:
The first mode commutation circuit, input end links to each other with described reading data signal output terminal;
The edge signal trigger circuit, input end links to each other with the output terminal of described first mode commutation circuit;
The second pattern commutation circuit, input end links to each other with the output terminal of described edge signal trigger circuit, output terminal links to each other with described clock signal input terminal;
Described first mode commutation circuit has the first Enable Pin, and described the second pattern commutation circuit has the second Enable Pin.
Preferably, when the first Enable Pin control first mode commutation circuit access reading data signal output terminal, when the second Enable Pin was controlled the second pattern commutation circuit access edge signal trigger circuit output terminal, described SRAM storage unit, first mode commutation circuit, edge signal trigger circuit and the second pattern commutation circuit formed the first annular oscillation circuit;
When the first Enable Pin control first mode commutation circuit accessed the output terminal of the second pattern commutation circuit, described first mode commutation circuit, edge signal trigger circuit and the second pattern commutation circuit formed the second annular oscillation circuit.
Described first mode commutation circuit adopts two road gates, wherein an input end links to each other with the reading data signal output terminal of described SRAM by the first Sheffer stroke gate, another input end links to each other with the output terminal of described the second pattern commutation circuit, and output terminal links to each other with the input end of described edge signal trigger circuit by the first phase inverter.
Described edge signal trigger circuit comprise delay unit, the second phase inverter, the second Sheffer stroke gate and same or door, described delay unit input end links to each other with described the first inverter output, described the second phase inverter input end links to each other with described delay unit output terminal, wherein an input end links to each other with the output terminal of described the second phase inverter described the second Sheffer stroke gate, another input end links to each other with described the first Enable Pin, described with or door wherein an input end links to each other with the output terminal of described the second Sheffer stroke gate, another input end links to each other with described delay unit input end.
Described the second pattern commutation circuit adopts two road gates, wherein an input end through the 3rd phase inverter with described with or the output terminal of door links to each other, another input end is inputted external testing input clock signal, output terminal links to each other with the clock signal input terminal of described SRAM.
Described test circuit unit also comprises:
Address production electric circuit, input end links to each other with described edge signal trigger circuit output terminal;
The three-mode commutation circuit, input end links to each other with described address production electric circuit output terminal, output terminal links to each other with described address signal input end.
Described address production electric circuit adopts clock synchronization circuit, and its Enable Pin is the second Enable Pin.
Described three-mode commutation circuit adopts two road gates, another input termination external address input signal, and its Enable Pin is the second Enable Pin.
Another object of the present invention also is the sequence testing circuit based on SRAM, discloses a kind of SRAM time sequence test method, may further comprise the steps:
Step 1, the first Enable Pin control first mode commutation circuit access reading data signal output terminal, the second Enable Pin is controlled the second pattern commutation circuit access edge signal trigger circuit output terminal, by the output oscillation period of described the first annular oscillation circuit of external testing apparatus measures;
Step 2, the first Enable Pin control first mode commutation circuit accesses the output terminal of the second pattern commutation circuit, by the output oscillation period of described the second annular oscillation circuit of external testing apparatus measures.
Preferably, before measuring output oscillation period of the first annular oscillation circuit, trigger the SRAM storage unit by external schema and carry out primary address and read, the address value that reads remains on described reading data signal output terminal.
Comprise by the external schema triggering: the second Enable Pin is controlled respectively the second pattern commutation circuit input external testing input clock signal, three-mode commutation circuit input external address input signal, and described external testing input clock signal triggers the SRAM storage unit outside address input signal is read.
Beneficial effect of the present invention is: the measured value of (1) Tcq is obtained by output value oscillation period of two annular oscillation circuits, and the circuit layout form can be finished by auto-placement tool fully on the not impact of measurement of Tcq, and efficient is high; (2) error is little, measures accurately high; (3) measure simple, easily realization, compared with prior art, saved the time that a large amount of delay circuits selections are adjusted.
Description of drawings
Fig. 1 is the SRAM sequence testing circuit principle schematic of prior art;
Fig. 2 is the waveform schematic diagram of Fig. 1 circuit when carrying out the Tcq measurement;
Fig. 3 is the output waveform schematic diagram of the annular oscillation circuit that forms among Fig. 1;
Fig. 4 is the principle schematic of SRAM sequence testing circuit of the present invention;
Fig. 5 is the waveform schematic diagram of Fig. 4 circuit when carrying out the Tcq measurement;
Fig. 6 is the output waveform schematic diagram of the second annular oscillation circuit of forming in Fig. 4 circuit;
Fig. 7 is the schematic flow sheet of SRAM time sequence test method of the present invention.
Embodiment
Below in conjunction with accompanying drawing of the present invention, the technical scheme of the embodiment of the invention is carried out clear, complete description.
Disclosed a kind of SRAM sequence testing circuit, by forming two annular oscillation circuits, measure respectively the output oscillation period of two annular oscillation circuits, thereby accurately obtain the time value of SRAM storage unit reading out data, the measuring accuracy that exists in the existing Tcq measuring method is low, process is loaded down with trivial details, it is many to expend time in, inefficient problem to overcome.
As shown in Figure 4, disclosed a kind of SRAM sequence testing circuit comprises: SRAM storage unit I10, first mode commutation circuit I5, the edge signal trigger circuit, the second pattern commutation circuit I8, address production electric circuit I9 and three-mode commutation circuit I11, described SRAM storage unit I10 is the effective clock synchronization circuit of rising edge clock, comprise signal input part and signal output part, described signal input part comprises clock signal input terminal, write the enable signal input end, the address signal input end, the write data signal input end, described clock signal input terminal is used for input clock synchronizing signal CK, and the rising edge of signal CK triggers the operation that SRAM storage unit I10 once reads or writes; The described enable signal input end of writing is effectively write enable signal WEB for input low level, and the definition high level is logical one, and low level is logical zero, namely when the signal WEB of input is logical zero, triggers SRAM storage unit I10 and carries out write operation; Described address signal input end links to each other with the output terminal of described three-mode commutation circuit I11, is used for the address date that input is produced by external schema or address production electric circuit I9; The write data signal input part is used for after SRAM storage unit I10 is triggered by signal WEB, and data input signal D1 is write in input, and data are write among the SRAM storage unit I10; The signal output part of described SRAM storage unit I10 comprises the reading data signal output terminal, is used for output read data output signal DO, and the data that SRAM storage unit I10 reads are exported.
In preferred embodiment of the present invention, described first mode commutation circuit I5 selects has two input ends, two road gates of output terminal and the first Enable Pin, one of them input end links to each other with the reading data signal output terminal of described SRAM storage unit I10 by the first Sheffer stroke gate I6, another input end links to each other with the output terminal of described the second pattern commutation circuit I8, described the first Enable Pin is used for incoming control signal OSCE, be used for the output of control first mode commutation circuit I5, namely when signal OSCE was logical zero, first mode commutation circuit I5 exported the logical inverse of read data output signal DO; When signal OSCE was logical one, first mode commutation circuit I5 output signal was then selected the output signal of the second pattern commutation circuit I8.
In preferred embodiment of the present invention, described edge signal trigger circuit comprise delay unit I3, the second phase inverter I2, the second Sheffer stroke gate I1 and same or door I0, the output terminal of described first mode commutation circuit I5 through the first phase inverter I4 respectively with the input end of described delay unit I3, a wherein input end same or door I0 links to each other, the input signal that defines described edge signal trigger circuit is NODEO, be the output signal of first mode commutation circuit I5 behind the first phase inverter I4, the output terminal of described delay unit I3 links to each other with the wherein input end of described the second Sheffer stroke gate I1 through the second phase inverter I2, described another input end incoming control signal of the second Sheffer stroke gate I1 OSCE, it is the control signal of described edge signal trigger circuit, when signal OSCE is logical zero, described edge signal trigger circuit respond to the logic variation of input signal NODEO, namely if signal NODEO occurs once from the logical one to the logical zero or logical zero to the saltus step of logical one, then low pulse that logic is " 0 " of edge signal trigger circuit output, pulse width is by determining the time delay of delay unit I3; When signal OSCE is logical one, described delay unit I3, the second phase inverter I2 and the second Sheffer stroke gate I1 locking, the output signal of described edge signal trigger circuit will be always the logical inverse of input signal NODE0.Described another input end same or door I0 links to each other with the output terminal of described the second Sheffer stroke gate I1.
Certainly, the edge signal trigger circuit among the present invention can be replaced by other forms of circuit, as long as replacement circuit can be finished the identical work of the edge signal trigger circuit among the present invention.
In preferred embodiment of the present invention, described the second pattern commutation circuit I8 selects equally has two input ends, two road gates of output terminal and the second Enable Pin, be used for selecting the clock input signal of output SRAM, described output terminal same or door I0 links to each other with the wherein input end of described the second pattern commutation circuit I8 through the 3rd phase inverter I7, another input end access external testing input clock signal CK_EXT of described the second pattern commutation circuit I8, output terminal links to each other with the clock signal input terminal of described SRAM, Enable Pin access signal MD_EX, be used for the clock input signal of SRAM is selected, namely when signal MD_EX was logical zero, the clock signal input terminal of SRAM was inputted logical inverse same or door I0 output signal; When signal MD_EX is logical one, the clock signal input terminal of SRAM input external testing input clock signal CK_EXT.Signal MD_EX also is the enable signal of address production electric circuit I9 and three-mode commutation circuit I11 simultaneously, and accesses respectively both Enable Pins.
In preferred embodiment of the present invention, described address production electric circuit I9 selects the effective clock synchronization circuit of rising edge, its input end links to each other with described output terminal same or door I0, output terminal links to each other with a wherein input end of described three-mode commutation circuit, MD_EX controls by signal, and triggers OPADD by the rising edge of the output signal OSC_OUT of edge signal trigger circuit.Certainly, address production electric circuit I9 among the present invention can be replaced by any form, the address production electric circuit that satisfies arbitrary address width S RAM, as long as SRAM reading out data measurement of time of the present invention can be realized in the address that address production electric circuit produces, namely can be the present invention and adopt.
In preferred embodiment of the present invention, described three-mode commutation circuit I11 select equally have two input ends, two road gates of output terminal and the 3rd Enable Pin, its another input end access external address input signal A_EXT, output terminal links to each other with the address signal input end of described SRAM.When enable signal MD_EX was logical zero, the input of the address signal input end of described SRAM was by the address signal of address production electric circuit I9 output; When the second enable signal MD_EX is logical one, the address signal input end of described SRAM input external address input signal A_EXT.
When the second enable signal MD_EX and the first enable signal OSCE were logical zero, described SRAM storage unit I10, first mode commutation circuit I5, edge signal trigger circuit and the second pattern commutation circuit I8 formed the first annular oscillation circuit; When described the first enable signal OSCE is logical one, described first mode commutation circuit I5, the first phase inverter I4, with or door I0, the 3rd phase inverter I7 and the second pattern commutation circuit I8 form the second annular oscillation circuit.
The present invention is based on the SRAM sequence testing circuit, also disclosed a kind of SRAM time sequence test method, be used for measuring the reading out data time T cq of SRAM.Here only comprise two address location AddrH and AddrL as example take SRAM, describe the method for testing of SRAM sequence testing circuit, in conjunction with shown in Figure 7, may further comprise the steps:
The first step is carried out primary address by external schema triggering SRAM storage unit and is read, and the address value that reads remains on the read data output terminal of described SRAM.
To write enable signal WEB and be set to logical zero, and trigger the SRAM storage unit to the address location data writing, AddrH writes logical one at address location, and address location AddrL writes logical zero.When signal MD_EX is set to logical one, control the second pattern commutation circuit I8 and three-mode commutation circuit I11 and export respectively external timing signal CK_EXT and external address input signal A_EXT, the rising edge of external timing signal CK_EXT triggers the SRAM storage unit data among the address location AddrL is read one time, the output data of SRAM storage unit I10 are logical zero like this, by the characteristic of SRAM output interface as can be known, the data that once read before its output signal DO will keep before the SRAM read operation occurs next time.
Second step, the first Enable Pin control first mode commutation circuit access reading data signal output terminal, the second Enable Pin is controlled the second pattern commutation circuit access edge signal trigger circuit output terminal, by the output oscillation period of described the first annular oscillation circuit of external testing apparatus measures.
To write enable signal WEB and be set to logical one, when the second Enable Pin signal MD_EX is converted to logical zero by logical one, address production electric circuit I9 OPADD AddrH, therefore the address signal input end A of SRAM is with receiver address AddrH, the logic transition of the second Enable Pin MD_EX causes input signal NODEO and occurs by the transformation of logical one to logical zero, after the edge signal trigger circuit are sensed the logic variation of input end signal NODEO, exporting a logic at signal OSC_OUT is " 0 " low pulse, the negative edge of low pulse is behind the 3rd phase inverter I7 and the second pattern commutation circuit I8, the clock signal C K that triggers SRAM jumps to logical one by logical zero, trigger SRAM to the read operation of address AddrH, so SRAM output signal DO will become logical one by logical zero; Rising edge in low pulse causes that the OPADD of address production electric circuit I9 changes, and namely is changed to address AddrL by address AddrH.
The variation that the output signal of SRAM becomes logical one by logical zero can cause the variation of signal NODE0 simultaneously, signal NODE0 is as the input signal of edge signal trigger circuit, its variation and then cause that the edge signal trigger circuit export a low pulse again on signal OSC_OUT, current low pulse reverts to AddrH again with the output of address production electric circuit I9 after triggering SRAM is to the read operation of AddrL, therefore, as long as the second enable signal MD_EX is maintained " 0 ", the first enable signal OSCE is maintained " 1 ", SRAM just will constantly read the data among address location AddrH and the address location AddrL repeatedly, produces and just have at set intervals a low pulse on signal OSC_OUT.
Shown in Fig. 5 oscillogram, the oscillogram that when measuring Tcq, produces for test circuit, from the last rising edge of clock signal C K to clock period that a rear rising edge is clock signal C K, be SRAM storage unit reading the time address input data, be defined as Tx, but this time has been passed through first mode commutation circuit I5 successively, the first phase inverter, with or the door I0, the delay of the 3rd phase inverter I7 and the second pattern commutation circuit I8, so want to obtain accurate SRAM reading out data time T cq, just need to deduct from signal D0 and output to the time delay that produces new signal CK rising edge, be defined as Tosc.Can find out from oscillogram shown in Figure 5, Tcq is the difference of Tx and Tcq, so as long as measure the value of Tx and Tcq, just can obtain the exact value of Tcq.When measuring Tx, the second enable signal MD_EX and the first enable signal OSCE all are set to logical zero, the oscillation period of the output signal OSC_OUT by external testing apparatus measures pulse signal trigger, obtain Tx.
In the 3rd step, the first Enable Pin control first mode commutation circuit accesses the output terminal of the second pattern commutation circuit, by the output oscillation period of described the second annular oscillation circuit of external testing apparatus measures.
The first enable signal OSCE is set to logical one, this moment first mode commutation circuit I5, the first phase inverter I4, with or door I0, the 3rd phase inverter I7 and the second pattern commutation circuit I8 form the second annular oscillation circuit, signal OSC_OUT output waveform as shown in Figure 6, measure the oscillation period of the output signal OSC_OUT of the second annular oscillation circuit, can obtain outputing to the time delay that produces new signal CK rising edge from signal D0, be defined as Ty, from the annular oscillation circuit principle as can be known, Tosc=Ty/2.
In the 4th step, by the output oscillation period of two annular oscillation circuits that measure, the data that calculate the SRAM storage unit read the time.
By formula Tcq=Tx-Tosc, can measure SRAM reading out data cycle T cq.
SRAM storage unit among the present invention can be the SRAM of arbitrary address width, any input and output bit wide, and is not limited only to the above-mentioned SRAM storage unit that two address locations and an input and output position are only arranged.
Technology contents of the present invention and technical characterictic have disclosed as above; yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and are done all replacement and modifications that does not deviate from spirit of the present invention; therefore; protection domain of the present invention should be not limited to the content that embodiment discloses; and should comprise various do not deviate from replacement of the present invention and modifications, and contained by the present patent application claim.
Claims (11)
1.SRAM sequence testing circuit comprises SRAM storage unit and test circuit unit, described SRAM storage unit comprises address signal input end, clock signal input terminal and reading data signal output terminal, it is characterized in that, described test circuit unit comprises:
The first mode commutation circuit, input end links to each other with described reading data signal output terminal;
The edge signal trigger circuit, input end links to each other with the output terminal of described first mode commutation circuit;
The second pattern commutation circuit, input end links to each other with the output terminal of described edge signal trigger circuit, output terminal links to each other with described clock signal input terminal;
Described first mode commutation circuit has the first Enable Pin, and described the second pattern commutation circuit has the second Enable Pin.
2. SRAM sequence testing circuit according to claim 1 is characterized in that,
When the first Enable Pin control first mode commutation circuit access reading data signal output terminal, when the second Enable Pin was controlled the second pattern commutation circuit access edge signal trigger circuit output terminal, described SRAM storage unit, first mode commutation circuit, edge signal trigger circuit and the second pattern commutation circuit formed the first annular oscillation circuit;
When the first Enable Pin control first mode commutation circuit accessed the output terminal of the second pattern commutation circuit, described first mode commutation circuit, edge signal trigger circuit and the second pattern commutation circuit formed the second annular oscillation circuit.
3. SRAM sequence testing circuit according to claim 1, it is characterized in that, described first mode commutation circuit adopts two road gates, wherein an input end links to each other with described reading data signal output terminal by the first Sheffer stroke gate, another input end links to each other with the output terminal of described the second pattern commutation circuit, and output terminal links to each other with the input end of described edge signal trigger circuit by the first phase inverter.
4. SRAM sequence testing circuit according to claim 3, it is characterized in that, described edge signal trigger circuit comprise delay unit, the second phase inverter, the second Sheffer stroke gate and same or door, described delay unit input end links to each other with described the first inverter output, described the second phase inverter input end links to each other with described delay unit output terminal, described the second a Sheffer stroke gate wherein input end links to each other with the output terminal of described the second phase inverter, another input end links to each other with described the first Enable Pin, described with or the door wherein an input end link to each other with the output terminal of described the second Sheffer stroke gate, another input end links to each other with described delay unit input end.
5. SRAM sequence testing circuit according to claim 4, it is characterized in that, described the second pattern commutation circuit adopts two road gates, wherein an input end through the 3rd phase inverter with described with or the output terminal of door links to each other, another input end is inputted external testing input clock signal, output terminal links to each other with described clock signal input terminal.
6. SRAM sequence testing circuit according to claim 4 is characterized in that, described test circuit unit also comprises:
Address production electric circuit, input end links to each other with described edge signal trigger circuit output terminal;
The three-mode commutation circuit, input end links to each other with described address production electric circuit output terminal, output terminal links to each other with described address signal input end.
7. SRAM sequence testing circuit according to claim 6 is characterized in that, described address production electric circuit adopts clock synchronization circuit, and its Enable Pin is the second Enable Pin.
8. SRAM sequence testing circuit according to claim 6 is characterized in that, described three-mode commutation circuit adopts two road gates, another input termination external address input signal, and its Enable Pin is the second Enable Pin.
9. the SRAM time sequence test method of described SRAM sequence testing circuit according to claim 1 is characterized in that, may further comprise the steps:
Step 1, the first Enable Pin control first mode commutation circuit access reading data signal output terminal, the second Enable Pin is controlled the second pattern commutation circuit access edge signal trigger circuit output terminal, by the output oscillation period of described the first annular oscillation circuit of external testing apparatus measures;
Step 2, the first Enable Pin control first mode commutation circuit accesses the output terminal of the second pattern commutation circuit, by the output oscillation period of described the second annular oscillation circuit of external testing apparatus measures.
Step 3, by the output oscillation period of two annular oscillation circuits that measure, the data that calculate the SRAM storage unit read the time.
10. SRAM time sequence test method according to claim 9, it is characterized in that, before measuring output oscillation period of the first annular oscillation circuit, trigger the SRAM storage unit by external schema and carry out primary address and read, the address value that reads remains on described reading data signal output terminal.
11. SRAM time sequence test method according to claim 10, it is characterized in that, comprise by the external schema triggering: the second Enable Pin is controlled respectively the second pattern commutation circuit input external testing input clock signal, three-mode commutation circuit input external address input signal, and described external testing input clock signal triggers the SRAM storage unit outside address input signal is read.
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| CN111383702A (en) * | 2020-03-11 | 2020-07-07 | 展讯通信（上海）有限公司 | SRAM (static random Access memory) timing sequence test circuit and method and memory |
| CN116094497A (en) * | 2023-04-11 | 2023-05-09 | 长鑫存储技术有限公司 | Sampling test circuit |
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| CN106158044A (en) * | 2015-04-17 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | SRAM accesses test circuit and the method for testing of time |
| CN106158044B (en) * | 2015-04-17 | 2019-06-18 | 中芯国际集成电路制造(上海)有限公司 | The test circuit and test method of SRAM access time |
| CN107293329A (en) * | 2016-03-30 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of access time measuring circuit |
| CN106155857B (en) * | 2016-07-13 | 2018-06-22 | 无锡中微亿芯有限公司 | The storage unit read-write detecting system and method for FPGA electrification reset processes |
| CN106155857A (en) * | 2016-07-13 | 2016-11-23 | 无锡中微亿芯有限公司 | The memory cell read-write detecting system of FPGA electrification reset process and method |
| CN106782669B (en) * | 2016-11-23 | 2020-04-10 | 上海华力微电子有限公司 | Self-calibration extensible SRAM delay test circuit |
| CN106782669A (en) * | 2016-11-23 | 2017-05-31 | 上海华力微电子有限公司 | A kind of self calibration scalability SRAM delay test circuits |
| CN107068192A (en) * | 2017-03-31 | 2017-08-18 | 上海华虹宏力半导体制造有限公司 | Local clock pulses generation circuit for the time-ordered measurement of memory |
| CN109994144A (en) * | 2019-04-23 | 2019-07-09 | 江苏科大亨芯半导体技术有限公司 | A kind of SRAM outgoing route sequence testing circuit and test method |
| CN110047551A (en) * | 2019-04-23 | 2019-07-23 | 江苏科大亨芯半导体技术有限公司 | A kind of SRAM input path sequence testing circuit and test method |
| CN111312323A (en) * | 2020-03-11 | 2020-06-19 | 展讯通信（上海）有限公司 | SRAM (static random Access memory) timing sequence test circuit and method and memory |
| CN111341376A (en) * | 2020-03-11 | 2020-06-26 | 展讯通信（上海）有限公司 | SRAM (static random Access memory) timing sequence test circuit and test method |
| CN111383702A (en) * | 2020-03-11 | 2020-07-07 | 展讯通信（上海）有限公司 | SRAM (static random Access memory) timing sequence test circuit and method and memory |
| CN116094497A (en) * | 2023-04-11 | 2023-05-09 | 长鑫存储技术有限公司 | Sampling test circuit |
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