CN102495349B - Path delay on-line measurement circuit - Google Patents
Path delay on-line measurement circuit Download PDFInfo
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- CN102495349B CN102495349B CN201110411950.XA CN201110411950A CN102495349B CN 102495349 B CN102495349 B CN 102495349B CN 201110411950 A CN201110411950 A CN 201110411950A CN 102495349 B CN102495349 B CN 102495349B
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Abstract
A path delay on-line measurement circuit comprises a measurement trigger module connected with a to-be-detected circuit, a to-be-detected source selection module connected with the measurement trigger module and controlling signals sent by the measurement trigger module to selectively pass, a delay measurement module connected with the to-be-detected source selection module and carrying out delay measurement to signals sent by the to-be-detected source selection module, a storage module connected with the delay measurement module and storing delay measurement information of the delay measurement module, and a control module for controlling operation of the measurement trigger module, the to-be-detected source selection module and the storage module. The path delay on-line measurement circuit is connected to the to-be-detected circuit, the control module controls the path delay on-line measurement circuit to work in a probe path delay measurement mode so as to measure and obtain delay of each probe path and controls the path delay on-line measurement circuit to work in an on-line delay measurement mode so as to measure and obtain total delay. Finally, the measured probe path delay is subtracted from the total delay, and the delay of the to-be-detected path is obtained.
Description
[technical field]
The present invention relates to integrated circuit technique, particularly relate to a kind of path delay on-line measurement circuit that VLSI (very large scale integrated circuit) middle part sub-path is carried out to on-line measurement in path delay.
[background technology]
Along with the continuous progress of semiconductor industry production technology, constantly the VLSI (very large scale integrated circuit) of upgrading shows stronger function and lower cost.But meanwhile, the performance of integrated circuit presents more and more significant unpredictability (in the same time, under environment, its performance difference is quite not large).This is because the deviation in procedure for producing, the environmental parameter in when work change and the factor such as aging effect is more and more serious on the impact of performance of integrated circuits.Correspondingly, for the sequential correctness (being in most cases the most important performance index of integrated circuit) of integrated circuit, common testing scheme is by integrated circuit being moved to production test program on outside tester.But this method of testing has more and more been difficult to ensure sequential correctness.Auto testing instrument itself has inevitably been introduced measuring error, and this error, for measuring more and more accurate integrated circuit timing performance, shows more and more serious interference.In addition, the metering circuit on the conventional chip that does not rely on outside auto testing instrument, cannot carry out on-line measurement, and it is very low to carry out its measuring accuracy of metering circuit of on-line measurement.
[summary of the invention]
Based on this, be necessary to provide a kind of path delay on-line measurement circuit, can realize very high measuring accuracy and treat survey line-hit less.This path delay on-line measurement circuit comprises the measurement triggering module being connected with circuit under test, the signal that also control survey trigger module transmits that is connected with measurement triggering module selects the source to be measured of passing through to select module, the signal of selecting module to be connected with source to be measured and to transmit selection module in source to be measured carries out the Time delay measurement module of Time delay measurement, the memory module that is connected with Time delay measurement module and the Time delay measurement information of Time delay measurement module is stored, and the control module of control survey trigger module, source to be measured selection module and memory module operation
In a preferred embodiment, described measurement triggering module comprises circuit under test and the isolated multiple measurement triggering devices that come of source to be measured selection module.
In a preferred embodiment, described measurement triggering device comprises input selector, main latch, from latch, the first phase inverter, the second phase inverter and MUX, the output terminal of described input selector is connected with the input end of described main latch, the output terminal of described main latch is connected with the described input end from latch, the described input end from latch is connected with the input end of described the first phase inverter, described main latch and being connected with the input end of described the second phase inverter from the clock signal terminal of latch interconnects, the output terminal of the output terminal of described the first phase inverter and described the second phase inverter is connected with two input ends of described MUX respectively.
In a preferred embodiment, the signal selection module that signal is selected module to comprise to produce to select in described source to be measured be connected with signal selection module, according to the multiplexer of the selection signal gating respective paths of signal selection module.
In a preferred embodiment, described signal selection module comprises the priority encoder that judges that the input signal logical value whether occurrence logic value changes changes detector and is connected, the highest signal of priority is encoded with logical value transformation detector.
In a preferred embodiment, described Time delay measurement module comprises multistage Time delay measurement circuit, described every grade of Time delay measurement circuit has signal input part DI, signal input part CI, time delay output terminal DO, time delay output terminal CO and result output terminal Q, between multistage Time delay measurement circuit by making to connect as the signal input part DI of prime the time delay output terminal DO of prime, the time delay output terminal CO that connects prime as the signal input part CI of prime forms cascade structure, and every grade is all exported by result output terminal Q.
In a preferred embodiment, described Time delay measurement circuit comprises the first impact damper, the second impact damper, the 3rd impact damper, the 4th impact damper, d type flip flop and MUX;
Described the first impact damper, the second impact damper series connection, and the output terminal of described the first impact damper connects the input end of the second impact damper, the input end of described the first impact damper is as the signal input part DI of Time delay measurement circuit, the output terminal of described the first impact damper is connected with the D of d type flip flop end, and the output terminal of described the second impact damper is as the time delay output terminal DO of Time delay measurement circuit;
Described the 3rd impact damper, the 4th impact damper are in parallel, the 3rd impact damper, the 4th input end of impact damper and the CK of d type flip flop end are connected and as the signal input part CI of Time delay measurement circuit, the output terminal of the 3rd impact damper, the 4th impact damper is inputted respectively two input ports of MUX, the Q end of d type flip flop is connected with the control end of MUX, the output terminal of described MUX is as the time delay output terminal CO of Time delay measurement circuit, and the Q end of d type flip flop is as the result output terminal Q of Time delay measurement circuit.
In a preferred embodiment, the Time delay measurement information of described memory module storage comprises numbering, measurement type and the delay time of measurement triggering device.
In a preferred embodiment, described Time delay measurement module adopt clock signal, control signal and synchronizing signal one of them as benchmark.
In above-mentioned path delay on-line measurement circuit, control module control survey trigger module is placed in probe path Time delay measurement pattern, so that measurement triggering module output calibrating signal, first, this calibrating signal is transmitted to delay measuring unit along probe path; Then, source to be measured select the signal selection module of module and multiplexer successively the each paths of gating transfer to Time delay measurement module and measure and stored by memory module; Now obtain the time delay of each probe path.In addition, control module control survey trigger module is placed in total Time delay measurement pattern, and first, measured signal propagates into signal selection module along probe path separately; Then, source to be measured selects the signal selection module of module to produce a set of selection signal using the control signal as multiplexer, controls the corresponding path of multiplexer gating, makes to only have a road signal to continue to propagate by multiplexer; Then, the unique road signal choosing continues to be transmitted to Time delay measurement module, and carries out Time delay measurement at that; Then, the result of Time delay measurement is input to memory module and stores; Now obtain total time delay.The time delay that total time delay deducts probe path just can obtain the time delay in path to be measured.This path delay on-line measurement circuit is realized the isolation of source to be measured selection module and circuit under test by measurement triggering module, eliminate the interference between circuit under test and this path delay on-line measurement circuit, adopt and probe path time delay is deducted from total time delay and obtain the mechanism of circuit under test path delay, eliminate the uncertain of probe path and to measuring the error effect causing, realized high-acruracy survey.This path delay on-line measurement circuit have disturb little, measuring accuracy is high, circuit design is simple, and the low advantage of cost.
[brief description of the drawings]
Fig. 1 is the general frame of the path delay on-line measurement circuit of one embodiment of the invention;
Fig. 2 is the circuit structure diagram of the measurement triggering device of measurement triggering module;
Fig. 3 is the circuit module figure that the signal selection module of module is selected in source to be measured;
Fig. 4 is the circuit structure diagram that the logical value of signal selection module shown in Fig. 3 changes detector;
Fig. 5 is the circuit module figure of Time delay measurement module;
Fig. 6 is the circuit structure diagram of the wherein one-level Time delay measurement circuit of Time delay measurement module shown in Fig. 5.
Fig. 7 is the memory circuit schematic diagram of memory module.
Fig. 8 is the working waveform figure of Time delay measurement module.
Fig. 9 is that path delay on-line measurement circuit application of the present invention carries out in reference circuit S38417 the experimental result that path delay measures.
Figure 10 introduces foozle for path delay on-line measurement circuit of the present invention and measures obtained measurement result.
[embodiment]
Below in conjunction with accompanying drawing, preferred embodiment of the present invention is described in detail, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that, protection scope of the present invention is made to more explicit defining.
Please refer to Fig. 1, one embodiment of the invention provides a kind of path delay on-line measurement circuit.This path delay on-line measurement circuit comprises the measurement triggering module 2 being connected with circuit under test 1, the signal that also control survey trigger module 2 transmits that is connected with measurement triggering module 2 selects the source to be measured of passing through to select module 3, the signal of selecting module 3 to be connected with source to be measured and to transmit selection module 3 in source to be measured carries out the Time delay measurement module 4 of Time delay measurement, the memory module 5 that is connected with Time delay measurement module 4 and the Time delay measurement information of Time delay measurement module 4 is stored, and control survey trigger module 2, the source to be measured control module 6 of selecting module 3 and memory module 5 to move.Wherein, source to be measured selects module 3 to be made up of signal selection module 8 and multiplexer 7.
By in this path delay on-line measurement circuit access circuit under test 1, measurement triggering module 2 is placed in probe path by control module 6, and (probe path refers to the path from a measurement triggering device to delay measuring unit, also be that measured signal is drawn and arrives the path of measuring unit) Time delay measurement pattern, to make it to export calibrating signal, this signal is transmitted to Time delay measurement module 4 along probe path; The module 3 each paths of gating is successively selected in source to be measured, and one of each gating.Just can measure the time delay of each probe path.Then, control path delay on-line measurement circuit is entered online Time delay measurement pattern by control module 6, signal arrives after end along propagated to be measured in circuit under test 1, measured trigger module 2 is drawn and is entered this path delay on-line measurement circuit, and enters Time delay measurement module 4 along probe path always and carry out Time delay measurement.Now measured delay value is total time delay of path to be measured and probe path.Finally, from total time delay, deduct the time delay of measured probe path, just obtain the time delay in path to be measured.
The modules of this path delay on-line measurement circuit will specifically be introduced below.
Please refer to Fig. 1 and Fig. 2, measurement triggering module 2 comprises selects the isolated multiple measurement triggering devices 20 that come of module 3 by circuit under test 1 and source to be measured.This measurement triggering device 20, except realizing the function of common sweep trigger, can also be introduced Time delay measurement module as required by measured signal and calibrating signal.This measurement triggering device 20 comprises input selector (T
1) 21, main latch 22, from latch 23, the first phase inverter (E
0) 24, the second phase inverter (E
1) 25 and MUX (M
0) 26.The output terminal of input selector 21 is connected with the input end of main latch 22, the output terminal of main latch 22 be connected from the input end of latch 23, from input end and the first phase inverter (E of latch 23
0) 24 input end is connected, main latch 22 and the clock signal terminal from latch 23 interconnect and the second phase inverter (E
1) 25 input end is connected, the first phase inverter (E
0) 24 output terminal and the second phase inverter (E
1) 25 output terminal respectively with MUX (M
0) two input ends of 26 are connected.The wherein output terminal Q as measurement triggering device 20 from the output terminal of latch 20, MUX (M
0) 26 output terminal is as the M end of measurement triggering device 20, MUX (M
0) 26 control end is as the P end of measurement triggering device 20, input selector (T
1) 21 data input pin D is as the D end of measurement triggering device 20.This measurement triggering device 20 compared with common sweep trigger, many three doors on hardware spending, i.e. two phase inverter (E
0) 24, (E
1) 25 and a MUX (M
0) 26.Two phase inverter (E
0) 24, (E
1) 25 effect is functional circuit to be measured 1 and source to be measured to be selected to module 3 is isolated to come, thereby do not disturb the normal work of circuit under test 1.On logic level, circuit under test 1 is unaware of additional metering circuit completely, still according to designed function operation, thereby has simplified circuit design and operation.The effect of MUX 26 is corresponding to different measurement patterns, output measured signal or calibrating signal.
This measurement triggering device 20 compared with common sweep trigger, in input, on output port, many an input port P and output port M.The mode signal of port P Access Control module 6, to select probe path Time delay measurement pattern (P=1) or total Time delay measurement pattern (P=0).Corresponding to different patterns, the M end corresponding calibrating signal of output or the measured signal of measurement triggering device 20, be all transferred to Time delay measurement module 4 and measure.
When control module 6 control survey triggers 20 are during in probe path Time delay measurement pattern (P=1), the clock signal C K in measurement triggering device 20 is selected by MUX (M
0) 26 (by the second phase inverter (E
1) 25 signal), and via the M end output of measurement triggering device 20.One end of Time delay measurement module 4 is connected with clock signal all the time, and therefore, now the mistiming of two input signals is probe path time delay, also just means the time delay that now measures probe path.
When control module 6 control survey triggers 20 are during in total Time delay measurement pattern (P=0), the output of main latch 22 (Master Latch) is via the first phase inverter (E
0) 24, by MUX (M
0) 26 gatings and draw the M end of measurement triggering device 20, also mean that signal along propagated to be measured to end is further drawn the M of measurement triggering device 20 and held, carry out Time delay measurement to be input to Time delay measurement module 4.The total time delay that is path to be measured and probe path now surveyed.
Adopt phase inverter to realize the isolation of circuit under test 1 and source to be measured selection module 3 herein, also phase inverter can be changed to other device in other embodiments, as Sheffer stroke gate.Herein, measurement triggering device 20 is drawn measured signal from main latch 22 (Master Latch) outgoing position (being the output terminal of main latch 22), is sent to the first phase inverter (E
0) 24, also the extraction location of measured signal can be changed to other correct position in other embodiments, as positions such as the output terminal Q of the data input pin D of the input end of main latch 22, measurement triggering device 20, measurement triggering device 20.In the time utilizing the output terminal Q of data input pin D, measurement triggering device 20 of measurement triggering device 20 to draw measured signal, can use conventional trigger, because now can draw measured signal outward at trigger, without trigger being made to inner change.
Please refer to Fig. 3, in one embodiment, the signal selection module 8 that signal is selected module 3 to comprise to produce to select in source to be measured be connected with signal selection module 8, according to the multiplexer 7 of the selection signal gating respective paths of signal selection module 8.Signal selection module 8 comprises the priority encoder that judges that the input signal logical value whether occurrence logic value changes changes detector TD and is connected, the highest signal of priority is encoded with logical value transformation detector TD.Adopt mulitpath to share the pattern of same Time delay measurement circuit herein, and ensure that each moment only has a paths to be strobed and carry out Time delay measurement, to avoid conflict and to disturb, can greatly reduce like this hardware quantity and the power consumption of path delay on-line measurement circuit.When this source to be measured selects module 3 to work, whether subsistence logic value changes in specific time window first to survey every path to be measured, then selects a path that priority is the highest to carry out Time delay measurement the path changing from subsistence logic value.
Specifically, signal selection module 8 produces a set of selection signal, using the control signal as multiplexer 7, controls the multiplexer 7 corresponding paths of gating, thereby makes to only have a road signal to continue to propagate by multiplexer 7 in multiple signals.This signal selection module 8 mainly contains logical value and changes detector TD (Transition Detector) and priority encoder composition.From each output port M
0, M
1... M
nsignal out, arrives source to be measured along probe path separately and selects after module 3, and the logical value first entering separately changes detector TD.When entering input signal that logical value changes detector TD within the predetermined time when the transformation of occurrence logic value, the output that this logical value changes detector TD becomes effectively, otherwise maintenance disarmed state.Useful signal represents that corresponding path interested signal has occurred and propagated, and waits pending Time delay measurement.Then in the path, changing in all occurrence logic values, select the path transmission that priority is the highest to a Time delay measurement module to carry out Time delay measurement.
Please refer to Fig. 4, logical value changes detector TD and comprises three PMOS transistor P
0, P
1, P
2, five nmos pass transistor N
0, N
1, N
2, N
3, and N
4, and a rejection gate G
0.What logical value changed detector TD is mainly to survey in given time window, and whether input signal D the transformation of logical value has occurred, and for example logical value becomes 1 or become 0 from 1 from 0.The lower bound of this time window is by input signal T
l, determine, the upper bound is by input signal T
udetermine.In the time that logical value changes, logical value changes detector TD output R and becomes logical one, otherwise keeps 0.
Please refer to Fig. 5, this Time delay measurement module 4 comprises multistage Time delay measurement circuit S
0, S
1... S
n-1, S
n.Every grade of Time delay measurement circuit has signal input part DI, signal input part CI, time delay output terminal DO, time delay output terminal CO and result output terminal Q, between multistage Time delay measurement circuit by making to connect as the signal input part DI of prime the time delay output terminal DO of prime, the time delay output terminal CO that connects prime as the signal input part CI of prime forms cascade structure, and every grade is all exported by result output terminal Q.The design of this Time delay measurement module is the measurement mechanism based on vernier delay line.Two input signal R and T are successively by every one-level Time delay measurement circuit of Time delay measurement module 4, and input signal R and input signal T mistiming between the two just can make the output (Q at different levels of circuit
n-Q
0) present different combinations, correspondingly, synthetic circuit output at different levels just can obtain the result of Time delay measurement.This Time delay measurement module 4 can adopt clock signal, control signal and synchronizing signal one of them as benchmark (being connected with among input signal R and input signal T one).
The Time delay measurement circuit S at different levels of this Time delay measurement module 4
0, S
1... S
n-1, S
ndetailed design as shown in Figure 6.Every one-level circuit comprises the first impact damper (B
i) 41, the second impact damper (B
d) 42, the 3rd impact damper (B
0) 43, the 4th impact damper (B
1) 44,, d type flip flop 45 and MUX 46.Wherein the first impact damper (B
i) 41, the second impact damper (B
d) 42 series connection, and the first impact damper (B
i) 41 output terminal connects the second impact damper (B
d) 42 input end, the first impact damper (B
i) 41 input end is as the signal input part DI of Time delay measurement circuit, the first impact damper (B
i) 41 output terminal and the D of d type flip flop 45 end is connected, the second impact damper (B
d) 42 output terminal is as the time delay output terminal time delay output terminal DO of Time delay measurement circuit.The 3rd impact damper (B
0) 43, the 4th impact damper (B
1) 44 be in parallel, the 3rd impact damper (B
0) 43, the 4th impact damper (B
1) 44 input end and the CK of d type flip flop 45 end is connected and as the signal input part CI of Time delay measurement circuit, the 3rd impact damper (B
0) 43, the 4th impact damper (B
1) 44 output terminal inputs respectively two input ports of MUX 46, the Q end of d type flip flop 45 is connected with the control end of MUX 46, the output terminal of MUX 46 is as the time delay output terminal CO of Time delay measurement circuit, and the Q end of d type flip flop is as the result output terminal Q of Time delay measurement circuit.This Time delay measurement circuit utilizes d type flip flop at rising edge clock, input data to be carried out the principle of value, the mistiming of two input signals is compared and obtains the output of this grade, and according to result relatively to this mistiming adjust accordingly, thereby make two signals there is the new mistiming after by this grade.
Please also refer to Fig. 5 and Fig. 6, this Time delay measurement module 4 is different from common vernier delay line.
In the design based on vernier delay line, two input signals pass through delay line separately in circuit at different levels, and the time delay of two delay lines is not identical, and its difference is called feature delay inequality.In the design of current vernier delay line, these two delay lines have an identical feature delay inequality d at different levels.And feature time delay differences that have according to exponential distribution at different levels in this Time delay measurement module, the feature delay inequality in i level is d
i=d
0× 2
i, most end one-level (the 0th grade) be d
0.Accordingly, in the measurement based on common vernier delay line, the calculating of measurement result needs first after statistical measurement, be output as effective progression m, and then to obtain measurement result be D=m × d.And this Time delay measurement module is without follow-up statistics, output (Q at different levels
n... Q
0) be exactly directly the binary numeral of measurement result, D=(Q
n... Q
0)
2× d
0, wherein, in formula, the footmark 2 in the round bracket lower right corner represents scale-of-two.As can be seen here, this Time delay measurement module reduction circuit design and numerical value processing.
In common vernier delay line, the processing that circuit at different levels are fixed the delay inequality of two input signals, the delay inequality that delay inequality of output equals to input deducts feature delay inequality at the corresponding levels.And in this Time delay measurement module, if the delay inequality of two input signals is greater than feature delay inequality at the corresponding levels, the delay inequality that delay inequality of output equals to input deducts feature delay inequality at the corresponding levels, otherwise remain unchanged.
Based on the time difference measurements of vernier delay line, its range is the summation of circuit feature delay inequalities at different levels, and measuring accuracy depends on minimum feature delay inequality.This Time delay measurement module utilizes the little delay inequality of most end one-level (the 0th grade) to realize high measurement accuracy, and the delay inequalities at different levels that utilization index increases have been realized wide range, have reduced the progression of circuit.
Time delay measurement module is the mistiming of two input signals relatively, and this mistiming is converted into digitized value, thus processing and storage after convenient.In addition, one end of Time delay measurement module is connected with clock signal all the time, also just mean each measured signal all therewith clock signal carry out the comparison of mistiming.The function of Time delay measurement module is that the mistiming of two input signals is carried out to digitizing, and the multiple Time delay measurement module being implemented on chip may be used to this Time delay measurement module.And having adopted a kind of new delay measurements module herein, it can carry out Time delay measurement better.The benefit of this delay measurements module is: realize high measurement accuracy with low hardware spending, and measurement result Direct Digital can be turned to binary numeral, simplified subsequent treatment.
Please refer to Fig. 7, the memory module 5 of this path delay on-line measurement circuit is not simple storage measurement result each time, can cause like that great storage space needs.In one embodiment, for each measurement triggering device 20, only for it is equipped with 2 storage unit, the measurement result of first cell stores path delay, the measurement result of second total time delay of cell stores.For example, if adopt the delay measuring unit of 8 grades, just measurement result is the binary number of 8, the needed storage space of each measurement triggering device is only 16, or 2 bytes (byte); If be provided with 100 measurement triggering devices, only need 200 bytes of storage space.
After each measurement, the information that is input to memory module 5 comprises: the signal institute of this time measuring from measurement triggering device 20 number, measure type (probe path time delay, always time delay), delay time.First memory module 5 reads corresponding to the content of the storage unit of this measurement triggering device 20 (being last measurement result) and compares,, in the time that new measurement result is greater than storing value, be just only new measurement result (long delay is the deciding factor of performance of integrated circuits and the useful information of circuit monitoring) by the content update of storage unit.
Therefore this programme, with minimum hardware spending, has been realized the storage of valuable measurement result, thereby the burden of main system is increased seldom.
The measuring process of this path delay on-line measurement circuit will be introduced below.
The measuring process of this path delay on-line measurement circuit comprises the Time delay measurement of probe path and two stages of measurement of total time delay.Wherein, in each measuring phases, the workflow that this path delay on-line measurement circuit is realized Time delay measurement is as follows:
(1) measured signal propagates in the circuit of this path delay on-line measurement circuit along probe path separately.
(2) first measured signal arrives source to be measured and selects module, source to be measured selects the signal selection module of module to produce a set of selection signal, using the control signal as multiplexer, control the corresponding path of its gating, thereby make to only have a road signal to continue to propagate by multiplexer in multiple signals.
(3) the unique road signal choosing continues to be transmitted to Time delay measurement module, and carries out Time delay measurement at that.
(4) result of Time delay measurement is input to memory module and stores.
Wherein, probe path refers to the path from a measurement triggering device to delay measuring unit, is also that measured signal is drawn and arrives the path of measuring unit.When path delay on-line measurement circuit is started working, first the time delay of each probe path is measured successively and is stored.In the probe path Time delay measurement stage, each measurement triggering device is placed in probe path Time delay measurement pattern by control module, and to make it to export calibrating signal, this signal is transmitted to delay measuring unit along probe path; The multiplexer each paths of gating successively of module is selected in source to be measured, and one of each gating.Just can measure the time delay of each probe path.Be herein clock signal that measurement triggering device is drawn as calibrating signal, carry out the measurement of probe path time delay.Also can adopt in other embodiments other signal, if control signal, synchronizing signal etc. are as calibrating signal.
For the measuring phases of total time delay, after having carried out probe path Time delay measurement, control path delay on-line measurement circuit is entered online Time delay measurement pattern by the control module of path delay on-line measurement circuit.Signal arrives after end along propagated to be measured in circuit, is further drawn by each measurement triggering device, enters Time delay measurement module always carry out Time delay measurement along probe path.Now measured delay value is total time delay of path to be measured and probe path.
The time delay of probe path and total time delay are stored in memory module, obtaining, after the Time delay measurement of probe path and the measurement result of total time delay, deducting the time delay of measured probe path from total time delay, just obtain the time delay in path to be measured.
Only circuit under test end is connected in this path delay on-line measurement circuit, carrying out, in Time delay measurement, measuring and deduct the time delay of this probe path herein.In one embodiment, also the signal input part of circuit under test and signal output part all can be connected to this path delay on-line measurement circuit, carrying out in Time delay measurement, the time delay of these two probe path that measurement and deduction are connected respectively with signal input part, signal output part two ends just can obtain the time delay of circuit under test.
The effect of utilizing this path delay on-line measurement circuit to do some to test to verify this path delay on-line measurement circuit below.
Please refer to Fig. 8, in an experiment, we have carried out functional verification to the Time delay measurement module of this path delay on-line measurement circuit.
The function of Time delay measurement module is that the mistiming of two input signals is carried out to digitizing.In this experiment, delay measuring unit has 5 grades of (S
4s
3s
2s
1s
0) form, feature delay inequality at different levels was respectively for 0.32,0.16,0.08,0.04,0.02 nanosecond, set two input signal V
in, V
refmistiming be 0.45 nanosecond.Waveform from Fig. 8 can be found out, the measuring unit Q that are output as at different levels
4q
3q
2q
1q
0=10110, mean that measurement result is D=(Q
n... Q
0)
2× d
0=(10110)
2× 0.02=0.44 nanosecond.Wherein, in formula, the footmark 2 in the round bracket lower right corner represents scale-of-two.This Time delay measurement result is compared with 0.45 nanosecond of actual value, and this measured value exists the error of-0.01 nanosecond.
Please refer to Fig. 9, in an experiment, we verify the measuring accuracy of this path delay on-line measurement circuit.
In this experiment, this path delay on-line measurement circuit application is carried out to path delay measurement in the reference circuit S38417 of ISCAS ' 89.Corresponding to the required measurement range of this experiment, this experiment has realized the measuring unit with 7 grades, and wherein the delay inequality of i level is d
i=d
0× 2
i=0.02 × 2
inanosecond.To the Time delay measurement result of 10 wherein the longest paths as shown in the figure.Wherein, the first hurdle No. is path sequence number; The second hurdle d
simube the path delay obtaining from SPICE data, can be considered the actual value d of path delay; Third column d
pfor utilizing the measured value of the probe path time delay that this path delay on-line measurement circuit obtains; The 4th hurdle d
tfor utilizing the measured value of total time delay that this path delay on-line measurement circuit obtains; The 5th hurdle d
cODA=d
t-d
p, for utilizing the numerical value of the path delay to be measured that this path delay on-line measurement circuit obtains; The 6th hurdle Δ d=d
cODA-d
simu, for utilizing the absolute error of the measurement result that this path delay on-line measurement circuit obtains; The 7th hurdle Err=| Δ d/d
simu| × 100%, for utilizing the relative error of the measurement result that this path delay on-line measurement circuit obtains.
Can find out from experimental result, the measurement result of utilizing this path delay on-line measurement circuit to obtain, its absolute error is at [d
0, d
0] scope in (this experiment in d
0=0.02 nanosecond), therefore, this path delay on-line measurement circuit has very high measuring accuracy.
Please refer to Figure 10, in an experiment, we verify the impact of measuring accuracy the foozle of this path delay on-line measurement circuit.
For the impact of testing integrated circuits foozle on this path delay on-line measurement circuit, (error that in circuit, each CMOS transistor is introduced in each simulation is random value specially to introduce the foozle of 5% scope by the mode of Monte Carlo simulation, but maximum is no more than 5%), and in the case of the foozle of this scope exists, utilize this path delay on-line measurement circuit to carry out the test of 1000 times to each target to be measured, the statistical conditions of corresponding test result as shown in figure 10.
Wherein, the first hurdle time delay is target time delay to be measured, from 0.8 to 1.15 nanosecond; The second hurdle to the seven hurdle measuring error are the shared ratio of measurement result with different errors.For example the numerical value of the third line third column is 13%, means that the measurement result with-40 psec (ps) errors is occupied 13% ratio (1000 × 13%=130 time) in 1000 times that the time delay of 0.8 nanosecond is done are measured.
Experimental data from Figure 10 can sum up, and its error amount of nearly 85% measurement result is in the scope of 0.02 nanosecond.And maximum error was 0.06 nanosecond, shared ratio only has 0.1%.As can be seen here, this path delay on-line measurement circuit is insensitive to foozle,, in the situation that foozle exists, still can obtain high-precision Time delay measurement result.
This path delay on-line measurement circuit of the present invention can be realized the glitch-free online Time delay measurement in integrated circuit (IC) chip.After additional this path delay on-line measurement circuit, integrated circuit still carries out the feature operation of itself, does not recognize the additional of this path delay on-line measurement circuit on logic level completely, only in needs, reads interested data.And this path delay on-line measurement circuit can, in circuit working, carry out glitch-free Time delay measurement to circuit, what obtain is the path delay numerical value among real circuit working.This is because this path delay on-line measurement circuit by the measurement triggering device of this path delay on-line measurement circuit, completely cuts off functional circuit to come with metering circuit, makes the feature operation of functional circuit interference-free.
In this path delay on-line measurement circuit, by being deducted to probe path time delay, total time delay obtains the measurement mechanism of path delay to be measured, realized high-precision measurement, this be because this path delay on-line measurement circuit for eliminating the uncertainty of probe path time delay.Can not determine in final produced chip that in chip design stage the trend of probe path and length also just cannot be determined its time delay.If can not obtain the accurate data of probe path time delay, will greatly reduce the precision of path to be measured being carried out to Time delay measurement, even make the result of measurement valueless at all.This path delay on-line measurement circuit, by measurement triggering device, sends calibrating signal by probe path, to measure the time delay in time delay path, eliminates the interference that probe path is measured path delay to be measured, has improved the precision of measuring.
In addition, this path delay on-line measurement circuit only needs path ends to be connected to delay measuring unit, can greatly reduce the wiring expense of circuit, especially in the situation that metering circuit is positioned near path ends.This path delay on-line measurement circuit utilizes the little delay inequality of most end one-level (the 0th grade) to realize high measurement accuracy, and the delay inequalities at different levels that utilization index increases have been realized wide range, have reduced the sum of series hardware spending of circuit.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (7)
1. a path delay on-line measurement circuit, it is characterized in that, comprise the measurement triggering module being connected with circuit under test, the signal that also control survey trigger module transmits that is connected with measurement triggering module selects the source to be measured of passing through to select module, the signal of selecting module to be connected with source to be measured and to transmit selection module in source to be measured carries out the Time delay measurement module of Time delay measurement, the memory module that is connected with Time delay measurement module and the Time delay measurement information of Time delay measurement module is stored, and control survey trigger module, the control module of module and memory module operation is selected in source to be measured, the signal selection module that signal is selected module to comprise to produce to select in described source to be measured be connected with signal selection module, according to the multiplexer of the selection signal gating respective paths of signal selection module, described signal selection module comprises and judge the input signal logical value transformation detector whether occurrence logic value changes and the priority encoder that is connected, the highest signal of priority is encoded with logical value transformation detector.
2. path delay on-line measurement circuit according to claim 1, is characterized in that, described measurement triggering module comprises selects the isolated multiple measurement triggering devices that come of module by circuit under test and source to be measured.
3. path delay on-line measurement circuit according to claim 2, it is characterized in that, described measurement triggering device comprises input selector, main latch, from latch, the first phase inverter, the second phase inverter and MUX, the output terminal of described input selector is connected with the input end of described main latch, the output terminal of described main latch is connected with the described input end from latch, the described input end from latch is connected with the input end of described the first phase inverter, described main latch and being connected with the input end of described the second phase inverter from the clock signal terminal of latch interconnects, the output terminal of the output terminal of described the first phase inverter and described the second phase inverter is connected with two input ends of described MUX respectively.
4. path delay on-line measurement circuit according to claim 1, it is characterized in that, described Time delay measurement module comprises multistage Time delay measurement circuit, described every grade of Time delay measurement circuit has signal input part DI, signal input part CI, time delay output terminal DO, time delay output terminal CO and result output terminal Q, between multistage Time delay measurement circuit by making to connect as the signal input part DI of prime the time delay output terminal DO of prime, the time delay output terminal CO that connects prime as the signal input part CI of prime forms cascade structure, and every grade is all exported by result output terminal Q.
5. path delay on-line measurement circuit according to claim 4, is characterized in that, described Time delay measurement circuit comprises the first impact damper, the second impact damper, the 3rd impact damper, the 4th impact damper, d type flip flop and MUX;
Described the first impact damper, the second impact damper series connection, and the output terminal of described the first impact damper connects the input end of the second impact damper, the input end of described the first impact damper is as the signal input part DI of Time delay measurement circuit, the output terminal of described the first impact damper is connected with the D of d type flip flop end, and the output terminal of described the second impact damper is as the time delay output terminal DO of Time delay measurement circuit;
Described the 3rd impact damper, the 4th impact damper are in parallel, the 3rd impact damper, the 4th input end of impact damper and the CK of d type flip flop end are connected and as the signal input part CI of Time delay measurement circuit, the output terminal of the 3rd impact damper, the 4th impact damper is inputted respectively two input ports of MUX, the Q end of d type flip flop is connected with the control end of MUX, the output terminal of described MUX is as the time delay output terminal CO of Time delay measurement circuit, and the Q end of d type flip flop is as the result output terminal Q of Time delay measurement circuit.
6. path delay on-line measurement circuit according to claim 2, is characterized in that, the Time delay measurement information of described memory module storage comprises numbering, measurement type and the delay time of measurement triggering device.
7. path delay on-line measurement circuit according to claim 1, is characterized in that, described Time delay measurement module adopt clock signal, control signal and synchronizing signal one of them as benchmark.
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| CN106970317A (en) * | 2017-03-24 | 2017-07-21 | 哈尔滨工业大学（威海） | A kind of degradation failure detection sensor based on protection band |
| CN108829923B (en) * | 2018-05-04 | 2022-08-05 | 上海创远仪器技术股份有限公司 | Method and device for determining time delay calibration parameters, electronic equipment and storage medium |
| CN113884865B (en) * | 2020-07-01 | 2023-12-01 | 复旦大学 | Test circuit and test method of D trigger |
| CN114236285B (en) * | 2021-12-14 | 2023-06-13 | 中国工程物理研究院流体物理研究所 | Detonation experiment electrical measurement dynamic self-checking test system and test method thereof |
| CN114325348A (en) * | 2022-01-13 | 2022-04-12 | 苏州博创集成电路设计有限公司 | Inter-channel matching test circuit |
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