CN103825556A - Oscillating circuit - Google Patents
Oscillating circuit Download PDFInfo
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- CN103825556A CN103825556A CN201410078704.0A CN201410078704A CN103825556A CN 103825556 A CN103825556 A CN 103825556A CN 201410078704 A CN201410078704 A CN 201410078704A CN 103825556 A CN103825556 A CN 103825556A
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Abstract
The invention relates to an oscillating circuit. The oscillating circuit comprises a see-saw amplifier and a buffer, wherein the output end of the see-saw amplifier is connected with the input end of the buffer; the oscillating circuit also comprises a band-gap reference circuit and a current supplying circuit; the band-gap reference circuit comprises a current mirror circuit and is suitable for inputting a supply voltage; the current mirror circuit comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end and the second input end of the current mirror circuit are both suitable for inputting the supply voltage, and the first output end of the current mirror circuit is suitable for outputting reference current; the current supplying circuit is suitable for outputting first supply current to the power supply end of the see-saw amplifier and outputting second supply current to the power supply end of the buffer, and the first supply current and the second supply current are both related to the reference current.
Description
Technical field
The present invention relates to a kind of oscillating circuit.
Background technology
As shown in Figure 1, existing oscillating circuit comprises: inverting amplifier 1, buffer 2, the first resistance R _ f, the second resistance R s, the first capacitor C 1, the second capacitor C 2 and crystal oscillator Z.
The power end of inverting amplifier 1 and buffer 2 is suitable for inputting the supply voltage VDD of described oscillating circuit, and the output of inverting amplifier 1 connects the input OUT of buffer 2, and the input OUT of buffer 2 is as the output of oscillating circuit.
The first end of the first resistance R _ f connects input, the first end of crystal oscillator Z and the first end of the first capacitor C 1 of inverting amplifier 1, and the second end of the first resistance R _ f connects the first end of the second resistance R s and the output of inverting amplifier 2.
The second end of the second resistance R s connects the second end of crystal oscillator Z and the first end of the second capacitor C 2.The second end ground connection GND of the second end of the first capacitor C 1 and the second capacitor C 2.
Oscillating circuit can be operated under different supply voltage VDD, and generally, supply voltage VDD can be between 1.8V to 5.5V.But in the time that supply voltage VDD is larger, the power consumption of oscillating circuit is higher.
Summary of the invention
The problem that the present invention solves is the supply voltage of existing oscillating circuit when larger, and the power consumption of oscillating circuit is higher.
For addressing the above problem, the invention provides a kind of oscillating circuit, comprising: inverting amplifier and buffer, the output of described inverting amplifier connects the input of described buffer, also comprises: band-gap reference circuit and electric current provide circuit;
Described band-gap reference circuit comprises current mirroring circuit, described band-gap reference circuit is suitable for input supply voltage, described current mirroring circuit comprises: first input end, the second input, the first output and the second output, the first input end of described current mirroring circuit and the second input are all suitable for inputting described supply voltage, and the first output of described current mirroring circuit is suitable for output reference electric current;
Described electric current provides circuit to be suitable for exporting the power end of the first source current to described inverting amplifier, and output second source electric current is to the power end of described buffer, and described the first source current is all relevant to described reference current with second source electric current.
Optionally, described current mirroring circuit comprises: a PMOS pipe and the 2nd PMOS manage;
The source electrode of a described PMOS pipe is the first input end of described current mirroring circuit, and the grid of a described PMOS pipe connects the drain electrode of a described PMOS pipe and the grid of the 2nd PMOS pipe the first output as described current mirroring circuit;
The source electrode of described the 2nd PMOS pipe is the second input of described current mirroring circuit, the second output that the drain electrode of described the 2nd PMOS pipe is described current mirroring circuit.
Optionally, described band-gap reference circuit also comprises: the first triode, the second triode and the first resistance;
The first end of described the first resistance connects the first output of described current mirroring circuit;
The emitter of described the first triode connects the second end of described the first resistance;
The emitter of described the second triode connects the second output of described current mirroring circuit;
The base stage of the base stage of described the first triode, the collector electrode of the first triode, the second triode and the equal ground connection of collector electrode of the second triode.
Optionally, described electric current provides circuit to comprise: the 3rd PMOS pipe and the 4th PMOS manage;
The source electrode of described the 3rd PMOS pipe is suitable for inputting described supply voltage, and the grid of described the 3rd PMOS pipe connects the first output of described current mirroring circuit, and the drain electrode of described the 3rd PMOS pipe is suitable for exporting described the first source current;
The source electrode of described the 4th PMOS pipe is suitable for inputting described supply voltage, and the grid of described the 4th PMOS pipe connects the first output of described current mirroring circuit, and the drain electrode of described the 4th PMOS pipe is suitable for exporting described second source electric current.
Optionally, described oscillating circuit also comprises: level shifting circuit; The voltage that described level shifting circuit is suitable for the output to the described buffer processing of boosting.
Optionally, described oscillating circuit also comprises: the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, a NMOS pipe, the 2nd NMOS pipe and inverter;
The source electrode of described the 5th PMOS pipe is suitable for inputting described supply voltage, and the grid of described the 5th PMOS pipe connects the first output of described current mirroring circuit, and the drain electrode of described the 5th PMOS pipe connects the power end of described inverter;
The source electrode of described the 6th PMOS pipe is suitable for inputting described supply voltage, the grid of described the 6th PMOS pipe connects the drain electrode of described the 7th PMOS pipe and the drain electrode of described the 2nd NMOS pipe, and the drain electrode of described the 6th PMOS pipe connects the drain electrode of grid and a NMOS pipe of described the 7th PMOS pipe;
The source electrode of described the 7th PMOS pipe is suitable for inputting described supply voltage;
The grid of a described NMOS pipe connects the output of described inverter, and the source electrode of a described NMOS pipe connects source electrode the ground connection of the 2nd NMOS pipe;
The input of described inverter connects described the 2nd grid of NMOS pipe and the output of described buffer.
Optionally, described oscillating circuit also comprises: the second resistance, the 3rd resistance, the first electric capacity, the second electric capacity and crystal oscillator;
The first end of described the second resistance connects input, the first end of crystal oscillator and the first end of the first electric capacity of described inverting amplifier, and the second end of described the second resistance connects described the 3rd first end of resistance and the output of described inverting amplifier;
The second end of described the 3rd resistance connects the second end of described crystal oscillator and the first end of the second electric capacity;
The second end ground connection of the second end of described the first electric capacity and the second electric capacity.
Optionally, the current value of described the first source current and the current value of described reference current are proportional, and the current value of described second source electric current and the current value of described reference current are proportional.
Compared with prior art, in oscillating circuit of the present invention, the input current of the power end of inverting amplifier and buffer can not raise and become large with the supply voltage of oscillating circuit, and its power consumption and supply voltage are substantially irrelevant, thereby have reduced the overall power of oscillating circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing oscillating circuit;
Fig. 2 is a structural representation of oscillating circuit of the present invention;
Fig. 3 is another structural representation of oscillating circuit of the present invention.
Embodiment
Continue with reference to figure 1, inverting amplifier 1 in existing oscillating circuit is directly connected supply voltage VDD with the power end of buffer 2, in the time that supply voltage VDD is larger, flow into the also corresponding increase of electric current of the power end of inverting amplifier 1 and buffer 2, finally cause the power consumption of oscillating circuit to increase.For the problems referred to above, the present inventor proposes a kind of new oscillating circuit.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
As shown in Figure 2, the oscillating circuit that the embodiment of the present invention provides comprises: inverting amplifier 1, buffer 2, band-gap reference circuit 3 and electric current provide circuit 4.
The output of inverting amplifier 1 connects the input of buffer 2.
Band-gap reference circuit 3 is suitable for input supply voltage VDD, and band-gap reference circuit 3 comprises current mirroring circuit 31.Current mirroring circuit 31 comprises first input end, the second input, the first output and the second output, the first input end of current mirroring circuit 31 and the second input are all suitable for inputting described supply voltage VDD, and the first output of current mirroring circuit 31 is suitable for output reference electric current I A.
Electric current provides circuit 4 to be suitable for exporting the power end of the first source current I1 to inverting amplifier 1, and output second source electric current I 2 is to the power end of buffer 2.The first source current I1 is relevant to reference current IA with second source electric current I 2.
The present embodiment does not use the characteristic that band-gap reference circuit can output reference voltage, but utilize the reference current IA that in band-gap reference circuit 3, current mirroring circuit 31 is exported relevant with the element of band-gap reference circuit 3, and with the substantially irrelevant feature of the size of supply voltage VDD.The the first source current I1 that provides circuit 4 to export due to the electric current of the present embodiment is all relevant to reference current IA with the first source current I1, so the input current of the power end of inverting amplifier and the power end of buffer is also only relevant to reference current IA, and substantially irrelevant with the size of supply voltage VDD.In the time that supply voltage VDD is larger, the input current of the power end of inverting amplifier and the power end of buffer can not increase thereupon, thereby has reduced the power consumption of oscillating circuit.
The source electrode of the one PMOS pipe MP1 is the first input end of current mirroring circuit 31, and drain electrode and the 2nd PMOS that the grid of a PMOS pipe MP1 connects a PMOS pipe MP1 manage the grid of MP2 the first output as current mirroring circuit 31.
The source electrode of the 2nd PMOS pipe MP2 is the second input of current mirroring circuit 31, and the drain electrode of the 2nd PMOS pipe MP2 is the second output of current mirroring circuit 31.
The size ratio of a described PMOS pipe MP1 and the 2nd PMOS pipe MP2 can be 1:1, or other arbitrary proportions.
In the present embodiment, band-gap reference circuit 3 also comprises: the first triode Q1, the second triode Q2 and the first resistance R 1.
The first end of the first resistance R 1 connects the first output of described current mirroring circuit 31, is suitable for input reference electric current I
a.
The emitter of the first triode Q1 connects the second end of described the first resistance R 1.
The emitter of the second triode Q2 connects the second output of described current mirroring circuit 31.
The base stage of the first triode Q1, the collector electrode of the first triode Q1, the base stage of the second triode Q2 and the equal ground connection GND of the collector electrode of the second triode Q2.
Voltage-current characteristic from PN junction:
I
dfor the electric current in PN junction, I
sfor the reverse saturation current of PN junction, V
dfor the forward voltage drop of PN junction, V
tfor thermal voltage constant, q is electron charge, and K is Boltzmann constant, and T is absolute temperature.
In Fig. 2, a PMOS pipe MP1 drain electrode is node A with the tie point of the first resistance R 1, and the 2nd PMOS pipe MP2 drain electrode is Node B with the tie point of the second triode Q2 emitter, and the tie point of the first resistance R 1 and the first triode Q1 emitter is node C:
I
afor the current value of reference current, I
bfor the current value of Node B, V
bfor the magnitude of voltage of Node B, V
cfor the magnitude of voltage of node C.
Reference current I
acurrent value:
I
A=(V
A-V
C)/R (4)
V
afor the magnitude of voltage of node A, R is the resistance value of the first resistance R 1.
In the time of a PMOS pipe MP1 and the 2nd PMOS pipe MP2 measure-alike:
I
A=I
B (5)
V
A≈V
B (6)
Can be learnt by formula (1) to formula (6):
I
A=I
B=(V
T/R)lnn (7)
Can be found out reference current I by formula (7)
airrelevant with supply voltage VDD.
Formula (5) and formula (6) are to draw in the case of a PMOS pipe MP1 and the 2nd PMOS pipe MP2 measure-alike, in the time that the size ratio of a PMOS pipe MP1 and the 2nd PMOS pipe MP2 is other ratios, only need be multiplied by corresponding multiple, can draw equally the formula that reference current IA and supply voltage VDD are irrelevant, repeat no more herein.
So, the reference current I that the current mirroring circuit 31 described in the present embodiment is exported
arelevant with the resistance value of the first resistance R 1 and the size of the first triode Q1 and the second triode Q2, and basic have nothing to do with supply voltage VDD.
What deserves to be explained is, the band-gap reference circuit (bandgap) described in the present embodiment and the current mirroring circuit in band-gap reference circuit also can be realized with other existing band-gap reference circuits and the current mirroring circuit being positioned at wherein, do not limit herein.
Continue with reference to figure 2, electric current provides circuit 4 to comprise: the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4.
The source electrode of described the 3rd PMOS pipe MP3 is suitable for inputting described supply voltage VDD, and the grid of described the 3rd PMOS pipe MP3 connects the first output of described current mirroring circuit 31, and the drain electrode of described the 3rd PMOS pipe MP3 is suitable for exporting described the first source current I1.
The source electrode of described the 4th PMOS pipe MP4 is suitable for inputting described supply voltage VDD, and the grid of described the 4th PMOS pipe MP4 connects the first output of described current mirroring circuit 31, and the drain electrode of described the 4th PMOS pipe is suitable for exporting described second source electric current I 2.
The one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4 have formed current-mirror structure, and electric current and the reference current IA of the drain electrode output of the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 are proportional.
The current value of the first source current I1 and second source electric current I 2 depends on the size of current value and the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 of reference current IA, therefore, can be according to the required current value of the normal work of inverting amplifier 1 and buffer 2 current value to reference current IA and the size of the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 set.
Oscillating circuit described in the present embodiment can also comprise: the second resistance R 2, the 3rd resistance R 3, the first capacitor C 1, the second capacitor C 2 and crystal oscillator Z.
The first end of described the second resistance R 2 connects input, the first end of crystal oscillator Z and the first end of the first capacitor C 1 of described inverting amplifier 1, and the second end of described the second resistance R 2 connects the first end of described the 3rd resistance R 3 and the output of described inverting amplifier 1.
The second end of described the 3rd resistance R 3 connects the second end of described crystal oscillator Z and the first end of the second capacitor C 2.The second end ground connection GND of the second end of described the first capacitor C 1 and the second capacitor C 2.
As shown in Figure 3, the oscillating circuit described in the present embodiment can also comprise: level shifting circuit 5.The voltage that level shifting circuit 5 is suitable for the output to the described buffer processing of boosting.
The voltage of the power end of the power end of inverting amplifier 1 and buffer 2 can be less than supply voltage VDD because of the setting of the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4, in the time that supply voltage VDD is larger, because of the 3rd PMOS pipe and the 4th PMOS, to manage the voltage influence that voltage that MP4 reduces exports buffer 2 less, but, when supply voltage VDD hour, the voltage influence that can export buffer 2 is larger.Level shifting circuit 5 can be to the processing of boosting of the voltage of the output of described buffer, and the voltage of having avoided the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 to cause reduces problem.Level shifting circuit 5 can be increased to the voltage of the output of buffer with the magnitude of voltage of supply voltage VDD and equate.
Level shifting circuit 5 can comprise: the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, a NMOS pipe MN1, the 2nd NMOS pipe MN2 and inverter 51.
The source electrode of described the 5th PMOS pipe MP5 is suitable for inputting described supply voltage VDD, and the grid of described the 5th PMOS pipe MP5 connects the first output of described current mirroring circuit 31, and the drain electrode of described the 5th PMOS pipe MP5 connects the power end of described inverter 51.
The source electrode of described the 6th PMOS pipe MP6 is suitable for inputting described supply voltage VDD, drain electrode and described the 2nd NMOS that the grid of described the 6th PMOS pipe MP6 connects described the 7th PMOS pipe MP7 manage the drain electrode of MN2 the output OUT as described oscillating circuit, and the drain electrode of described the 6th PMOS pipe MP6 connects the drain electrode of grid and the NMOS pipe MN1 of described the 7th PMOS pipe MP7;
The source electrode of described the 7th PMOS pipe MP7 is suitable for inputting described supply voltage VDD;
The grid of a described NMOS pipe MN1 connects the output of described inverter, and the source electrode of a described NMOS pipe MN1 connects source electrode the ground connection GND of the 2nd NMOS pipe MN2;
The input of described inverter 51 connects described the 2nd NMOS pipe grid of MN2 and the output of described buffer 2.
In the level shifting circuit 5 that the present embodiment provides, the drain electrode of the 5th PMOS pipe MP5 can be exported the 3rd source current I3, similar with the first source current I1 and second source electric current I 2, the 3rd source current I3 is relevant to reference current IA, also can, because the supply voltage VDD compared with large becomes greatly, further not reduce the power consumption of pierce circuit so flow into the electric current of the power end of inverter.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (8)
1. an oscillating circuit, comprising: inverting amplifier and buffer, and the output of described inverting amplifier connects the input of described buffer, it is characterized in that, also comprises: band-gap reference circuit and electric current provide circuit;
Described band-gap reference circuit comprises current mirroring circuit, described band-gap reference circuit is suitable for input supply voltage, described current mirroring circuit comprises: first input end, the second input, the first output and the second output, the first input end of described current mirroring circuit and the second input are all suitable for inputting described supply voltage, and the first output of described current mirroring circuit is suitable for output reference electric current;
Described electric current provides circuit to be suitable for exporting the power end of the first source current to described inverting amplifier, and output second source electric current is to the power end of described buffer, and described the first source current is all relevant to described reference current with second source electric current.
2. oscillating circuit as claimed in claim 1, is characterized in that, described current mirroring circuit comprises: a PMOS pipe and the 2nd PMOS pipe;
The source electrode of a described PMOS pipe is the first input end of described current mirroring circuit, and the grid of a described PMOS pipe connects the drain electrode of a described PMOS pipe and the grid of the 2nd PMOS pipe the first output as described current mirroring circuit;
The source electrode of described the 2nd PMOS pipe is the second input of described current mirroring circuit, the second output that the drain electrode of described the 2nd PMOS pipe is described current mirroring circuit.
3. oscillating circuit as claimed in claim 1, is characterized in that, described band-gap reference circuit also comprises: the first triode, the second triode and the first resistance;
The first end of described the first resistance connects the first output of described current mirroring circuit;
The emitter of described the first triode connects the second end of described the first resistance;
The emitter of described the second triode connects the second output of described current mirroring circuit;
The base stage of the base stage of described the first triode, the collector electrode of the first triode, the second triode and the equal ground connection of collector electrode of the second triode.
4. oscillating circuit as claimed in claim 1, is characterized in that, described electric current provides circuit to comprise: the 3rd PMOS pipe and the 4th PMOS pipe;
The source electrode of described the 3rd PMOS pipe is suitable for inputting described supply voltage, and the grid of described the 3rd PMOS pipe connects the first output of described current mirroring circuit, and the drain electrode of described the 3rd PMOS pipe is suitable for exporting described the first source current;
The source electrode of described the 4th PMOS pipe is suitable for inputting described supply voltage, and the grid of described the 4th PMOS pipe connects the first output of described current mirroring circuit, and the drain electrode of described the 4th PMOS pipe is suitable for exporting described second source electric current.
5. oscillating circuit as claimed in claim 1, is characterized in that, also comprises: level shifting circuit; The voltage that described level shifting circuit is suitable for the output to the described buffer processing of boosting.
6. oscillating circuit as claimed in claim 1, is characterized in that, also comprises: the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, a NMOS pipe, the 2nd NMOS pipe and inverter;
The source electrode of described the 5th PMOS pipe is suitable for inputting described supply voltage, and the grid of described the 5th PMOS pipe connects the first output of described current mirroring circuit, and the drain electrode of described the 5th PMOS pipe connects the power end of described inverter;
The source electrode of described the 6th PMOS pipe is suitable for inputting described supply voltage, the grid of described the 6th PMOS pipe connects the drain electrode of described the 7th PMOS pipe and the drain electrode of described the 2nd NMOS pipe, and the drain electrode of described the 6th PMOS pipe connects the drain electrode of grid and a NMOS pipe of described the 7th PMOS pipe;
The source electrode of described the 7th PMOS pipe is suitable for inputting described supply voltage;
The grid of a described NMOS pipe connects the output of described inverter, and the source electrode of a described NMOS pipe connects source electrode the ground connection of the 2nd NMOS pipe;
The input of described inverter connects described the 2nd grid of NMOS pipe and the output of described buffer.
7. oscillating circuit as claimed in claim 1, is characterized in that, also comprises: the second resistance, the 3rd resistance, the first electric capacity, the second electric capacity and crystal oscillator;
The first end of described the second resistance connects input, the first end of crystal oscillator and the first end of the first electric capacity of described inverting amplifier, and the second end of described the second resistance connects described the 3rd first end of resistance and the output of described inverting amplifier;
The second end of described the 3rd resistance connects the second end of described crystal oscillator and the first end of the second electric capacity;
The second end ground connection of the second end of described the first electric capacity and the second electric capacity.
8. oscillating circuit as claimed in claim 1, is characterized in that, the current value of described the first source current and the current value of described reference current are proportional, and the current value of described second source electric current and the current value of described reference current are proportional.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410078704.0A CN103825556B (en) | 2014-03-05 | 2014-03-05 | Oscillating circuit |
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| CN201410078704.0A CN103825556B (en) | 2014-03-05 | 2014-03-05 | Oscillating circuit |
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| CN103825556A true CN103825556A (en) | 2014-05-28 |
| CN103825556B CN103825556B (en) | 2017-01-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106794488A (en) * | 2014-08-29 | 2017-05-31 | 株式会社村田制作所 | The driving method of oscillating circuit and oscillating circuit |
| CN106936385A (en) * | 2015-12-31 | 2017-07-07 | 无锡华润矽科微电子有限公司 | The crystal oscillating circuit of low-power consumption Width funtion |
| CN112600518A (en) * | 2021-01-06 | 2021-04-02 | 北京中科芯蕊科技有限公司 | Automatic amplitude control type crystal oscillator |
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| CN102931917A (en) * | 2012-11-20 | 2013-02-13 | 上海宏力半导体制造有限公司 | Method for determining oscillation-starting time of crystal oscillator, oscillation-starting detection circuit and clock output circuit |
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| CN202306376U (en) * | 2011-11-02 | 2012-07-04 | 四川和芯微电子股份有限公司 | Reference current source circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106794488A (en) * | 2014-08-29 | 2017-05-31 | 株式会社村田制作所 | The driving method of oscillating circuit and oscillating circuit |
| CN106794488B (en) * | 2014-08-29 | 2019-07-05 | 株式会社村田制作所 | The driving method of oscillating circuit and oscillating circuit |
| CN106936385A (en) * | 2015-12-31 | 2017-07-07 | 无锡华润矽科微电子有限公司 | The crystal oscillating circuit of low-power consumption Width funtion |
| CN112600518A (en) * | 2021-01-06 | 2021-04-02 | 北京中科芯蕊科技有限公司 | Automatic amplitude control type crystal oscillator |
| CN112600518B (en) * | 2021-01-06 | 2024-02-27 | 北京中科芯蕊科技有限公司 | Automatic amplitude control type crystal oscillator |
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| CN103825556B (en) | 2017-01-11 |
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