CN103780258A - Digital double-line delay phase lock loop - Google Patents
Digital double-line delay phase lock loop Download PDFInfo
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- CN103780258A CN103780258A CN201410043906.1A CN201410043906A CN103780258A CN 103780258 A CN103780258 A CN 103780258A CN 201410043906 A CN201410043906 A CN 201410043906A CN 103780258 A CN103780258 A CN 103780258A
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Abstract
The invention discloses a digital double-line delay phase lock loop which comprises a delay cell remainder line, a phase detector, a locking control cell and two delay lines. The two delay lines include the delay line composed of a plurality of delay cells and the compensation line composed of a plurality of compensation delay cells, and the delay cells include the rough adjustment line delay cells and the fine adjustment line delay cells, wherein the rough adjustment line delay cells and the fine adjustment line delay cells are arranged in a stagger and reversal mode. A reference clock sequentially passes through the rough adjustment line delay cells and the fine adjustment line delay cells, the rough adjustment line delay cells are used for inputting the reference clock, and the fine adjustment line delay cells are used for outputting the reference clock; meanwhile, the reference clock passes through the compensation delay cells of the compensation line, the phase detector compares a clock output by the compensation line with the reference clock and outputs the phase detecting result, the output clock is adjusted by the locking control cell according to the phase detecting result, if the output clock is ahead of the reference clock, the delay time is prolonged, and the output clock is delayed, the reverse is also true till the phase detector detects that the two clock signals are synchronous, and system locking is carried out.
Description
Technical field
The present invention relates to DLL, relate in particular to a kind of digital double-stranded delay phase-locked loop.
Background technology
DLL is the abbreviation of Delay Lock Loop, and the effect of DLL is the phase place of adjusting a clock signal, is usually used in the clock synchronous of processor storage.
For strand DLL, reference clock is connected on the input of all delay cells simultaneously, phase discriminator compares the phase place of reference clock and feedback clock, if feedback clock is faster than reference clock, control shift register moves to left, strengthen time of delay, until reference clock and feedback clock are synchronous, vice versa.Shortcoming is that locking time is long, and precision is low.
For analog D LL, phase discriminator is reference clock and feedback clock phase place relatively, the electric current of controlling charge pump according to phase difference generation control signal is to filter capacity charge or discharge, low pass filter filters the high-frequency signal of phase discriminator and charge pump generation, generate and control voltage, thereby by changing the phase place that changes feedback clock time of delay of this magnitude of voltage adjustment voltage controlled delay line.Shortcoming is that power consumption is large, and speed is slow.
At a high speed, in the communication system of parallel chip chamber, in order to realize the clock synchronous of each interchannel, and complete reliable data sampling, high speed orthogonal clock generation system has been proposed to urgent demand.And in order to coordinate the requirement of different communication protocol, need to provide the range of application that the support of different frequency and the orthogonal clock that can expand is produced to system.
Summary of the invention
In order to solve the problems of the technologies described above, the object of the present invention is to provide digital double-stranded delay phase-locked loop, adopt high speed orthogonal clock system, guarantee the requirements for high precision of orthogonal clock, can meet the requirement of high speed, wide range of frequencies locking, the variation of technique, voltage, temperature is had to very strong adaptability and reliability.
Specifically, the invention discloses a kind of digital double-stranded delay phase-locked loop, the double-stranded delay phase-locked loop of this numeral comprises delay cell remainder chain, phase discriminator, locking control unit and two delay chains, wherein, article two, delay chain comprises the compensated chain that the delay chain that is made up of multiple delay cell and Multilevel compensating delay cell form, and delay cell comprises staggered coarse adjustment chain delay cell and the fine tuning chain delay cell of putting upside down setting;
Reference clock is from first delay cell input of delay chain, successively through coarse adjustment chain delay cell and fine tuning chain delay cell, then enter next delay cell, the input of coarse adjustment chain delay cell, the output of fine tuning chain delay cell, enter phase discriminator or enter phase discriminator by delay cell remainder chain through the delayed selection culture, simultaneously, reference clock is through the Multilevel compensating delay cell of compensated chain, enter phase discriminator through delay compensation, by phase discriminator, compensated chain output clock and reference clock are compared, output identified result, adjust output clock according to this identified result by locking control unit, if output clock is led over reference clock, be increased time of delay, output clock is postponed, vice versa, until phase discriminator is identified two clock signal synchronizations, system lock.
Article two, the multiple delay cell of delay chain and Multilevel compensating delay cell equidistantly arrange, to obtain desirable duty ratio.
The data wire that coarse adjustment chain delay cell and fine tuning chain delay cell are exported is respectively Bus structure.
Delay cell in delay cell remainder chain is identical with coarse adjustment chain delay cell structure.
Reference clock is a pair of differential clocks.
The metal routing length of differential clock signal is the same.
The difference of output clock and reference clock is locked in the scope that is less than half clock cycle.
The double-stranded phase-lock technique that postpones of a kind of numeral, comprises the steps:
1) two delay chains are set, comprise the compensated chain that the delay chain that is made up of multiple delay cell and Multilevel compensating delay cell form;
2) staggered coarse adjustment chain delay cell and the fine tuning chain delay cell that each delay cell is set put upside down;
3) reference clock is from first delay cell input of delay chain, successively through coarse adjustment chain delay cell and fine tuning chain delay cell, then enter next delay cell, the input of coarse adjustment chain delay cell, the output of fine tuning chain delay cell, enter phase discriminator or enter phase discriminator by delay cell remainder chain through the delayed selection culture, simultaneously, reference clock is through the Multilevel compensating delay cell of compensated chain, enter phase discriminator through delay compensation, by phase discriminator, compensated chain output clock and reference clock are compared to output identified result;
4) adjust output clock according to this identified result by locking control unit, if output clock is led over reference clock, be increased time of delay, output clock is postponed, and vice versa, until phase discriminator is identified two clock signal synchronizations, system lock.
A kind of processor or memory and clock synchronous device that adopts above-mentioned DDL.
Technique effect of the present invention:
Mainly for differential clocks CKN/CKP walk circuit warp, keep the synchronous of two signals, although through different delay cell, still can obtain good synchronous effect
Accompanying drawing explanation
The double-stranded delay phase-locked loop block diagram of Fig. 1 the present invention numeral;
Fig. 2 coarse adjustment chain of the present invention delay cell strand circuit diagram;
Fig. 3 coarse adjustment chain of the present invention delay cell difference channel figure.
Wherein, Reference numeral
1 is locking control unit;
2 is phase discriminator;
3 is the delayed selection culture;
4 is delay compensation;
5 is delay cell remainder chain;
6 is compensating delay unit;
7 is coarse adjustment chain delay cell;
8 is fine tuning chain delay cell.
Embodiment
The double-stranded delay phase-locked loop DLL of numeral of the present invention, referring to Fig. 1, main functional unit comprises: compensating delay unit 6(DelayLine), coarse adjustment chain delay cell 7(Delaycell CT), fine tuning chain delay cell 8(Delaycell FT), phase discriminator 2(PhaseDetect), delay compensation 4, the delayed selection culture 3, delay cell remainder chain 5 and locking control unit 1(LockControl).
Article two, delay chain comprises the compensated chain that the delay chain that is made up of multiple delay cell and Multilevel compensating delay cell 6 form, delay cell adopts duplex structure, comprises coarse adjustment chain delay cell 7(Delaycell CT) and fine tuning chain delay cell 8(Delaycell FT).The benefit of this duplex structure is can reduce locking time and reduce static phase error.Be to evaluate a DLL to design fine or not key parameter locking time.
In order to realize orthogonal clock generating, design adopts identical 4 delay cells, and 4 delay cells adopt identical coarse adjustment code and the control of fine tuning code, and the precision of coarse adjustment and fine tuning is 4 times of wall scroll delay chain.
The a pair of differential clocks of reference clock CKP/CKN(), CKP/CKN is from the input of first delay cell Delaycell, successively through coarse adjustment chain delay cell 7(Delaycell CT) and fine tuning chain delay cell 8(Delaycell FT), then entering next stage postpones, coarse adjustment chain delay cell 7(Delaycell CT) enter, fine tuning chain delay cell 8(Delaycell FT) go out, coarse adjustment chain delay cell 7(Delaycell CT) quick lock in of the realization numeral double-stranded delay phase-locked loop DLL itself of step-length greatly, after the double-stranded delay phase-locked loop DLL quick lock in of numeral, by coarse adjustment chain delay cell 7(Delaycell CT) adjustment code fallback mechanism and fine tuning chain delay cell 8(Delaycell FT) meticulous adjusting realize the high accuracy again locking of digital double-stranded delay phase-locked loop DLL, thereby meet broadband quick lock in and high-precision characteristic.Referring to Fig. 1, coarse adjustment chain delay cell 7(DelaycellCT) and fine tuning chain delay cell 8(DelaycellFT) staggered being placed upside down, it is that CKP/CKN postpones output via identical path from afterbody completely that first benefit is set like this, second benefit is that differential clocks directly enters next stage delay along shortest path on delay chain, and the 3rd benefit is the equidistant requirement that is conducive to keep different inter-stages.
In addition, coarse adjustment chain delay cell 7(Delaycell CT)/fine tuning chain delay cell 8(Delaycell FT) also export respectively 8 position datawires, due to coarse adjustment chain delay cell 7(Delaycell CT)/fine tuning chain delay cell 8(Delaycell FT) be placed upside down, therefore, when data output, all connect by the horizontal main data line being placed between unit, this wire laying mode is the structure of a Bus.
It should be noted that this delay chain path, all strictly follow principle of equidistance between every grade, delay chain is equidistantly placed, to obtain desirable duty ratio.In order to guarantee that delay cell Delaycell phase differences at different levels are 90 degree, the structure of delays at different levels needs consistent, and cabling needs evenly, keeps differential signal path consistent.
Meanwhile, the reference clock CKP/CKN of input also pass through other one by compensating delay unit 6(DelayLine) compensated chain that forms, arrive the output of this delay chain.This is that intrinsic postpones the impact of (coarse adjustment code and fine tuning code are the delay of 0 o'clock delay cell), specially designed 4 grades of compensated chains when compensating high frequency and to use.
CKP/CKN(differential clocks) respectively from above-mentioned two delay chains output, reference clock CKP5/CKN5 enters phase discriminator 2 through delay compensation 4, directly enter phase discriminator 2 and be compared clock CKP4/CKN4 through the delayed selection culture 3, or enter phase discriminator 2 by delay cell remainder chain 5.
In this process, between a pair of differential signal, track lengths need keep highly consistent, illustrate, compensating delay unit 6(DelayLine) output signal while outputing to delay compensation 4, because CKP is nearer than CKN to delay compensation 4, therefore in layout design, need deliberately to elongate the cabling of CKP, to guarantee the coupling of two differential lines.
In order to make phase error more accurate, when coarse adjustment completes after locking, a lock detecting signal is by the low height that is set to, the fine tuning process that precision is higher starts, until system is finally locked, the difference of output clock and reference clock is locked in the scope that is less than half clock cycle, and the error of output clock and reference clock is less than the dead band of phase discriminator 2.
To guarantee under the condition of precision and lock speed in order solving, to meet the phase place locking of better frequency, at fine tuning chain delay cell 8(Delaycell FT) afterwards, adopt delay cell remainder chain 5 structures.Delay cell in delay cell remainder chain 5 adopts and coarse adjustment chain delay cell 7(Delaycell CT) identical structure.
After coarse adjustment process, delay cell remainder chain 5 realizes 1 under the control of remainder adjustment code, 2, 3, 4 grades of coarse adjustment chain delay cell 7(Delaycell CT) delay regulate, as the 4 grades of coarse adjustment chain delay cell 7(Delaycell CT that delay to reach of delay cell remainder chain 5) time, carry when 5 zero clearing of delay cell remainder chain, increase a coarse adjustment code CT, so guaranteed in whole coarse adjustment process with a coarse adjustment chain delay cell 7(Delaycell CT) precision regulate continuously, in the time reaching coarse adjustment locking, utilize the delayed selection culture 3 to walk around the delay of delay cell remainder chain 5, and 3 delays own are selected in compensating delay in the time of clock phase discrimination.
At ensuing two unit phase discriminator 2(PD) and locking control unit 1(LockControl), differential signal is preserved symmetry still, until differential clocks enters locking control unit 1(LockControl).
Reference clock is through 4 grades of compensating delay unit 6(Delayline) after, by phase discriminator 2 by compensating delay unit 6(Delayline) output clock and reference clock make comparisons, locking control unit 1(LockControl) adjust output clock according to identified result, if output clock is led over reference clock, be increased time of delay, output clock is postponed, and vice versa, until phase discriminator 2 identifies that two signals are synchronous, system lock.
Fig. 2 coarse adjustment chain of the present invention delay cell strand circuit diagram; Fig. 3 coarse adjustment chain of the present invention delay cell difference channel figure.
To sum up, a kind of digital double-stranded delay phase-locked loop, the double-stranded delay phase-locked loop of this numeral comprises delay cell remainder chain 5, phase discriminator 2, locking control unit 1 and two delay chains, wherein, article two, delay chain comprises the delay chain and the Multilevel compensating delay cell 6(Delayline that are made up of multiple delay cell) compensated chain that forms, delay cell comprises the staggered coarse adjustment chain delay cell 7(Delaycell CT that puts upside down setting) and fine tuning chain delay cell 8(Delaycell FT);
Reference clock is from first delay cell input of delay chain, successively through coarse adjustment chain delay cell 7(Delaycell CT) and fine tuning chain delay cell 8(Delaycell FT), then enter next delay cell, coarse adjustment chain delay cell 7(Delaycell CT) input, fine tuning chain delay cell 8(Delaycell FT) output, enter phase discriminator 2 or enter phase discriminator 2 by delay cell remainder chain 5 through the delayed selection culture 3, simultaneously, reference clock is through the Multilevel compensating delay cell 6(Delayline of compensated chain), enter phase discriminator 2 through delay compensation 4, by phase discriminator 2, compensated chain output clock and reference clock are compared, output identified result, according to this identified result by locking control unit 1(LockControl) adjust output clock, if output clock is led over reference clock, be increased time of delay, output clock is postponed, vice versa, until phase discriminator 2 is identified two clock signal synchronizations, system lock.
Article two, the multiple delay cell of delay chain and Multilevel compensating delay cell 6(Delayline) equidistantly arrange, to obtain desirable duty ratio.
Coarse adjustment chain delay cell 7(Delaycell CT) and fine tuning chain delay cell 8(Delaycell FT) respectively output data wire be Bus structure.
Delay cell in delay cell remainder chain 5 and coarse adjustment chain delay cell 7(Delaycell CT) structure is identical.
Reference clock is a pair of differential clocks.The metal routing length of differential clock signal is the same.
The difference of output clock and reference clock is locked in the scope that is less than half clock cycle.
The present invention is the double-stranded phase-lock technique that postpones of open a kind of numeral also, comprises the steps:
1) two delay chains are set, comprise the delay chain and the Multilevel compensating delay cell 6(Delayline that are formed by multiple delay cell) compensated chain that forms;
2) the staggered coarse adjustment chain delay cell 7(Delaycell CT that each delay cell is set that puts upside down) and fine tuning chain delay cell 8(Delaycell FT);
3) reference clock is from first delay cell input of delay chain, successively through coarse adjustment chain delay cell 7(Delaycell CT) and fine tuning chain delay cell 8(Delaycell FT), then enter next delay cell, coarse adjustment chain delay cell 7(Delaycell CT) input, fine tuning chain delay cell 8(Delaycell FT) output, enter phase discriminator 2 or enter phase discriminator 2 by delay cell remainder chain 5 through the delayed selection culture 3, simultaneously, reference clock is through the Multilevel compensating delay cell 6(Delayline of compensated chain), enter phase discriminator 2 through delay compensation 4, by phase discriminator 2, compensated chain output clock and reference clock are compared, output identified result,
4) according to this identified result by locking control unit 1(LockControl) adjust output clock, if output clock is led over reference clock, be increased time of delay, output clock is postponed, vice versa, until phase discriminator 2 is identified two clock signal synchronizations, system lock.
Adopt processor or memory or the clock synchronous device of above-mentioned DDL.
Claims (10)
1. the double-stranded delay phase-locked loop of numeral, it is characterized in that, the double-stranded delay phase-locked loop of this numeral comprises delay cell remainder chain, phase discriminator, locking control unit and two delay chains, wherein, article two, delay chain comprises the compensated chain that the delay chain that is made up of multiple delay cell and Multilevel compensating delay cell form, and delay cell comprises staggered coarse adjustment chain delay cell and the fine tuning chain delay cell of putting upside down setting;
Reference clock is from first delay cell input of delay chain, successively through coarse adjustment chain delay cell and fine tuning chain delay cell, then enter next delay cell, the input of coarse adjustment chain delay cell, the output of fine tuning chain delay cell, enter phase discriminator or enter phase discriminator by delay cell remainder chain through the delayed selection culture, simultaneously, reference clock is through the Multilevel compensating delay cell of compensated chain, enter phase discriminator through delay compensation, by phase discriminator, compensated chain output clock and reference clock are compared, output identified result, adjust output clock according to this identified result by locking control unit, if output clock is led over reference clock, be increased time of delay, output clock is postponed, vice versa, until phase discriminator is identified two clock signal synchronizations, system lock.
2. digital double-stranded delay phase-locked loop as claimed in claim 1, is characterized in that, two multiple delay cell of delay chain and Multilevel compensating delay cell equidistantly arrange, to obtain desirable duty ratio.
3. digital double-stranded delay phase-locked loop as claimed in claim 1, is characterized in that, the data wire that coarse adjustment chain delay cell and fine tuning chain delay cell are exported is respectively Bus structure.
4. digital double-stranded delay phase-locked loop as claimed in claim 1, is characterized in that, the delay cell in delay cell remainder chain is identical with coarse adjustment chain delay cell structure.
5. digital double-stranded delay phase-locked loop as claimed in claim 1, is characterized in that, reference clock is a pair of differential clocks.
6. digital double-stranded delay phase-locked loop as claimed in claim 5, is characterized in that, the metal routing length of differential clock signal is the same.
7. digital double-stranded delay phase-locked loop as claimed in claim 1, is characterized in that, the difference of output clock and reference clock is locked in the scope that is less than half clock cycle.
8. the double-stranded phase-lock technique that postpones of numeral, is characterized in that, comprises the steps:
1) two delay chains are set, comprise the compensated chain that the delay chain that is made up of multiple delay cell and Multilevel compensating delay cell form;
2) staggered coarse adjustment chain delay cell and the fine tuning chain delay cell that each delay cell is set put upside down;
3) reference clock is from first delay cell input of delay chain, successively through coarse adjustment chain delay cell and fine tuning chain delay cell, then enter next delay cell, the input of coarse adjustment chain delay cell, the output of fine tuning chain delay cell, enter phase discriminator or enter phase discriminator by delay cell remainder chain through the delayed selection culture, simultaneously, reference clock is through the Multilevel compensating delay cell of compensated chain, enter phase discriminator through delay compensation, by phase discriminator, compensated chain output clock and reference clock are compared to output identified result;
4) adjust output clock according to this identified result by locking control unit, if output clock is led over reference clock, be increased time of delay, output clock is postponed, and vice versa, until phase discriminator is identified two clock signal synchronizations, system lock.
9. one kind adopts processor or the memory of claim 1-8 any one.
10. one kind adopts the clock synchronous device of claim 1-8 any one.
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| CN103986443A (en) * | 2014-05-29 | 2014-08-13 | 威盛电子股份有限公司 | Delay line circuit and semiconductor integrated circuit |
| CN108551342A (en) * | 2018-03-20 | 2018-09-18 | 上海集成电路研发中心有限公司 | A kind of delay phase-locked loop with broadband input range |
| CN109933127A (en) * | 2019-03-07 | 2019-06-25 | 中科亿海微电子科技（苏州）有限公司 | Programmable delay cellular construction |
| CN112260686A (en) * | 2020-10-27 | 2021-01-22 | 宁波芯辉科技有限公司 | Low locking error delay chain phase-locked loop |
| CN112787665A (en) * | 2020-12-28 | 2021-05-11 | 珠海全志科技股份有限公司 | Phase-adjustable clock signal generation method and device |
| CN113835332A (en) * | 2021-09-29 | 2021-12-24 | 东南大学 | High-resolution two-stage time-to-digital converter and conversion method |
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| CN103986443A (en) * | 2014-05-29 | 2014-08-13 | 威盛电子股份有限公司 | Delay line circuit and semiconductor integrated circuit |
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| CN113835332A (en) * | 2021-09-29 | 2021-12-24 | 东南大学 | High-resolution two-stage time-to-digital converter and conversion method |
| CN113835332B (en) * | 2021-09-29 | 2022-08-23 | 东南大学 | High-resolution two-stage time-to-digital converter and conversion method |
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