CN104967445B - Phase detection device and phase adjustment method - Google Patents
Phase detection device and phase adjustment method Download PDFInfo
- Publication number
- CN104967445B CN104967445B CN201510245375.9A CN201510245375A CN104967445B CN 104967445 B CN104967445 B CN 104967445B CN 201510245375 A CN201510245375 A CN 201510245375A CN 104967445 B CN104967445 B CN 104967445B
- Authority
- CN
- China
- Prior art keywords
- data
- phase
- sampling value
- value
- data sampling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000001514 detection method Methods 0.000 title claims description 31
- 238000005070 sampling Methods 0.000 claims abstract description 259
- 238000010586 diagram Methods 0.000 description 6
- 238000011084 recovery Methods 0.000 description 6
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 4
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 4
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 4
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 4
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/0055—Synchronisation arrangements determining timing error of reception due to propagation delay
- H04W56/0065—Synchronisation arrangements determining timing error of reception due to propagation delay using measurement of signal travel time
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A phase detecting device and a phase adjusting method. Whether a phase adjustment control signal is output or not is judged according to a first data sampling value, a second data sampling value and a third data sampling value which are generated successively so as to adjust the phase of a sampling clock signal according to a sampling data signal.
Description
Technical field
The present invention relates to a kind of electronic installation, and more particularly to a kind of phase detection device and phase adjusting method.
Background technology
In the receiving terminal of high-speed serial data, in order to correctly obtain data, it is necessary to have a clock signal as sampling number
According to foundation, the frequency of this clock signal must lock the data-signal received with phase.Traditional receiving terminal is to utilize
Clock and data recovery device is to provide such clock signal.
Conventional clock data recovery device utilizes voltage-controlled oscillator (VCO:voltage control oscillator)
Clock signal is provided, by phase detectors according to clock signal sampled data signal, and charge pump is controlled according to sampling value
The discharge and recharge of (charge pump), and then the frequency of control voltage control oscillator adjustment clock signal, and have clock signal
There is correct phase.
Existing phase detectors can be according to adjacent two data sampling value and between this adjacent two data signal side
The sampling value of edge come judge the phase of clock signal for it is leading or fall behind, and according to this control charge pump discharge and recharge, with time
Adjust the phase of clock signal.However as the popularization and progress of the communication technology, the transmission bit rate (bit rate) of data is more
Come higher, the situation of signal attenuation more becomes obvious, and this phase adjustment mode has gradually lost the accuracy of its adjustment, and need to have
More accurately phase adjustment mode, it is unstable and circuit performance declines come circuit caused by avoiding phase difference.
The content of the invention
The present invention provides a kind of phase detection device and phase adjusting method, can correctly adjust sampling clock signal
Phase, circuit caused by avoiding phase difference is unstable and circuit performance declines.
The phase detection device of the present invention, including comparing unit, storage element and processing unit.Wherein comparing unit connects
Collect sample data-signal and caused sampled signal, sampled signal includes the multiple data sampling values being alternately produced and more numbers
According to edge sampling value, the more adjacent data sampling value of comparing unit and data edges sampling value, to produce multiple fiducial values.Storage
Memory cell storage data sampling value, data edges sampling value and fiducial value.Processing unit couples storage element, and foundation is produced in succession
Raw the first data sampling value, the second data sampling value and the 3rd data sampling value judges whether output phase adjustment control letter
Number, to adjust the phase of the sampling clock signal of sampled data signal institute foundation.
The phase adjusting method of the present invention comprises the following steps.Sampled data signal and caused sampled signal are received, is taken
Sample signal includes the multiple data sampling values being alternately produced and multiple data edges sampling values.More adjacent data sampling value
With data edges sampling value, to produce multiple fiducial values.Store data sampling value, data edges sampling value and fiducial value.According to
Judge whether that output phase is adjusted according to caused first data sampling value, the second data sampling value and the 3rd data sampling value in succession
Whole control signal, to adjust the phase of the sampling clock signal of sampled data signal institute foundation.
Based on above-mentioned, the present invention is by according to caused first data sampling value in succession, the second data sampling value and the
Three data sampling values judge whether that output phase adjusts control signal, to adjust the sampling clock of sampled data signal institute foundation
Phase, to be sampled the phase adjustment of clock signal when circuit is relatively stable, and it can more correctly adjust sampling clock signal
Phase, avoid phase difference cause circuit unstable and circuit performance decline.
To enable the features described above of the present invention and advantage to become apparent, special embodiment below, and it is detailed with reference to accompanying drawing
Explanation.
Brief description of the drawings
Fig. 1 is schematically shown as the schematic diagram of the phase detection device of one embodiment of the invention.
Fig. 2 is schematically shown as carrying out data-signal the schematic diagram of over sampling.
Fig. 3 illustrates the schematic diagram of the clock and data recovery device using phase detection device of one embodiment of the invention.
Fig. 4 illustrates the schematic flow sheet of the phase adjusting method of one embodiment of the invention.
Fig. 5 illustrates the schematic flow sheet of the phase adjusting method of another embodiment of the present invention.
Reference numeral explanation
102：Sampling unit
104：Comparing unit
106：Storage element
108：Processing unit
302：Phase detection device
304、306：Charge pump
308：Loop filter
310：Voltage-controlled oscillator
312：Frequency divider
314：Phase-frequency detector
316：Lock detector
318：Switch unit
SF：Reference frequency signal
SC：Clock signal
SW：Switch-over control signal
S1：Data-signal
S2：Sampled signal
S3：Phase adjustment control signals
CLK1、CLK2、CLK3：Sampling clock signal
D-1、D0、D1：Data sampling value
S402~S416, S512：The process step of phase adjusting method
Embodiment
Fig. 1 is schematically shown as the schematic diagram of the phase detection device of one embodiment of the invention.It refer to Fig. 1, phase detection device
Including sampling unit 102, comparing unit 104, storage element 106 and processing unit 108, the wherein coupling of comparing unit 104 takes
Sample unit 102 and storage element 106, storage element 106 are also coupled to processing unit 108.Sampling unit 102 can be for example with over sampling
Mode data-signal S1 is sampled, it is right respectively that is, with the sampling clock signal of one group of identical frequency but out of phase
Data-signal S1 makees the action sampled.Fig. 2 is schematically shown as carrying out data-signal S1 the schematic diagram of over sampling, refer to Fig. 2.Fig. 2
Embodiment is sampled to data-signal respectively using three sampling clock signals CLK1, CLK2 and CLK3, to produce sampling
Signal S2 is to comparing unit 104.Wherein, sampled signal may include the multiple data sampling values being alternately produced and multiple data sides
Edge sampling value, such as in fig. 2, the rising edge according to sampling clock signal CLK1, CLK3 are sampled to data-signal S1 and can obtained
To data sampling value (that is, D0、D1), and the rising edge according to sampling clock signal CLK2 is sampled and can obtained to data-signal S1
To the data edges sampling value between above-mentioned two data sampling value.So constantly foundation sampling clock signal CLK1,
CLK2 and CLK3 is sampled to data-signal S1 respectively, alternately caused multiple data sampling values and multiple data
Edge sampling value.It is worth noting that, in some embodiments, sampling unit 102 also can be according to single sampling clock signal pair
Data-signal S1 is sampled, and is not limited to be sampled data-signal S1 in a manner of over sampling.
Comparing unit 104 can be implemented such as with comparator or logic circuit (as with door, XOR gate ...), and it is in order
Data sampling value from sampling unit 102 is compared two-by-two, each sampling value can all be entered with its next sampling value
Row compares, also i.e. by adjacent data sampling value compared with data edges sampling value, to produce multiple fiducial values.Storage is single
Member 106 can store data sampling value, data edges sampling value and fiducial value.In addition, processing unit 108 then can be according to producing in succession
Three raw data sampling values come judge whether output phase adjust control signal S3, to adjust the sampled data of sampling unit 102
The phase of the sampling clock signal of signal S1 when institutes foundation.
For example, three data sampling value D that the sampled data signal S1 of sampling unit 102 is obtained in succession-1、D0、D1
Sampling result, and D0、D1, can be as shown in following table one when data sampling value differs：
| D-1 | D0 | D1 | |
| Sampling result A | 0 | 0 | 1 |
| Sampling result B | 1 | 0 | 1 |
| Sampling result C | 0 | 1 | 0 |
| Sampling result D | 1 | 1 | 0 |
Table one
Data sampling value D shown in table one-1、D0、D1Sampling result be in data sampling value D0With data sampling value D1No
The sampling result being likely to occur in the case of identical.In the present embodiment, as data sampling value D0With data sampling value D1Not phase
Meanwhile processing unit 108 can determine whether data sampling value D0Previous data sampling value (that is, data sampling value D-1) whether with
Data sampling value D0It is identical.Wherein as data sampling value D-1With data sampling value D0When identical, processing unit 108 can be according to comparing
Unit 104 compares data sampling value D0, data sampling value D1And between data sampling value D0With data sampling value D1Between data
Fiducial value obtained by edge sampling value, to judge the sampling clock signal of the sampled data signal S1 institutes foundation of sampling unit 102
For leading or backward data-signal S1 phase.
By taking sampling result A as an example, if by between data sampling value D0With data sampling value D1Between data edges sampling value with
Data sampling value D0Fiducial value learn between data sampling value D0With data sampling value D1Between data edges sampling value and data
Sampling value D0Different (that is, data edges sampling value is 1), represent the sampling of the sampled data signal S1 institutes foundation of sampling unit 102
Clock signal falls behind data-signal S1 phase.If by between data sampling value D0With data sampling value D1Between data edges take
Sample value and data sampling value D1Fiducial value learn between data sampling value D0With data sampling value D1Between data edges sampling value
With data sampling value D1Different (that is, data edges sampling value is 0), represent the sampled data signal S1 institutes foundation of sampling unit 102
The leading data-signal S1 of sampling clock signal phase.And processing unit 108 judge sampling clock signal to be leading or
After falling behind data-signal S1, processing unit 108 can be according to the leading of sampling clock signal or backward adjustment sampling clock signal
Phase, to avoid the missampling of sampling unit 102, and caused by circuit it is unstable and circuit performance declines.
In addition, work as data sampling value D0With data sampling value D1When differing, and processing unit 108 judges data sampling
Value D0Previous data sampling value (that is, data sampling value D-1) also with data sampling value D0When different, processing unit 108 is not
Adjust the phase of sampling clock signal.For example, in the case of sampling result B, C of table one, processing unit 108 does not adjust
The phase of sampling clock signal.
In addition, above-mentioned storage element for example can be implemented with buffer, it can for example be configured to temporarily store data sampling value D-1、
D0、D1And data sampling value D-1、D0、D1With the fiducial value of data edges sampling value.
Due under the data transmission applications of high speed (such as more than 5GHz transmission rate), such as such as USB 3.0, USB
3.1st, the transmission technology such as PCIE Gen2, PCIE Gen3, the effect of signal attenuation will be more obvious, will so cause data-signal S1
When changing its state, there is the situation of state switching points skew in (that is, when switching its logic level), and when data-signal S1 switches it
When the frequency of state is higher, this deviation effect is more serious, so will greatly influence the standard of the phase adjustment of sampling clock signal
Exactness.To avoid the processing unit 108 of this situation above-described embodiment according to caused three data sampling values D in succession-1、D0、D1
To judge whether that output phase adjusts control signal, to adjust the phase of sampling clock signal, in data sampling value D-1With data
Sampling value D0Just according to data sampling value D in the case of identical0、D1The phase of sampling clock signal is adjusted, to avoid data-signal
The frequent switching of S1 state reduces the stability that processing unit 108 adjusts the phase of sampling clock signal.
In another embodiment, as data sampling value D0With data sampling value D1When differing, and processing unit 108 judges
Go out data sampling value D0Previous data sampling value (that is, data sampling value D-1) also with data sampling value D0When different, processing
Unit 108 adjusts the phase of clock signal according to a fixed count interval.For example, a meter is built in processing unit 108
Number device (not shown)s, this counter also can be independently outside processing units 108, and this counter is counting current sampled data
Quantity.Processing unit 108 adjusts the phase of clock signal according to a specific count value and its multiple.That is, in table
In the case of one sampling result B, C, processing unit 108 can be with reference to above-mentioned current count value, when current count value is
When specific count value or its multiple, processing unit 108 will adjust the phase of clock signal, otherwise not adjust sampling clock letter
Number phase.
Fig. 3 illustrates the schematic diagram of the clock and data recovery device using phase detection device of one embodiment of the invention, please
Reference picture 3.Phase detection device in above-mentioned Fig. 1 can be for example applied to clock and data recovery device, in the present embodiment, clock
Return apparatus shakes including phase detection device 302, charge pump 304, charge pump 306, loop filter 308, voltage control
Swing device 310, frequency divider 312, phase-frequency detector 314, lock detector 316 and switch unit 318, wherein phase-detection
Device 302 couples charge pump 304 and voltage-controlled oscillator 310, and switch unit 318 couples charge pump 304, charge pump 306
And loop filter 308, loop filter 308 couple voltage-controlled oscillator 310, frequency divider 312 couples phase frequency inspection
Survey device 314, lock detector 316 and voltage-controlled oscillator 310, phase-frequency detector 314 and be also coupled to charge pump 306.
Charge pump 306, loop filter 308, voltage-controlled oscillator 310, frequency divider 312, phase-frequency detector 314 may make up one
Phase-locked loop, it can carry out the clock signal SC that latch voltage control oscillator 310 is exported according to reference frequency signal SF.Work as lock
Determine detector 316 detect clock signal SC be divided after its phase of result and frequency and reference frequency signal SF phase with
Frequency (that is, locks) when falling within a tolerance and reaching stable state, and its exportable switch-over control signal SW is to being cut
Unit 318 is changed, loop filter 308 is switched to and is connected with charge pump 304, and causes phase detection device 302, charge pump
304th, the loop that loop filter 308 and voltage-controlled oscillator 310 are formed is come into operation.
The phase detection device of similar above-described embodiment, the processing unit in the phase detection device 302 of the present embodiment is (not
Illustrate) can be according to the three data sampling value D continuously generated-1、D0、D1To judge whether that output phase adjusts control signal S3,
To adjust the phase for the clock signal SC that voltage-controlled oscillator 310 is exported, clock signal SC is phase in the present embodiment
The foundation of sampling unit sampled data signal S1 in detection means 302, phase adjustment control signals S3 can be pull-up control letter
Number or drop-down control signal.Wherein in data sampling value D0With data sampling value D1The situation and data sampling value D differed-1
With data sampling value D0In the case of identical, the processing unit in phase detection device 302 is just according to data sampling value D0、D1With
Data edges sampling value come judge clock signal SC phase for it is leading or fall behind, and output phase adjustment control signal S3, according to
To control charge pump 304 to carry out discharge and recharge, to adjust clock signal SC phase.Data-signal S1 state can so be avoided
The stability of processing unit adjustment clock signal SC phase is reduced by frequent switching, and can correctly sample out taking for data
Sample signal S2.In data sampling value D0With data sampling value D1The situation and data sampling value D differed-1With data sampling value
D0In the case of differing, output phase does not adjust control signal S3 to the processing unit in phase detection device 302.In another reality
Apply in example, in data sampling value D0With data sampling value D1The situation and data sampling value D differed-1With data sampling value D0
In the case of differing, the processing unit in phase detection device 302 adjusts clock signal according to a fixed count interval
Phase.Processing unit 108 with reference to a counter current count value, and during according to a specific count value and its multiple to adjust
The phase of clock signal, the phase of sampling clock signal is not otherwise adjusted.
It is worth noting that, the phase detection device of above-described embodiment, which does not limit, is only applied to clock and data recovery device
In, it is equally applicable in any required circuit for carrying out phase detection device, such as in phase-locked loop circuit.
Fig. 4 illustrates the schematic flow sheet of the phase adjusting method of one embodiment of the invention, refer to Fig. 4.By above-mentioned phase
The embodiment of detection means understands that the phase adjusting method of phase detection device may include the following steps.First, sampling number is received
It is believed that number and caused sampled signal (step S402), wherein sampled signal include multiple data sampling values for being alternately produced and
Multiple data edges sampling values.Then, more adjacent data sampling value and data edges sampling value, to produce multiple fiducial values
(step S404).Then, data sampling value, data edges sampling value and fiducial value (step S406) are stored.Afterwards, foundation connects
First data sampling value, the second data sampling value and the 3rd data sampling value caused by even judge whether output phase adjustment control
Signal processed, to adjust the phase (step S408) of the sampling clock signal of sampled data signal institute foundation.Specifically, step
S408 may include, first judge whether the second data sampling value is different from the 3rd data sampling value (step S410), if the second data
Sampling value is identical with the 3rd data sampling value, then does not adjust the phase (step S412) of sampling clock signal.And if the second data
Sampling value is different from the 3rd data sampling value, then then judges whether the first data sampling value and the second data sampling value are identical
(step S414), if the first data sampling value is different from the second data sampling value, into step S412, do not adjust sampling clock
The phase of signal.If the first data sampling value is identical with the second data sampling value on the contrary, foundation compares the second data sampling
Value, the 3rd data sampling value and the data edges sampling value gained between the second data sampling value and the 3rd data sampling value
The fiducial value arrived judges the phase-lead of sampling clock signal or falls behind the phase of data-signal, and adjusts sampling clock letter according to this
Number phase (step S416).
Fig. 5 illustrates the schematic flow sheet of the phase adjusting method of another embodiment of the present invention, refer to Fig. 5.Fig. 5 is with Fig. 4
It is similar, difference is only that Fig. 5 increases step S512 newly.That is, in the present embodiment, when judge the second data sampling value with
3rd data sampling value is different and when the first data sampling value is with the second data sampling value difference, just into step S512, according to
One specific count value and its multiple adjust the phase of clock signal, for example, referring to the current count value of counter, work as mesh
When preceding count value is specific count value or its multiple, the phase of clock signal is adjusted.
In summary, the present invention is by according to caused first data sampling value in succession, the second data sampling value and the
Three data sampling values judge whether that output phase adjusts control signal, to adjust the sampling clock of sampled data signal institute foundation letter
Number phase, to be sampled the phase adjustment of clock signal when circuit is relatively stable, and can more correctly adjust sampling clock
The phase of signal, avoid phase difference cause circuit unstable and circuit performance decline.
Claims (11)
1. a kind of phase detection device, including：
One comparing unit, receives one data-signal of sampling and a caused sampled signal, the sampled signal include what is be alternately produced
Multiple data sampling values and multiple data edges sampling values, more adjacent data sampling value and data edges sampling value, with
Produce multiple fiducial values；
One storage element, store these data sampling values, these data edges sampling values and these fiducial values；And
One processing unit, the storage element is coupled, according to caused one first data sampling value, one second data sampling value in succession
And one the 3rd data sampling value it is whether identical, come judge whether export a phase adjustment control signals, with adjustment sample the number
It is believed that the phase of the sampling clock signal of number institute's foundation.
2. phase detection device as claimed in claim 1, wherein when the second data sampling value takes different from the 3rd data
When sample value and the first data sampling value identical with the second data sampling value, the processing unit adjusts the sampling clock signal
Phase.
3. phase detection device as claimed in claim 1, wherein when the second data sampling value takes different from the 3rd data
Sample value and when the first data sampling value is different from the second data sampling value, the processing unit does not adjust the sampling clock signal
Phase.
4. phase detection device as claimed in claim 1, wherein when the second data sampling value takes different from the 3rd data
Sample value and when the first data sampling value is different from the second data sampling value, the processing unit comes according to a fixed count interval
Adjust the phase of clock signal.
5. phase detection device as claimed in claim 4, the wherein processing unit refer to a current count value of a counter,
When the current count value is a specific count value or its multiple, the processing unit adjusts the phase of clock signal.
6. phase detection device as claimed in claim 1, in addition to：
One sampling unit, the comparing unit is coupled, sample the data-signal and produce the sampled signal.
7. a kind of phase adjusting method, including：
Receive and sample a data-signal and a caused sampled signal, the sampled signal include the multiple data samplings being alternately produced
Value and multiple data edges sampling values；
More adjacent data sampling value and data edges sampling value, to produce multiple fiducial values；
Store these data sampling values, these data edges sampling values and these fiducial values；And
According to caused one first data sampling value, one second data sampling value and one the 3rd data sampling value in succession whether phase
Together, come judge whether export a phase adjustment control signals, with adjustment sample the data-signal institute foundation sampling clock signal
Phase.
8. phase adjusting method as claimed in claim 7, wherein when the second data sampling value takes different from the 3rd data
When sample value and the first data sampling value identical with the second data sampling value, the phase of the sampling clock signal is adjusted.
9. phase adjusting method as claimed in claim 7, wherein when the second data sampling value takes different from the 3rd data
Sample value and when the first data sampling value is different from the second data sampling value, does not adjust the phase of the sampling clock signal.
10. phase adjusting method as claimed in claim 7, in addition to：
When the second data sampling value is different from second number different from the 3rd data sampling value and the first data sampling value
During according to sampling value, the phase of clock signal is adjusted according to a fixed count interval.
11. phase adjusting method as claimed in claim 10, in addition to：
When the second data sampling value is different from second number different from the 3rd data sampling value and the first data sampling value
During according to sampling value, with reference to a current count value of a counter, when the current count value is a specific count value or its multiple
When, adjust the phase of clock signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104109723A TWI556584B (en) | 2015-03-26 | 2015-03-26 | Phase detecting apparatus and phase adjusting method |
| TW104109723 | 2015-03-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104967445A CN104967445A (en) | 2015-10-07 |
| CN104967445B true CN104967445B (en) | 2018-02-27 |
Family
ID=54221406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510245375.9A Active CN104967445B (en) | 2015-03-26 | 2015-05-14 | Phase detection device and phase adjustment method |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9419783B1 (en) |
| CN (1) | CN104967445B (en) |
| TW (1) | TWI556584B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6476659B2 (en) * | 2014-08-28 | 2019-03-06 | 富士通株式会社 | Signal reproduction circuit and signal reproduction method |
| CN108345554B (en) * | 2017-01-22 | 2020-08-21 | 联发科技股份有限公司 | Method for determining sampling phase of sampling clock signal and related electronic device |
| CN107168220B (en) * | 2017-04-05 | 2019-09-06 | 深圳市恒扬数据股份有限公司 | A kind of programmable logic controller (PLC) part and its high speed signal method of reseptance |
| US10256968B1 (en) * | 2017-07-26 | 2019-04-09 | Xilinx, Inc. | Systems and methods for clock and data recovery |
| CN112042123B (en) * | 2018-05-03 | 2022-09-16 | 华为技术有限公司 | Clock data recovery device, optical module and optical line terminal |
| KR20210034136A (en) * | 2019-09-19 | 2021-03-30 | 삼성디스플레이 주식회사 | Clock data recovery circuit and display device including the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1125027A (en) * | 1993-06-07 | 1996-06-19 | 株式会社东芝 | Phase detector |
| US6347128B1 (en) * | 1998-07-20 | 2002-02-12 | Lucent Technologies Inc. | Self-aligned clock recovery circuit with proportional phase detector |
| CN101141128A (en) * | 2006-05-30 | 2008-03-12 | 奇梦达股份公司 | Signal processing circuit |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2358056A1 (en) * | 1976-07-09 | 1978-02-03 | Ibm France | METHOD AND DEVICE FOR SYNCHRONIZING THE CLOCK OF THE RECEIVER OF A DATA TRANSMISSION SYSTEM IN PSK MODULATION |
| US4475220A (en) * | 1982-01-19 | 1984-10-02 | Rca Corporation | Symbol synchronizer for MPSK signals |
| US6150855A (en) * | 1990-02-06 | 2000-11-21 | Bull, S.A. | Phase-locked loop and resulting frequency multiplier |
| JP3597433B2 (en) * | 1999-12-20 | 2004-12-08 | 富士通株式会社 | Clock adjustment device and optical disk device in data reproduction system |
| US6636092B1 (en) * | 2000-09-14 | 2003-10-21 | 3Com Corporation | Digital receive phase lock loop with cumulative phase error correction |
| US20030165208A1 (en) * | 2002-03-04 | 2003-09-04 | Andrew Carter | Non-linear decision feedback phase locked loop filter |
| US7292629B2 (en) * | 2002-07-12 | 2007-11-06 | Rambus Inc. | Selectable-tap equalizer |
| KR100641328B1 (en) * | 2004-12-24 | 2006-11-01 | 삼성전자주식회사 | Timing recovery method and timing recovery apparatus using the same |
| US7383160B1 (en) * | 2006-06-30 | 2008-06-03 | International Business Machines Corporation | Method and apparatus for constructing a synchronous signal diagram from asynchronously sampled data |
| CN101568967A (en) * | 2007-11-26 | 2009-10-28 | 松下电器产业株式会社 | Phase comparator, PLL circuit, information regeneration processing apparatus, optical disc regenerating apparatus, and magnetic disc regenerating apparatus |
| JPWO2009116296A1 (en) * | 2008-03-21 | 2011-07-21 | パナソニック株式会社 | Synchronous control circuit and video display device |
| CN102714499B (en) * | 2010-01-21 | 2016-10-19 | 美国莱迪思半导体公司 | Phase detector circuit and method |
| US8559582B2 (en) * | 2010-09-13 | 2013-10-15 | Altera Corporation | Techniques for varying a periodic signal based on changes in a data rate |
| US8798217B2 (en) * | 2010-11-03 | 2014-08-05 | Qualcomm Incorporated | Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection |
| US9237004B2 (en) * | 2013-09-16 | 2016-01-12 | Himax Technologies Limited | Clock data recovery circuit |
-
2015
- 2015-03-26 TW TW104109723A patent/TWI556584B/en active
- 2015-05-14 CN CN201510245375.9A patent/CN104967445B/en active Active
- 2015-06-10 US US14/735,156 patent/US9419783B1/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1125027A (en) * | 1993-06-07 | 1996-06-19 | 株式会社东芝 | Phase detector |
| US6347128B1 (en) * | 1998-07-20 | 2002-02-12 | Lucent Technologies Inc. | Self-aligned clock recovery circuit with proportional phase detector |
| CN101141128A (en) * | 2006-05-30 | 2008-03-12 | 奇梦达股份公司 | Signal processing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| US9419783B1 (en) | 2016-08-16 |
| CN104967445A (en) | 2015-10-07 |
| TWI556584B (en) | 2016-11-01 |
| TW201635715A (en) | 2016-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104967445B (en) | Phase detection device and phase adjustment method | |
| US10355852B2 (en) | Lock detector for phase lock loop | |
| US8934591B2 (en) | Clock and data recovery circuit and parallel output circuit | |
| US8040156B2 (en) | Lock detection circuit and lock detecting method | |
| CN100508398C (en) | Phase detecting circuit having adjustable gain curve and method thereof | |
| CN106357266B (en) | Lock detecting circuit, method and phase lock circuitry | |
| US6374361B1 (en) | Skew-insensitive low voltage differential receiver | |
| US9543937B2 (en) | Multi-phase clock generation | |
| WO2007106766A2 (en) | Signaling system with adaptive timing calibration | |
| US7482841B1 (en) | Differential bang-bang phase detector (BBPD) with latency reduction | |
| CN103684438A (en) | Delay locked loop | |
| CN100533976C (en) | Skew correction apparatus | |
| US7015727B2 (en) | Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal | |
| US20080056420A1 (en) | Oversampling circuit and oversampling method | |
| CN101494456B (en) | Delay-locked loop and a stabilizing method thereof | |
| US8773291B2 (en) | Audio receiver and sample rate converter without PLL or clock recovery | |
| KR101202084B1 (en) | A cdr circuit having improved jitter characteristics by using a bang-bang phase detector | |
| US7292070B1 (en) | Programmable PPM detector | |
| KR101515360B1 (en) | Providing a feedback loop in a low latency serial interconnect architecture | |
| CN107579736B (en) | hybrid lock detector | |
| US8718215B2 (en) | Method and apparatus for deskewing data transmissions | |
| US20040223574A1 (en) | Phase frequency detector used in digital PLL system | |
| CN1983815A (en) | Time-delay locking loop | |
| TW202224359A (en) | A method for improving the tracking performance of clock data recovery circuitand a system using the same | |
| CN105591648A (en) | Phase detector and correlative phase-detecting method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200628 Address after: Chinese Taiwan New Taipei City Patentee after: VIA LABS Inc. Address before: Chinese Taiwan New Taipei City Patentee before: Via Technologies, Inc. |