CN112260686A

CN112260686A - Low locking error delay chain phase-locked loop

Info

Publication number: CN112260686A
Application number: CN202011165309.8A
Authority: CN
Inventors: 马瑞; 陈义豪; 张玮; 朱樟明
Original assignee: Ningbo Xinhui Technology Co ltd
Current assignee: Ningbo Xinhui Technology Co ltd
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2021-01-22
Anticipated expiration: 2040-10-27
Also published as: CN112260686B

Abstract

The low-locking-error delay chain phase-locked loop provided by the embodiment of the invention comprises a first phase-locked loop and a second phase-locked loop, wherein a first clock signal and an Nth clock signal are respectively locked to the same reference clock signal REF through the two phase-locked loops, and after the two phase-locked loops are locked, the first clock signal and the Nth clock signal have the same locking error relative to the reference clock signal REF. By adopting error transmission, the phase error between the first clock signal and the Nth clock signal can be obviously reduced, and the first clock signal and the Nth clock signal both control devices in the differential charge pump after passing through the self-adjusting phase discriminator, so that the phase error caused by the fact that charging and discharging currents of the differential charge pump cannot be completely matched due to the fact that driving capacities of a driving circuit in the phase discriminator are not matched and switching speeds of the devices in the differential charge pump are different is avoided, and therefore the delay chain phase-locked loop with the low locking error has the obvious advantage of low locking phase error.

Description

Low locking error delay chain phase-locked loop

Technical Field

The invention belongs to the technical field of laser radar optical signal receiver systems, and relates to a delay chain phase-locked loop with low locking error.

Background

Laser radar ranging is a common ranging technology, and the working principle is as follows: when laser emitted by a laser emitter irradiates on a detected target object, a laser echo reflected by the target object is received by an avalanche photodiode working in a linear mode and converted into a current signal, a front-end analog receiver linearly converts pulse current generated by the avalanche photodiode into a voltage signal, and then a time-to-digital converter is used for obtaining the flight time information of the pulse, so that the method has extremely high requirements on the precision and the detection stability of the time-to-digital converter. The time-to-digital converter often needs a multiphase clock with uniform high-frequency phase distribution, an internal feedback loop of a delay chain phase-locked loop can enable an internally generated clock to inherit the excellent characteristics of a reference clock, the anti-interference performance on the environment influences such as process, voltage, temperature and the like is strong, and the requirements of a laser radar ranging system on high resolution and high precision can be met.

A conventional delay chain phase locked loop is shown in fig. 1 and is composed of a single phase detector, a charge pump, a loop filter, and a voltage controlled delay chain. Referring to the signal transmission schematic diagram of the conventional phase discriminator and the charge pump shown in fig. 2, two input clock signals of the phase-locked loop form charge and discharge currents by controlling the switches of the PMOS transistor and the NMOS transistor inside the charge pump through the phase discriminator, referring to the schematic diagram of the mismatching of the charge and discharge currents caused by the different switching speeds of the MOS transistors shown in fig. 3, the first clock signal forms the switch of the charge signal control PMOS transistor after passing through the phase discriminator, the nth clock signal forms the switch of the discharge signal control NMOS transistor after passing through the phase discriminator, because the switching characteristics of the NMOS and the PMOS transistors are different, the total charge amount of the charge and discharge currents is the same, but the charge and discharge currents cannot be completely matched in the on-off state and have a certain phase difference, and then the locking phase error can be introduced. Further, the phase uniformity of the output multiphase clock is affected, the conversion accuracy of the time-to-digital converter is reduced, and finally, the error of the range detection is increased, which may reduce the detection accuracy of the laser radar ranging system.

Disclosure of Invention

To solve the above problems in the prior art, the present invention provides a low-locking-error delay chain phase-locked loop. The technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides a low locking error delay chain phase-locked loop, which comprises: the self-adjusting phase discriminator, the differential charge pump, the first loop filter, the second loop filter, the third loop filter, the clamp amplifier and the voltage-controlled delay chain are sequentially connected to form a first phase-locked loop, the self-adjusting phase discriminator, the differential charge pump and the first loop filter are sequentially connected to form a second phase-locked loop, the output of the first loop filter is connected with the input of the clamp amplifier, a first clock signal and an Nth clock signal output by the voltage-controlled delay chain are input into the self-adjusting phase discriminator, a reference clock signal is generated inside the self-adjusting phase discriminator and then converted into a discharge signal to be output, the clamp amplifier controls a first adjusting voltage of the first phase-locked loop and a second adjusting voltage of the second phase-locked loop, and the difference value of the first regulating voltage and the second regulating voltage is in a preset range, and the first clock signal and the Nth clock signal input by the self-regulating phase discriminator are respectively locked to the reference clock signal through the first phase-locked loop and the second phase-locked loop.

Optionally, the self-adjusting phase detector comprises: the first fixed delay unit inputs a first clock signal, the output of the first fixed delay unit is connected with the input of the first trigger, the output of the first trigger is connected with the input of the logic AND gate, the input Nth clock signal of the variable delay unit, the output of the variable delay unit is connected with the second trigger, the output of the second trigger is connected with the input of the logic AND gate, the second fixed delay unit inputs the Nth clock signal, the output of the second fixed delay unit is connected with the input of the third trigger, the output of the third trigger is connected with the input of the logic AND gate, the outputs of the logic AND gate are respectively connected with the reset end of the first trigger, the reset end of the second trigger and the reset end of the third trigger, the first trigger outputs a first charging signal, the second trigger outputs a discharging signal DN, the third trigger outputs a second charging signal, and the logic AND gate outputs a reset signal.

Optionally, the first loop filter, the second loop filter, and the third loop filter include: the resistance of the resistor R is greater than the resistance of the resistor R, one end of a resistor R is connected to one end of a first capacitor C1, the other end of the resistor R is connected to one end of a second capacitor C2, the other end of the second capacitor C2 is connected to the other end of the first capacitor C1, one end of the resistor R in the first loop filter and one end of the resistor R in the second loop filter input an output signal of the differential charge pump, one end of a first capacitor C1 in the first loop filter outputs a first adjustment voltage to the clamp amplifier and the self-adjusting phase detector, one end of a first capacitor C1 in the second loop filter outputs a second adjustment voltage to the clamp amplifier and the self-adjusting phase detector, one end of the resistor R in the third loop filter input an output signal of the clamp amplifier, and one end of a first capacitor C1 in the third loop filter outputs a control voltage to the voltage-controlled delay chain.

Optionally, the voltage controlled delay chain comprises: the control end of each delay unit inputs the control voltage output by the third loop filter, the input end of the first delay unit is connected with an input clock, the nth delay unit outputs the nth clock signal, and N is from 1 to N.

Optionally, the differential charge pump comprises: a first PMOS transistor M1, a first NMOS transistor M2, a third capacitor C3, a second PMOS transistor M3, a second NMOS transistor M4, and a fourth capacitor C4, wherein a gate of the first PMOS transistor is connected to a first charging signal output by the self-regulating phase detector, a drain of the first PMOS transistor M1 is connected to a drain of the first NMOS transistor M2 and one end of the third capacitor C3, a drain of the first NMOS transistor M2 is connected to the other end of the third capacitor C3, a gate of the second PMOS transistor M3 is connected to a second charging signal output by the self-regulating phase detector, a drain of the second PMOS transistor M3 is connected to a drain of the second NMOS transistor M4 and one end of the fourth capacitor C4, a drain of the second NMOS transistor M4 is connected to the other end of the fourth capacitor C4, a gate of the first NMOS transistor M2 and a gate of the second NMOS transistor M4 are connected to a discharging signal output by the self-regulating phase detector, and a source of the first PMOS transistor M3 and a source of the second PMOS transistor M3 are connected to a source voltage source of the.

Optionally, the clamp amplifier comprises: a third NMOS tube M5, a fourth NMOS tube M6, a fifth NMOS tube M7, a third PMOS tube M8, a fourth PMOS tube M9, a fifth PMOS tube M10, and a current source, the gate of the third NMOS tube M5 is connected to the gate of the fifth PMOS tube M10, the drain of the third NMOS tube M5 is connected to the source of the fourth NMOS tube M6 and the source of the fifth NMOS tube M7, the gate of the fourth NMOS tube M6 is connected to the first regulated voltage VCTR _ a, the drain of the fourth NMOS tube M6 is connected to the gate of the third PMOS tube M8 and the gate of the fourth PMOS tube M9, the gate of the fifth NMOS tube M7 is connected to the second regulated voltage tr _ B, the drain of the fifth NMOS tube M7 is connected to the drain of the fourth PMOS tube M9 and the input of the third loop filter, the gate of the fourth NMOS tube M9 is connected to the gate of the third PMOS tube M8, the drain of the fifth NMOS tube M8, the drain of the fifth PMOS tube M842 is connected to the source of the third PMOS tube M8653, the drain of the fifth PMOS tube M8427, the drain of the direct current source of the PMOS tube M8653, and the source of the third NMOS transistor M5 is connected to the source of the fifth PMOS transistor M10 and to ground.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a schematic diagram of a conventional delay chain phase-locked loop structure;

fig. 2 is a schematic diagram of a conventional phase detector and charge pump signal transmission;

FIG. 3 is a schematic diagram illustrating the mismatching of charging and discharging currents caused by the different switching speeds of MOS transistors in the conventional delay chain phase-locked loop;

FIG. 4 is a schematic diagram of a low-locking-error delay chain phase-locked loop according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a timing sequence of an input signal after being locked by a phase-locked loop of a delay chain according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a self-adjusting phase detector according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a loop filter according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a voltage-controlled delay chain according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a differential charge pump according to an embodiment of the present invention;

fig. 10 is a schematic diagram of input/output signal connections of a self-adjusting phase detector and a differential charge pump according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a clamp amplifier according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

As shown in fig. 4, an embodiment of the invention provides a low lock error delay chain phase locked loop, including: the self-adjusting phase discriminator, the differential charge pump, the first loop filter, the second loop filter, the third loop filter, the clamp amplifier and the voltage-controlled delay chain are sequentially connected to form a first phase-locked loop, the self-adjusting phase discriminator, the differential charge pump and the first loop filter are sequentially connected to form a second phase-locked loop, the output of the first loop filter is connected with the input of the clamp amplifier, a first clock signal and an Nth clock signal output by the voltage-controlled delay chain are input into the self-adjusting phase discriminator, a reference clock signal is generated inside the self-adjusting phase discriminator, then the reference clock signal is converted into a discharge signal to be output, the clamp amplifier controls a first adjusting voltage of the first phase-locked loop and a second adjusting voltage of the second phase-locked loop, and the difference value of the first regulating voltage and the second regulating voltage is in a preset range, and the first clock signal and the Nth clock signal input by the self-regulating phase discriminator are respectively locked to the reference clock signal through the first phase-locked loop and the second phase-locked loop.

Wherein the predetermined range is an acceptable range that is set according to actual conditions and that can be changed such that the first adjustment voltage is approximately the same as the second adjustment voltage.

It can be understood that since the self-adjusting phase detector is connected to the differential charge pump, the discharge signal output from the self-adjusting phase detector is input to the differential charge pump.

Referring to fig. 5, as shown in fig. 5, a timing diagram of an input signal after being locked by a low-lock-error delay chain phase locked loop according to the present invention is shown, a phase-adjustable reference clock signal REF is generated inside a self-adjusting phase detector, and a first clock signal and an nth clock signal at an input end of the phase detector are respectively locked to the reference clock signal REF through a first phase-locked loop and a second phase-locked loop, and since both phase-locked loops are affected by process, voltage and temperature changes and phase noise introduced by the self-adjusting phase detector, a charge pump and a loop filter, both phase-locked loops have a certain phase error, but since the phase errors of the two phase-locked loops can be cancelled, the phase error between the first clock signal and the second clock signal is significantly reduced. Although phase errors exist after the first clock signal and the Nth clock signal are respectively locked with the reference clock signal REF, rising edges of the first clock signal and the Nth clock signal are completely aligned, and no phase errors exist. And the second adjusting voltage generated in the locking process is clamped at the first adjusting voltage by the clamp amplifier through a negative feedback loop, the output of the clamp amplifier is used as the control voltage of the voltage-controlled delay chain, the phases of the first clock signal and the Nth clock signal are further adjusted, the locking of the phase-locked loop of the delay chain is accelerated, finally, the low locking phase error of the first clock signal and the Nth clock signal is realized, and the high-quality clock signals with N-1 phase distribution are generated.

It can be understood that a phase-adjustable clock signal is newly built in the self-adjusting phase discriminator of the low-locking-error delay chain phase-locked loop of the invention, two input reference clock signals are respectively locked to the reference clock signal REF through two different phase-locked loops, the locking errors of the two phase-locked loops are mutually offset, thereby reducing the locking phase error after the two input clocks are locked, the first clock signal and the Nth clock signal both control the NMOS tube or both control the PMOS tube in the differential charge pump after passing through the self-adjusting phase discriminator, because the switching speed of the MOS tubes of the same type can be well matched in practical application, further the first and the Nth input clock signals can be well matched for the control of the MOS switch tube in the locking state, thereby reducing the phase error caused by the incomplete matching of the charge and discharge currents of the charge pump due to the different switching speeds of the NMOS tube and the PMOS tube, thereby further reducing the locking phase error of the system; the low locking error delay chain phase-locked loop adds the clamp amplifier, so that the two locking loops pass through the clamp amplifier, the first regulating voltage in the first phase-locked loop and the second regulating voltage in the second phase-locked loop are clamped to be approximately the same level, and finally the two phase-locked loops are enabled to have approximately the same locking phase error.

Example two

As shown in fig. 6, a self-adjusting phase detector in a low-lock-error delay chain phase locked loop according to an embodiment of the present invention includes: the first fixed delay unit inputs a first clock signal, the output of the first fixed delay unit is connected with the input of the first trigger, the output of the first trigger is connected with the input of the logic AND gate, the input Nth clock signal of the variable delay unit, the output of the variable delay unit is connected with the second trigger, the output of the second trigger is connected with the input of the logic AND gate, the second fixed delay unit inputs the Nth clock signal, the output of the second fixed delay unit is connected with the input of the third trigger, the output of the third trigger is connected with the input of the logic AND gate, the outputs of the logic AND gate are respectively connected with the reset end of the first trigger, the reset end of the second trigger and the reset end of the third trigger, the first trigger outputs a first charging signal, the second trigger outputs a discharging signal DN, the third trigger outputs a second charging signal, and the logic AND gate outputs a reset signal.

Referring to fig. 6, a first clock signal passes through a fixed delay unit and a first flip-flop to form a first charging signal, a second clock signal passes through a same second fixed delay unit and a third flip-flop to form a second charging signal, and a variable delay unit and a second flip-flop to form a discharging signal. The first charging signal and the discharging signal control a differential charge pump in the first phase-locked loop to charge and discharge, the charging and discharging current adjusts the delay time of the variable delay unit through a first adjusting voltage generated after passing through the first loop filter, and phase errors of the first clock signal and the reference clock signal REF are reduced and finally locked after adjustment. The second charging signal and the discharging signal control a differential charge pump in a second phase-locked loop to charge and discharge, the charging and discharging current generates a second adjusting voltage after passing through a loop filter, the first adjusting voltage and the second adjusting voltage generate a control voltage of a voltage-controlled delay chain through a clamping amplifier, the delay time of the voltage-controlled delay chain is adjusted, the phase of the Nth clock signal is further changed, and the phase error between the Nth clock signal and a reference clock signal REF is reduced and finally locked after adjustment. The first phase-locked loop has one less pole introduced by the loop filter than the second phase-locked loop, and the time constant of the first phase-locked loop is smaller than that of the second phase-locked loop, so the locking speed of the first phase-locked loop is faster than that of the second phase-locked loop.

In the self-adjusting phase discriminator provided by the embodiment of the invention, a phase-adjustable clock signal is newly established by a first clock signal and used as a discharging signal of a charge pump, and the first clock signal and an Nth clock signal are used as charging signals of the charge pump after passing through the same fixed delay unit. Make two input clock signal all control differential charge pump's PMOS pipe or all control NMOS pipe behind the self-adjusting phase discriminator, because the switching speed of the same type MOS pipe can accomplish good matching in practical application, and then can make first and Nth input clock signal under the lock-up condition, accomplish good matching to the control of MOS switch tube, thereby reduced because NMOS pipe and PMOS pipe switching speed difference have led to the charge pump charge-discharge current can not match completely and the phase error that arouses, thereby further reduced the locking phase error of system.

EXAMPLE III

As shown in fig. 7, the first loop filter, the second loop filter, and the third loop filter in the delay chain phase-locked loop with low lock error according to the embodiment of the present invention each include: the resistance of the resistor R is greater than the resistance of the resistor R, one end of a resistor R is connected to one end of a first capacitor C1, the other end of the resistor R is connected to one end of a second capacitor C2, the other end of the second capacitor C2 is connected to the other end of the first capacitor C1, one end of the resistor R in the first loop filter and one end of the resistor R in the second loop filter input an output signal of the differential charge pump, one end of a first capacitor C1 in the first loop filter outputs a first adjustment voltage to the clamp amplifier and the self-adjusting phase detector, one end of a first capacitor C1 in the second loop filter outputs a second adjustment voltage to the clamp amplifier and the self-adjusting phase detector, one end of the resistor R in the third loop filter input an output signal of the clamp amplifier, and one end of a first capacitor C1 in the third loop filter outputs a control voltage to the voltage-controlled delay chain.

Example four

As shown in fig. 8, a voltage-controlled delay chain in a delay chain phase-locked loop with low locking error according to an embodiment of the present invention includes: the control end of each delay unit inputs the control voltage output by the third loop filter, the input end of the first delay unit is connected with an input clock, the nth delay unit outputs the nth clock signal, and N is from 1 to N.

EXAMPLE five

As shown in fig. 9, a differential charge pump in a delay chain phase-locked loop with low locking error according to an embodiment of the present invention includes: the self-adjusting phase detector comprises a first PMOS tube M1, a first NMOS tube M2, a third capacitor C3, a second PMOS tube, a second NMOS tube M4 and a fourth capacitor C4, wherein the gate of the first PMOS tube M1 is connected to a first charging signal output by the self-adjusting phase detector, the drain of the first PMOS tube M1 is connected to the drain of the first NMOS tube M2 and one end of the third capacitor C3 respectively, the drain of the first NMOS tube M2 is connected to the other end of the third capacitor C3, the gate of the second PMOS tube is connected to a second charging signal output by the self-adjusting phase detector, the drain of the second PMOS tube is connected to the drain of the second NMOS tube M4 and one end of the fourth capacitor C4 respectively, the drain of the second NMOS tube M4 is connected to the other end of the fourth capacitor C4, the gate of the first NMOS tube M2 and the gate of the second NMOS tube M4 are connected to a discharging signal output by the phase detector, and the source of the first PMOS tube M1 and the source of the second PMOS tube are connected to a power supply voltage.

Referring to fig. 10, fig. 10 is a schematic diagram illustrating connection of input and output signals of a self-adjusting phase detector and a charge pump, in which two input clock signals in the present invention pass through the self-adjusting phase detector to control both NMOS transistors and both PMOS transistors in a differential charge pump. First clock signal and second clock signal that forms respectively behind the self-adjusting phase discriminator first charge signal and second charge signal all control the switch of the PMOS pipe in the charge pump, because good matching can be accomplished to the switching speed of the same type MOS pipe in practical application, and then can make first and Nth input clock signal under lock-out condition, accomplish good matching to the control of MOS switch tube, avoided different grade type MOS pipe switching speed difference to lead to the charge pump charge-discharge current mismatch and the locking phase error that arouses.

EXAMPLE six

As shown in fig. 11, a clamp amplifier in a delay chain phase-locked loop with low lock error according to an embodiment of the present invention includes:

a third NMOS transistor M5, a fourth NMOS transistor M6, a fifth NMOS transistor M7, a third PMOS transistor M8, a fourth PMOS transistor M9, a fifth PMOS transistor M10, and a current source, wherein a gate of the third NMOS transistor M5 is connected to a gate of the fifth PMOS transistor M10, a drain of the third NMOS transistor M5 is connected to a source of the fourth NMOS transistor M6 and a source of the fifth NMOS transistor M7, a gate of the fourth NMOS transistor M6 is connected to a first regulation voltage VCTR _ a, a drain of the fourth NMOS transistor M6 is connected to a gate of the third PMOS transistor M8 and a gate of the fourth PMOS transistor M9, a gate of the fifth NMOS transistor M7 is connected to a second regulation voltage VCTR _ B, a drain of the fifth NMOS transistor M7 is connected to a drain of the fourth PMOS transistor M9 and an input gate of the third PMOS transistor M4624, a drain of the fourth PMOS transistor M9 is connected to a gate of the third PMOS transistor M585, a gate of the fifth PMOS transistor M4624 and a gate of the fifth PMOS transistor M57323, the source electrode of the third PMOS transistor M8 and the source electrode of the fourth PMOS transistor M9 are connected to the other end of the dc current source and are connected to a power supply voltage, and the source electrode of the third NMOS transistor M5 is connected to the source electrode of the fifth PMOS transistor M10 and is connected to a power ground.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A low lock error delay chain phase locked loop, comprising: self-adjusting phase discriminator, differential charge pump, first loop filter, second loop filter, third loop filter, clamp amplifier and voltage-controlled delay chain, self-adjusting phase discriminator differential charge pump first loop filter connects gradually and forms first phase-locked loop, self-adjusting phase discriminator differential charge pump second loop filter clamp amplifier third loop filter voltage-controlled delay chain connects gradually and forms second phase-locked loop, the output of first loop filter with the input of clamp amplifier links to each other, the first clock signal and the N clock signal input of voltage-controlled delay chain output self-adjusting phase discriminator, the inside reference clock signal that produces of self-adjusting phase discriminator, then will reference clock signal turns into discharge signal output, clamp amplifier control the first regulation voltage of first phase-locked loop and the second phase-locked loop output The difference value between the first adjusting voltage and the second adjusting voltage is in a preset range, and a first clock signal and an nth clock signal input by the self-adjusting phase discriminator are respectively locked to the reference clock signal through the first phase-locked loop and the second phase-locked loop.

2. The low lock-error delay chain phase locked loop of claim 1, wherein the self-adjusting phase detector comprises: the clock signal processing circuit comprises a first fixed delay unit, a second fixed delay unit, a variable delay unit, a first trigger, a second trigger, a third trigger and a logic AND gate, wherein a first clock signal is input into the first fixed delay unit, the output of the first fixed delay unit is connected with the input of the first trigger, the output of the first trigger is connected with the input of the logic AND gate, an Nth clock signal is input into the variable delay unit, the output of the variable delay unit is connected with the second trigger, the output of the second trigger is connected with the input of the logic AND gate, the Nth clock signal is input into the second fixed delay unit, the output of the second fixed delay unit is connected with the input of the third trigger, the output of the third trigger is connected with the input of the logic AND gate, and gates are respectively connected with the reset end and the reset end of the first trigger, The reset end of the second trigger and the reset end of the third trigger, the first trigger outputs a first charging signal, the second trigger outputs a discharging signal (DN), the third trigger outputs a second charging signal, and the logic AND gate outputs a reset signal.

3. The low-lock-error delay chain phase-locked loop of claim 1, wherein the first, second, and third loop filters comprise: a resistor (R), a first capacitor (C1) and a second capacitor (C2), one end of the resistor (R) is connected to one end of the first capacitor (C1), the other end of the resistor (R) is connected to one end of the second capacitor (C2), the other end of the second capacitor (C2) is connected to the other end of the first capacitor (C1), one end of the resistor (R) in the first loop filter and one end of the resistor (R) in the second loop filter input the output signal of the differential charge pump, one end of the first capacitor (C1) in the first loop filter outputs a first adjustment voltage to the clamp amplifier and the phase detector, one end of the first capacitor (C1) in the second loop filter outputs a second adjustment voltage to the clamp amplifier and the phase detector, one end of a resistor (R) in the third loop filter is input with an output signal of a clamping amplifier, and one end of a first capacitor (C1) in the third loop filter outputs a control voltage to the voltage-controlled delay chain.

4. The low lock error delay chain phase locked loop of claim 1, wherein the voltage controlled delay chain comprises: the N delay units are connected in sequence, the control end of each delay unit inputs the control voltage output by the third loop filter, the input end of the first delay unit is connected with an input clock, the nth delay unit outputs the nth clock signal, and N is from 1 to N.

5. The low-lock-error delay chain phase-locked loop of claim 1, wherein the differential charge pump comprises: a first PMOS transistor (M1), a first NMOS transistor (M2), a third capacitor (C3), a second PMOS transistor (M3), a second NMOS transistor (M4) and a fourth capacitor (C4), the gate of the first PMOS transistor is connected to the first charging signal output by the self-adjusting phase detector, the drain of the first PMOS transistor (M1) is connected to the drain of the first NMOS transistor (M2) and one end of the third capacitor (C3), the drain of the first NMOS transistor (M2) is connected to the other end of the third capacitor (C3), the gate of the second PMOS transistor (M3) is connected to the second charging signal output by the self-adjusting phase detector, the drain of the second PMOS transistor (M3) is connected to the drain of the second NMOS transistor (M4) and one end of the fourth capacitor (C632), the drain of the second NMOS transistor (M4) is connected to the other end of the fourth capacitor (M3823), the drain of the fourth NMOS transistor (M638) is connected to the gate of the NMOS transistor (M2), and the gate of the second NMOS transistor (M4) is connected to the gate of the second NMOS transistor (M638) And the source electrode of the first PMOS tube and the source electrode of the second PMOS tube (M3) are connected with a power supply voltage according to the output discharge signal.

6. The low lock-error delay chain phase-locked loop of claim 1, wherein the clamp amplifier comprises: a third NMOS transistor (M5), a fourth NMOS transistor (M6), a fifth NMOS transistor (M7), a third PMOS transistor (M8), a fourth PMOS transistor (M9), a fifth PMOS transistor (M10), and a current source, wherein the gate of the third NMOS transistor (M5) is connected to the gate of the fifth PMOS transistor (M10), the drain of the third NMOS transistor (M5) is connected to the source of the fourth NMOS transistor (M6) and the source of the fifth NMOS transistor (M7), the gate of the fourth NMOS transistor (M6) is connected to a first regulation voltage (VCTR _ a), the drain of the fourth NMOS transistor (M6) is connected to the gate of the third PMOS transistor (M8) and the gate of the fourth PMOS transistor (M9), the gate of the fifth NMOS transistor (M7) is connected to a second regulation voltage (VCTR _ B), the drain of the fifth NMOS transistor (M6866) is connected to the drain of the third NMOS transistor (M9), and the gate of the fourth NMOS transistor (M3527) are connected to the PMOS transistor (9), the drain electrode of the fifth PMOS tube (M10) is respectively connected with one end of a direct current source and the grid electrode of the fifth PMOS tube (M10), the source electrode of the third PMOS tube (M8) and the source electrode of the fourth PMOS tube (M9) are connected with the other end of the direct current source and are connected with power supply voltage, and the source electrode of the third NMOS tube (M5) is connected with the source electrode of the fifth PMOS tube (M10) and connected with the power supply ground in parallel.