CN104467819A - Delay-locked loop, voltage-controlled delay line and delay unit - Google Patents
Delay-locked loop, voltage-controlled delay line and delay unit Download PDFInfo
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- CN104467819A CN104467819A CN201410589753.0A CN201410589753A CN104467819A CN 104467819 A CN104467819 A CN 104467819A CN 201410589753 A CN201410589753 A CN 201410589753A CN 104467819 A CN104467819 A CN 104467819A
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Abstract
The embodiment of the invention discloses a delay unit, a voltage-controlled delay line and a delay-locked loop. The delay unit comprises multiple current hunger buffers connected in series. Load capacitors are connected between output of each current hunger buffer and a power voltage and between the output and the ground respectively in series. The voltage-controlled delay line is formed by cascading one or more delay units. The delay-locked loop comprises an offset generation circuit and the voltage-controlled delay line, the offset generation circuit outputs voltage control signals Vbp and Vbn controlling the voltage-controlled delay line, and the voltage-controlled delay line comprises an internal voltage-controlled delay line for phase locking and one or more parallel external voltage-controlled delay lines providing delay clocks, wherein the internal voltage-controlled delay line and the external voltage-controlled delay lines each comprise one or more cascaded delay units. The delay unit, the voltage-controlled delay line and the delay-locked loop are suitable for high-speed circuits, connecting lines on the high-speed clocks can be reduced through the delay-locked loop, and the problem that clock accuracy is insufficient due to the fact that the connecting lines are long is solved.
Description
Technical field
The present invention relates to the communications field, particularly relate to a kind of delay phase-locked loop, voltage controlled delay line and delay unit.
Background technology
In the data transmission, along with increasing of volume of transmitted data, clock frequency is also more and more higher, simultaneously also more and more stricter to the requirement of synchronised clock.In order to improve the transfer rate of data, easy mode is the rising edge and the trailing edge image data that utilize clock simultaneously, thus the efficiency doubled under phase same rate.In addition when carrying out data processing, also needing the clock with out of phase, such as: 45 ° of phase clocks or 90 ° of phase clocks etc., requiring again the duty ratio that these clocks keep good simultaneously.At present, the generation of these phase clocks can be realized by DLL (Delay Locked Loop, delay phase-locked loop).
Fig. 1 shows the structure of typical DLL.
As shown in Figure 1, typical DLL comprises: phase discriminator 101, charge pump 102, offset generating circuit 103 and VCDL (Voltage Controlled Delay Line, voltage controlled delay line) 104.Wherein, phase discriminator 101, for comparing to the phase place of input clock CLKIN and feedback clock CLKFB the phase difference detecting two signals, thus produces upwards detection signal UP or downwards detection signal DOWN; Charge pump 102, for receiving upwards detection signal UP or downwards detection signal DOWN from phase discriminator 101, and respond upwards detection signal UP increase output current electric capacity C is charged or respond downward detection signal DOWN reduce output current electric capacity C is discharged, thus adjustment Vctrl current potential; Offset generating circuit 103, under the control of Vctrl, output voltage signal Vbp and Vbn; VCDL 104, for exporting the CLKFB of certain time-delay under the control of Vbp and Vbn, making CLKFB consistent with input clock phase place, completing locking (LOCK) state; Now, CLKOUT can export different delayed clock (clocks as the outs of phase such as 45 °, 90 °); Wherein, inner normal being connected in series by multiple delay unit of VCDL104 forms.
Fig. 2 shows the structure of typical single delay unit.
As shown in Figure 2, each delay unit comprises: nmos pass transistor M5 and M6, and wherein the grid of M5 and M6 is differential input end, and drain electrode is difference output end; PMOS transistor M1 to M4, M1 to M4 constitutes a pair balanced load, wherein M1 and M2 formation parallel with one another VCR (Voltage ControlledResisitor, thyrite) 1, M3 and M4 formation parallel with one another VCR2, the structure of VCR1 with VCR2 is identical, for VCR1, its structure is described, in VCR1, the source electrode of M1 and M2 connects supply voltage, drain electrode is connected with the drain electrode of M5, and the grid of M1 and its drain electrode couple; The drain electrode of nmos pass transistor M7, M7 is connected with the source electrode of M5 and M6, and the source electrode of M7 is connected to ground.Wherein, the grid of Vbn control M7, the grid of Vbp control M2 and M3.During work, input signal Vin inputs to the grid of M5 and M6, and input signal Vin is delayed by a default value to the control of balanced load due to Vbp, to provide delayed signal as Vout.Meanwhile, M7 provides tail current under the control of Vbn, compensates the change of drain electrode and substrate voltage.
The delay unit of this Fig. 2 structure can only be used in the slow situation of clock, and when clock frequency even goes up GHz to hundreds of MHZ just by helpless.
Summary of the invention
Embodiment of the present invention technical problem to be solved is, provides a kind of delay phase-locked loop, delay unit and voltage controlled delay line, can be applied in high speed circuit.
In order to solve the problems of the technologies described above, embodiments provide a kind of delay unit, comprising: the hungry buffer of electric current of multiple series connection, the output of the hungry buffer of each electric current is connected in series load capacitance respectively with between supply voltage and ground.
Further, the inverter of being connected by even number between the hungry buffer of described electric current connects.
Further, the hungry buffer of electric current is transported in the input of described delay unit after the inverter process that even number is connected, and the output of described delay unit exports after the inverter process that even number is connected.
Further, the hungry buffer of each electric current comprises: nmos pass transistor I, nmos pass transistor II, PMOS transistor I and PMOS transistor II; The source electrode of described PMOS transistor I is connected with supply voltage, and grid controls by voltage control signal Vbp, and drain electrode is connected with the source electrode of described PMOS transistor II; The drain electrode of described nmos pass transistor is connected with the drain electrode of described PMOS transistor II, and source electrode is connected with the drain electrode of described nmos pass transistor II; The source ground of described nmos pass transistor II, grid controls by voltage control signal Vbn; The grid of described PMOS transistor II and nmos pass transistor I is connected to the input of the hungry buffer of this electric current, and described PMOS transistor II is connected the output for this current-steering buffer with the drain electrode of nmos pass transistor I.
Further, the load capacitance between the output of current-steering buffer and supply voltage is realized by PMOS transistor III, and source electrode, the drain electrode of described PMOS transistor III are all connected with supply voltage, and grid is connected with the drain electrode of PMOS transistor II; Load capacitance between the output of described current-steering buffer and ground is realized by nmos pass transistor III, and described nmos pass transistor III source electrode, drain electrode are all connected to ground, and grid is connected with the drain electrode of nmos pass transistor I.
Present invention also offers a kind of voltage controlled delay line, comprise: the delay unit of one or more cascade, described delay unit comprises: the hungry buffer of the electric current of multiple series connection, the output of the hungry buffer of each electric current and be serially connected with load capacitance respectively between supply voltage and ground.
Further, the inverter of being connected by even number between the hungry buffer of described electric current connects, the hungry buffer of electric current is transported in the input of described delay unit after the inverter process that even number is connected, and the output of described delay unit exports after the inverter process that even number is connected.
Further, the hungry buffer of each electric current comprises: nmos pass transistor I, nmos pass transistor II, PMOS transistor I and PMOS transistor II; The source electrode of described PMOS transistor I is connected with supply voltage, and grid controls by voltage control signal Vbp, and drain electrode is connected with the source electrode of described PMOS transistor II; The drain electrode of described nmos pass transistor is connected with the drain electrode of described PMOS transistor II, and source electrode is connected with the drain electrode of described nmos pass transistor II; The source ground of described nmos pass transistor II, grid controls by voltage control signal Vbn; The grid of described PMOS transistor II and nmos pass transistor I is connected to the input of the hungry buffer of this electric current, and described PMOS transistor II is connected the output for this current-steering buffer with the drain electrode of nmos pass transistor I.
Present invention also offers a kind of delay phase-locked loop, comprise: offset generating circuit and voltage controlled delay line, described offset generating circuit exports voltage control signal Vbp and Vbn controlling voltage controlled delay line, described voltage controlled delay line comprises: for phase-locked inside voltage controlled delay line with for providing the one or more parallel outside voltage controlled delay line of delay clock, described inner voltage controlled delay line and outside voltage controlled delay line all comprise the delay unit of one or more cascade, described delay unit comprises further: the hungry buffer of electric current of multiple series connection, the output of the hungry buffer of each electric current and be serially connected with load capacitance respectively between supply voltage and ground.
Further, the inverter of being connected by even number between the hungry buffer of described electric current connects, the hungry buffer of electric current is transported in the input of described delay unit after the inverter process that even number is connected, and the output of described delay unit exports after the inverter process that even number is connected.
Implement the embodiment of the present invention, there is following beneficial effect:
The delay unit of the embodiment of the present invention is in series by the hungry buffer of multiple electric current, and be connected in series load capacitance in the output of the hungry buffer of each electric current respectively with between supply voltage and ground, thus realize time delay by the discharge and recharge of load capacitance, this kind of structure due to delay unit inside be all comparator configuration, their time of delay is all very short, response time quickly, therefore can be operated in the frequency of hundreds of Mhz to 1GHz, is suitable for high speed circuit and uses.
The delay phase-locked loop of the embodiment of the present invention, there is provided phase-locked by inner voltage controlled delay line, the clock of time delay is provided by outside voltage controlled delay line, such as: 45 ° of phase clocks or 90 ° of phase clocks etc. are provided, this kind of structure can be placed near desired location due to outside voltage controlled delay line, and do not need to be placed on delay phase-locked loop inside, because this reducing the line on high-frequency clock, avoid the problem causing clock inaccurate because line is long, and due to voltage control signal Vbp and Vbn that inner voltage controlled delay line and outside voltage controlled delay line all use offset generating circuit to produce, therefore chip area during integrated circuit (IC) design can be reduced.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structure of typical DLL;
Fig. 2 is the structure of typical single delay unit;
Fig. 3 is the circuit structure diagram of the embodiment of the delay unit that the embodiment of the present invention provides;
Fig. 4 is the structural representation of the embodiment of the delay phase-locked loop (DLL) that the embodiment of the present invention provides;
Fig. 5 is the structural representation of the embodiment of the voltage controlled delay line that the embodiment of the present invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Please refer to Fig. 3, is the circuit structure diagram of the embodiment of the delay unit that the embodiment of the present invention provides.
As shown in Figure 3, delay unit comprises: metal-oxide-semiconductor M1 to M12 and inverter I1 to I6.Wherein, M1, M2, M5, M7, M8, M11 are PMOS, and M3, M4, M6, M9, M10, M12 are NMOS tube.
Wherein, M1 to M6 and M7 to M12 forms identical structure, i.e. the hungry buffer (Current Starving Buffer) of the electric current of bringing onto load electric capacity, and realizes series connection by inverter I3 and I4.
Concrete, M1 to M4 forms hungry buffer (the Current Starving Buffer) BUF1 of an electric current.M7 to M10 forms the hungry buffer BUF2 of another electric current, both structures are identical, therefore the hungry buffer of electric current only formed for M1 to M4 illustrates: the source electrode of M1 is connected with supply voltage VDD, and the grid of M1 controls by voltage control signal Vbp, and the drain electrode of M1 is connected with the source electrode of M2; The grid of M2 is connected the input as the hungry buffer of this electric current with the grid of M3, the drain electrode of M2 is connected the output as the hungry buffer of this electric current with the drain electrode of M3, the source electrode of M3 is connected with the drain electrode of M4, and the grid of M4 controls by voltage control signal Vbn, and the source electrode of M4 is connected to ground.
The structure of Here it is the hungry buffer of electric current, the hungry buffer of each electric current output and be all in series with load capacitance between supply voltage and ground, continue the electric current hunger buffer formed for M1 to M4 below, load capacitance be described.
As shown in Figure 3, the output of the electric current that grid and the M1 to M4 of M5 are formed hungry buffer is connected, and source electrode and the drain electrode of M5 are connected with supply voltage, the load capacitance between the output of the electric current hunger buffer of formation M1 to M4 formation and supply voltage; The output of the electric current that grid and the M1 to M4 of M6 are formed hungry buffer is connected, and source electrode and the drain electrode of M6 are connected to ground, and forms the load capacitance between the output of the electric current hunger buffer that M1 to M4 is formed and supply voltage.
In addition, as shown in Figure 3, before the input of the hungry buffer of the electric current of M1 to M4 formation, serial connection two inverter I1 and I2, are connected in series two inverter I1 and I2 after the output of the hungry buffer of the electric current of M7 to M9 formation.
In figure 3, if input IN raises, then A point and then raises, and when A point raises, M1 and M2 ends, M3 and M4 conducting, and B point, by M3 and M4 electric discharge, has a time delay; At this moment C point can reduce, M7 and M8 conducting, M9 and M10 ends, and D point is by M7 and M8 charging, and this also has one section of time delay, at this moment exports OUT point and uprises.On the contrary, when IN step-down, A point also step-down, M1 and M2 conducting, M3 and M4 ends, and B point, by M1 and M2 charging, has a time delay; At this moment C point can raise, M7 and M8 ends, M9 and M10 conducting, and D point is by M9 and M10 electric discharge, and this also has a time delay, at this moment exports OUT step-down.In figure 3, by the size of control Vbp and vbn, charging and discharging size of current can be adjusted, thus adjustment delay time, delay time herein comprises: the response time of discharge and recharge time and inverter I1 to I6.
In aforementioned, due to A point and C point anti-phase, therefore BUF1 and BUF2 mono-controls the slope of rising edge, and another controls the slope of trailing edge.
The present embodiment, the Main Function of I1 to I6 carries out clock shaping, wherein I1, I2, I5 and I6 are generally common inverters, I3 and I4 can be the inverter of customization, this due to B point be have electric capacity, when its charging or electric discharge, just have time delay, this can have influence on the duty ratio that OUT exports, therefore adjustment is needed, the present embodiment, by changing the size (namely adjusting their turnover voltage) of the inner PMOS of I3 and I4 and NMOS tube, adjusts the duty ratio of delay unit, enable OUT provide one close to 50% duty ratio.Herein, duty ratio refers to that high level time accounts for the percentage of whole cycle time, and it is best that general low and high level respectively accounts for half the time, and namely duty ratio is 50%; Due to the impact of discharge and recharge time, in one-period, rise time and fall time can account for the long period, and duty ratio can be poor, therefore carrys out shaping by inverter, the final output rise time made and fall time very short, duty ratio can close to 50%.
The delay unit of the present embodiment is in series by the hungry buffer of multiple electric current, and be connected in series load capacitance in the output of the hungry buffer of each electric current respectively with between supply voltage and ground, thus realize time delay by the discharge and recharge of load capacitance, this kind of structure due to delay unit inside be all comparator configuration, their time of delay is all very short, response time quickly, therefore can be operated in the frequency of hundreds of Mhz to 1GHz, is suitable for high speed circuit and uses.
Please refer to Fig. 4, is the structural representation of the embodiment of the delay phase-locked loop that the embodiment of the present invention provides.
As shown in Figure 4, it comprises: phase discriminator, charge pump, offset generating circuit, inner voltage controlled delay line and outside voltage controlled delay line.Wherein phase discriminator, charge pump, offset generating circuit are introduced in the introduction, are not repeated herein.
In the diagram, voltage controlled delay line comprises two kinds: one is inner voltage controlled delay line, and another kind is outside voltage controlled delay line, and wherein inner voltage controlled delay line is for phase-locked, and outside voltage controlled delay line is the clock for providing out of phase time delay.Wherein the structure of inner voltage controlled delay line and outside voltage controlled delay line all can as shown in Figure 5, be in series by delay unit 1 to delay unit n, wherein n be more than or equal to 1 positive integer.
For inner voltage controlled delay line, because it is for phase-locked, therefore its phase delay is the integral multiple of 360 ° or 360 °.Being assumed to be its phase delay is 360 °, if so each delay unit provides the phase delay of 45 °, so need 8 delay unit series connection, if each delay unit provides the phase delay of 60 °, then need 6 delay unit series connection, if that is each delay unit provides the phase delay of N °, then need (360 ° of ÷ N °) individual delay unit series connection.But the number of delay unit is unsuitable too many also should not very little, because the capital of the structure of delay unit and the parasitic capacitance of itself affects delay time herein.
Lift an example below to illustrate: such as input is 400M clock, and needs the time delay of 45 °; So can design voltage controlled delay line and just need 8 delay unit series connection, each delay unit time delay 45 °, the chances are 1/400M/8=312.5ps, and the effect of phase discriminator, charge pump, offset generating circuit, inner this line of voltage controlled delay line is exactly by adjustment vbp and vbn, make the time delay of each delay unit just in time reach 312.5ps, complete lock-out state.
For outside voltage controlled delay line, as shown in Figure 5, if each delay unit provides the phase delay of 45 °, then outside voltage controlled delay line 1 only needs a delay unit, outside voltage controlled delay line 2 needs 2 delay units series connection, individual delay unit series connection that outside voltage controlled delay line n needs (m ° ÷ 45 °).
As shown in Figure 5, the present embodiment can adopt the outside voltage controlled delay line of the delay unit with varying number to meet different latency requirement, and only need an offset generating circuit to provide Vbp and Vbn, namely Vbp and Vbn that the offset generating circuit in Fig. 5 exports is connected respectively to outside portion voltage controlled delay line 1, outside voltage controlled delay line 2, on the corresponding pin of outside voltage controlled delay line n, very save chip area
In addition, because Vbp and Vbn is voltage signal, its high-speed clock signal that is far from is so responsive, therefore outside voltage controlled delay line can be placed near corresponding position instead of DLL according to demand, like this when drawing domain, ensure all outside voltage controlled delay lines all will and the voltage-controlled delay line structure consistent (reduce the mismatch between them, ensure that each delay unit is consistent as far as possible) of DLL inside.In addition, when outside voltage controlled delay line quantity is more, may there is the problem of driving force deficiency in Vbp and Vbn, and this can be solved by the mode increasing driving force.
The delay phase-locked loop of the present embodiment, there is provided phase-locked by inner voltage controlled delay line, the clock of time delay is provided by outside voltage controlled delay line, such as: 45 ° of phase clocks or 90 ° of phase clocks etc., this kind of structure can be placed near desired location due to outside voltage controlled delay line, and do not need to be placed on delay phase-locked loop inside, because this reducing the line on high-frequency clock, avoid the problem causing clock inaccurate because line is long, and due to voltage control signal Vbp and Vbn that inner voltage controlled delay line and outside voltage controlled delay line all use offset generating circuit to produce, therefore an offset generating circuit is only needed, thus can chip area be reduced.
Above disclosedly be only a kind of preferred embodiment of the present invention, certainly the interest field of the present invention can not be limited with this, one of ordinary skill in the art will appreciate that all or part of flow process realizing above-described embodiment, and according to the equivalent variations that the claims in the present invention are done, still belong to the scope that invention is contained.
Claims (10)
1. a delay unit, is characterized in that: comprising: the hungry buffer of electric current of multiple series connection, the output of the hungry buffer of each electric current is connected in series load capacitance respectively with between supply voltage and ground.
2. delay unit as claimed in claim 1, is characterized in that: the inverter of being connected by even number between the hungry buffer of described electric current connects.
3. delay unit as claimed in claim 2, is characterized in that: the hungry buffer of electric current is transported in the input of described delay unit after the inverter process that even number is connected, and the output of described delay unit exports after the inverter process that even number is connected.
4. the delay unit according to any one of claim 1-3, is characterized in that: the hungry buffer of each electric current comprises: nmos pass transistor I, nmos pass transistor II, PMOS transistor I and PMOS transistor II; The source electrode of described PMOS transistor I is connected with supply voltage, and grid controls by voltage control signal Vbp, and drain electrode is connected with the source electrode of described PMOS transistor II; The drain electrode of described nmos pass transistor I is connected with the drain electrode of described PMOS transistor II, and source electrode is connected with the drain electrode of described nmos pass transistor II; The source ground of described nmos pass transistor II, grid controls by voltage control signal Vbn; The grid of described PMOS transistor II and nmos pass transistor I is connected to the input of the hungry buffer of this electric current, and described PMOS transistor II is connected the output for this current-steering buffer with the drain electrode of nmos pass transistor I.
5. delay unit as claimed in claim 4, it is characterized in that: the load capacitance between the output of current-steering buffer and supply voltage is realized by PMOS transistor III, source electrode, the drain electrode of described PMOS transistor III are all connected with supply voltage, and grid is connected with the drain electrode of PMOS transistor II; Load capacitance between the output of described current-steering buffer and ground is realized by nmos pass transistor III, and described nmos pass transistor III source electrode, drain electrode are all connected to ground, and grid is connected with the drain electrode of nmos pass transistor I.
6. a voltage controlled delay line, it is characterized in that: comprising: the delay unit of one or more cascade, described delay unit comprises: the hungry buffer of the electric current of multiple series connection, the output of the hungry buffer of each electric current and be serially connected with load capacitance respectively between supply voltage and ground.
7. voltage controlled delay line as claimed in claim 6, it is characterized in that: the inverter of being connected by even number between the hungry buffer of described electric current connects, the hungry buffer of electric current is transported in the input of described delay unit after the inverter process that even number is connected, and the output of described delay unit exports after the inverter process that even number is connected.
8. voltage controlled delay line as claimed in claims 6 or 7, is characterized in that: the hungry buffer of each electric current comprises: nmos pass transistor I, nmos pass transistor II, PMOS transistor I and PMOS transistor II; The source electrode of described PMOS transistor I is connected with supply voltage, and grid controls by voltage control signal Vbp, and drain electrode is connected with the source electrode of described PMOS transistor II; The drain electrode of described nmos pass transistor I is connected with the drain electrode of described PMOS transistor II, and source electrode is connected with the drain electrode of described nmos pass transistor II; The source ground of described nmos pass transistor II, grid controls by voltage control signal Vbn; The grid of described PMOS transistor II and nmos pass transistor I is connected to the input of the hungry buffer of this electric current, and described PMOS transistor II is connected the output for this current-steering buffer with the drain electrode of nmos pass transistor I.
9. a delay phase-locked loop, comprise: offset generating circuit and voltage controlled delay line, described offset generating circuit exports voltage control signal Vbp and Vbn controlling voltage controlled delay line, it is characterized in that: described voltage controlled delay line comprises: for phase-locked inside voltage controlled delay line with for providing the one or more parallel outside voltage controlled delay line of delay clock, described inner voltage controlled delay line and outside voltage controlled delay line all comprise the delay unit of one or more cascade, described delay unit comprises further: the hungry buffer of electric current of multiple series connection, the output of the hungry buffer of each electric current and be serially connected with load capacitance respectively between supply voltage and ground.
10. delay phase-locked loop as claimed in claim 9, it is characterized in that: the inverter of being connected by even number between the hungry buffer of described electric current connects, the hungry buffer of electric current is transported in the input of described delay unit after the inverter process that even number is connected, and the output of described delay unit exports after the inverter process that even number is connected.
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| CN107395166A (en) * | 2017-07-18 | 2017-11-24 | 中国电子科技集团公司第二十四研究所 | Clock duty cycle stabilizing circuit based on delay lock phase |
| US10715122B2 (en) | 2018-04-30 | 2020-07-14 | Qualcomm Incorporated | Voltage-controlled delay generator |
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| CN110045372B (en) * | 2019-03-11 | 2021-03-23 | 西安电子科技大学 | Ultra-wideband pulse signal transmitting device and ultra-wideband pulse radar system |
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| CN110673113B (en) * | 2019-08-16 | 2021-08-10 | 西安电子科技大学 | High-precision low-kickback-noise clock regeneration delay chain |
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Application publication date: 20150325 |