CN103779399A - 一种具有超结结构的半导体器件 - Google Patents

一种具有超结结构的半导体器件 Download PDF

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CN103779399A
CN103779399A CN201410058288.8A CN201410058288A CN103779399A CN 103779399 A CN103779399 A CN 103779399A CN 201410058288 A CN201410058288 A CN 201410058288A CN 103779399 A CN103779399 A CN 103779399A
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刘侠
杨东林
罗义
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XI'AN SEMIPOWER ELECTRONIC TECHNOLOGY Co Ltd
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Abstract

本发明一种具有超结结构的半导体器件，包括从下到上依次设置的N型掺杂半导体衬底和内部设有第一P型填充阱区、第二P型填充阱区和第三P型填充阱区N型掺杂外延层；第一P型填充阱区的上侧设有第一P型掺杂区，第一P型掺杂区中设有N型掺杂区，第二P型填充阱区上侧设有第二P型掺杂区；包括第二P型填充阱区、第二P型掺杂区、第三P型填充阱区和对应的部分N型掺杂外延层的终端耐压结构区域T布置在包括第一P型填充阱区、第一P型掺杂区、N型掺杂区和对应的部分N型掺杂外延层构成原胞源极区域C的***；两者上设置在部分栅氧化层上方介质层内的多晶硅对应原胞源极区域C和终端结构区域T的部分分别构成栅电极和多晶硅场板结构。

Description

一种具有超结结构的半导体器件
技术领域
本发明属于半导体功率器件技术领域，涉及一种高压功率器件，具体的为一种具有超结结构的半导体器件。
背景技术
传统纵向高压功率器件用低掺杂的外延漂移层作电压支持层，其导通电阻主要就是漂移层电阻。漂移层的耐压能力由其厚度和掺杂浓度决定。所以，为了提高击穿电压，必须同时增加漂移层厚度和降低其掺杂浓度。这就使得漂移层的电阻不断增加，在导通状态时(尤其是高压时)，漂移层电阻占导通电阻的绝大部分。
纵向超结半导体器件是一种具有金属氧化物半导体器件的绝缘栅结构优点同时具有高电流密度低导通电阻优点的新型器件，它是一种能用于有效地降低传统纵向高压功率器件的导电损耗的新型器件。它是基于电荷平衡原理的电荷补偿型器件。
超结半导体器件的基本特点是其由相互交替的，掺杂浓度较高的P型和N型区域构成的漂移区来实现耐压。在理想情况下，P型与N型掺杂区域的电荷严格平衡以便在达到击穿电压前，两区能实现完全耗尽，于是净余电荷急剧下降几乎为零。根据泊松方程，净电荷为零时，电场变为常数，这使得漂移区电场变为水平，即由传统的三角形分布变成矩形分布。在这种情况下，器件的击穿电压变得只与漂移区厚度有关，而与漂移区掺杂浓度无关，故可以通过适当增大漂移区掺杂浓度来降低导通电阻。
尽管如此，超结半导体器件在商业化的路途上困难重重，其设计难点在于器件的终端耐压结构。超结半导体器件的终端耐压结构有别于传统的纵向高压器件，这是因为超结半导体器件高浓度漂移区的存在，使得元胞区与终端耐压区之间的过渡区具有不规则的电场分布，从而降低器件的可靠性。在相关的现有技术中，有设计者提出在终端耐压区变化P/N区域的宽度比例，也有设计者提出在终端耐压区采用低浓度掺杂等，但这些方式均会带来工艺上的复杂度，从而增加成本，甚至会影响生产良率。
发明内容
针对现有技术中的问题，本发明提供一种具有超结结构的半导体器件；不增加工艺难度和成本，保证耐压要求，不增加额外的工艺制造过程，保证原有的终端结构尺寸，优化终端结构的表面电势分布，提高器件的可靠性。
本发明是通过以下技术方案来实现：
一种具有超结结构的半导体器件，包括从下到上依次设置的N型掺杂半导体衬底和N型掺杂外延层；N型掺杂外延层内部设有P型填充阱区，P型填充阱区包括由内向外设置且结构相同的第一P型填充阱区、第二P型填充阱区和第三P型填充阱区；第一P型填充阱区的上侧设有第一P型掺杂区，第一P型掺杂区中设有N型掺杂区，第二P型填充阱区上侧设有第二P型掺杂区；所述的第一P型填充阱区、第一P型掺杂区、N型掺杂区和对应的部分N型掺杂外延层共同构成原胞源极区域C；所述的第二P型填充阱区、第二P型掺杂区、第三P型填充阱区和对应的部分N型掺杂外延层共同构成终端耐压结构区域T；上表面最***设置有N型掺杂电极接触区的终端耐压结构区域T布置在原胞源极区域C的***；原胞源极区域C和终端耐压结构区域T上方依次设有栅氧化层、介质层和上金属层，部分栅氧化层上方介质层内设置多晶硅；上金属层穿过栅氧化层和介质层对应连接在第一P型掺杂区和第二P型掺杂区上方的部分构成源极金属电极，对应连接在N型掺杂电极接触区上方的部分构成截止环电极；设置在N型掺杂半导体衬底下方的下金属层构成漏极金属电极；多晶硅对应原胞源极区域C的部分构成栅电极；多晶硅对应终端结构区域T的部分构成多晶硅场板结构，与源极金属电极相连的部分为内侧多晶硅场板结构，与截止环电极相连为外侧多晶硅场板结构，内侧多晶硅场板结构与外侧多晶硅场板结构之间设置有若干呈间隔环形设置的中间多晶硅场板结构。
优选的，中间多晶硅场板结构由若干浮置的多晶硅绕制而成。
优选的，原胞源极区域C内沿长度方向第一P型填充阱区和N型掺杂外延层交替排列；终端结构区域T内沿长度方向第二P型填充阱区和第三P型填充阱区按顺序依次与N型掺杂外延层交替排列。
进一步，中间多晶硅场板结构在终端结构区域T的长度方向上平行设置于第三P型填充阱区上方，在终端结构区域T的宽度方向上垂直设置于第三P型填充阱区上方，在方向变换时采用圆弧过渡。
再进一步，中间多晶硅场板结构在终端结构区域T的长度方向上与对应的第三P型填充阱区向外呈错位设置。
优选的，P型填充阱区采用深槽腐蚀和硅回填工艺，表面平坦化处理后形成。
与现有技术相比，本发明具有以下有益的技术效果：
本发明通过在终端耐压结构区域设置的多晶硅场板结构，使得当半导体器件在反向耐压时，多晶硅场板结构在半导体器件的终端耐压结构表面引入多个电场峰值，从而降低表面电场，优化了表面电势分布，提高器件可靠性；并且多晶硅场板结构的设置和分布能够与现有制造工艺步骤统一，不会增加半导体器件的制造工艺。
进一步的，利用在长度方向上间隔设置的P型填充阱区和N型掺杂外延区，增加其在横向的耐压，提高了其使用的可靠性；同时配置由圆弧过渡且在宽度方向上垂直设置的中间多晶硅场板结构，在其表面形成电荷运动的环路，从而使得表面电势分布更加均匀稳定，提高耐压能力和工作稳定性。
进一步的，利用分离向外错位设置的多晶硅场板结构实现阻断特性，多晶硅场板结构的位置布局使与之有交叠的P型填充阱区的电势在多晶硅场板结构的引导下向终端结构耐压方向延伸，同时又不影响到与之相邻的另一个P型填充阱区，从而缓和的降低表面电场强度，增大了器件的横向耐压。
附图说明
图1是本发明部分终端耐压结构的表面俯视示意图。
图2是本发明实施例所述结构在图1中所示A-A’向的剖面图。
图3是本发明图1中所示结构的B-B’向剖面图。
图4是本发明图1中所示结构的C-C’向剖面图。
图中：N型掺杂半导体衬底1，N型掺杂外延层2，P型填充阱区3，第一P型填充阱区31，第二P型填充阱区32，第二P型填充阱区33，第一P型掺杂区41，第二P型掺杂区42，N型掺杂区51，N型掺杂电极接触区52，栅电极61，内侧多晶硅场板结构62，中间多晶硅场板结构63，外侧多晶硅场板结构64，介质层7，源极金属电极8，截止环电极9，漏极金属电极10。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明，所述是对本发明的解释而不是限定。
本发明一种具有超结结构的半导体器件，如图2所示，其包括从下到上依次设置的N型掺杂半导体衬底1和N型掺杂外延层2；N型掺杂外延层2内部设有P型填充阱区3，P型填充阱区3包括由内向外设置且结构相同的第一P型填充阱区31、第二P型填充阱区32和第三P型填充阱区33；第一P型填充阱区31的上侧设有第一P型掺杂区41，第一P型掺杂区41中设有N型掺杂区51，第二P型填充阱区32上侧设有第二P型掺杂区42；第一P型填充阱区31、第一P型掺杂区41、N型掺杂区51和对应的部分N型掺杂外延层2共同构成原胞源极区域C；所述的第二P型填充阱区32、第二P型掺杂区42、第三P型填充阱区33和对应的部分N型掺杂外延层2共同构成终端耐压结构区域T；上表面最***设置有N型掺杂电极接触区52的终端耐压结构区域T布置在原胞源极区域C的***；原胞源极区域C和终端耐压结构区域T上方依次设有栅氧化层、介质层7和上金属层，部分栅氧化层上方介质层7内设置多晶硅；上金属层穿过栅氧化层和介质层7对应连接在第一P型掺杂区41和第二P型掺杂区42上方的部分构成源极金属电极8，对应连接在N型掺杂电极接触区52上方的部分构成截止环电极9；设置在N型掺杂半导体衬底1下方的下金属层构成漏极金属电极10；多晶硅对应原胞源极区域C的部分构成栅电极61；多晶硅对应终端结构区域T的部分构成多晶硅场板结构，与源极金属电极8相连的部分为内侧多晶硅场板结构62，与截止环电极9相连为外侧多晶硅场板结构64，内侧多晶硅场板结构62与外侧多晶硅场板结构64之间设置有若干呈间隔环形设置的中间多晶硅场板结构63。
本优选实施例中，如图1-4所示，中间多晶硅场板结构63由若干浮置的多晶硅绕制而成，其长度和相互的间距都能够相等或不等设置，本优选实例中以相等为例进行说明。如图2所示，其中左侧是在沿A-A’方向剖视后，原胞源极区域C中最小的重复单元，其宽度由半导体器件的导通电阻和耐压要求决定，数量不限；原胞源极区域C内沿长度方向第一P型填充阱区31和N型掺杂外延层2交替排列；终端结构区域T内沿长度方向第二P型填充阱区32和第三P型填充阱区按顺序依次与N型掺杂外延层2交替排列。其中，P型填充阱区3和N型掺杂外延层2之间的宽度比例和浓度比例由半导体器件所应满足的导通电阻和耐压要求共同决定。
如图1所示，中间多晶硅场板结构63在终端结构区域T的长度方向上平行设置于第三P型填充阱区33上方，在终端结构区域T的宽度方向上垂直设置于第三P型填充阱区33上方，在方向变换时采用圆弧过渡。其中，如图2所示，中间多晶硅场板结构63在终端结构区域T的长度方向上与对应的第三P型填充阱区33向外呈错位设置。P型填充阱区3采用深槽腐蚀和硅回填工艺，表面平坦化处理后形成，其深度、深宽比和回填掺杂浓度由半导体器件的设计耐压要求所决定。
本发明在不增加工艺难度和成本的前提下，能够保证耐压要求的同时，不会增加额外的工艺制造过程，不会加长终端结构原先的尺寸，并且可以更好的优化终端结构的表面电势分布，有效降低表面的电场强度，阻断可动离子移动的路径，提高器件的可靠性。
本发明采用如下方法来制备：
1）取一块N型高浓度掺杂硅片作为N型掺杂半导体衬底1，外延生长N型掺杂外延层2；
2）采用深槽腐蚀和硅回填工艺，表面平坦化处理后形成包括第一P型填充阱区31、第二P型填充阱区32、第二P型填充阱区33的P型填充阱区3；
3）采用离子注入和后续的退火工艺形成阱结构相同的第一P型掺杂区41和第二P型掺杂区42；
4）然后经过热生长生成栅氧化层，接着淀积多晶硅，并进行刻蚀形成栅极61和包括内侧多晶硅场板结构62、中间多晶硅场板结构63、外侧多晶硅场板结构64的多晶硅场板结构，然后经过离子注入形成N型掺杂区51和N型掺杂电极接触区52；
5）经过淀积和刻蚀工艺，形成源极金属电极8作为半导体器件的源极，中间多晶硅场板63作为半导体器件场板，上金属层穿过栅氧化层和介质层7对应连接在N型掺杂电极接触区52上方的部分作为半导体器件的截止环电极9，漏极金属电极10作为半导体器件的漏极。最后进行后续钝化处理。

Claims (6)

1.一种具有超结结构的半导体器件，其特征在于，包括从下到上依次设置的N型掺杂半导体衬底（1）和N型掺杂外延层（2）；N型掺杂外延层（2）内部设有P型填充阱区（3），P型填充阱区（3）包括由内向外设置且结构相同的第一P型填充阱区（31）、第二P型填充阱区（32）和第三P型填充阱区（33）；第一P型填充阱区（31）的上侧设有第一P型掺杂区（41），第一P型掺杂区（41）中设有N型掺杂区（51），第二P型填充阱区（32）上侧设有第二P型掺杂区（42）；
所述的第一P型填充阱区（31）、第一P型掺杂区（41）、N型掺杂区（51）和对应的部分N型掺杂外延层（2）共同构成原胞源极区域C；所述的第二P型填充阱区（32）、第二P型掺杂区（42）、第三P型填充阱区（33）和对应的部分N型掺杂外延层（2）共同构成终端耐压结构区域T；上表面最***设置有N型掺杂电极接触区（52）的终端耐压结构区域T布置在原胞源极区域C的***；
原胞源极区域C和终端耐压结构区域T上方依次设有栅氧化层、介质层（7）和上金属层，部分栅氧化层上方介质层（7）内设置多晶硅；上金属层穿过栅氧化层和介质层（7）对应连接在第一P型掺杂区（41）和第二P型掺杂区（42）上方的部分构成源极金属电极（8），对应连接在N型掺杂电极接触区（52）上方的部分构成截止环电极（9）；设置在N型掺杂半导体衬底（1）下方的下金属层构成漏极金属电极（10）；多晶硅对应原胞源极区域C的部分构成栅电极（61）；多晶硅对应终端结构区域T的部分构成多晶硅场板结构，与源极金属电极（8）相连的部分为内侧多晶硅场板结构（62），与截止环电极（9）相连为外侧多晶硅场板结构（64），内侧多晶硅场板结构（62）与外侧多晶硅场板结构（64）之间设置有若干呈间隔环形设置的中间多晶硅场板结构（63）。
2.根据权利要求1所述的一种具有超结结构的半导体器件，其特征在于，所述的中间多晶硅场板结构（63）由若干浮置的多晶硅绕制而成。
3.根据权利要求1或2所述的一种具有超结结构的半导体器件，其特征在于，所述的原胞源极区域C内沿长度方向第一P型填充阱区（31）和N型掺杂外延层（2）交替排列；终端结构区域T内沿长度方向第二P型填充阱区（32）和第三P型填充阱区按顺序依次与N型掺杂外延层（2）交替排列。
4.根据权利要求3所述的一种具有超结结构的半导体器件，其特征在于，所述的中间多晶硅场板结构（63）在终端结构区域T的长度方向上平行设置于第三P型填充阱区（33）上方，在终端结构区域T的宽度方向上垂直设置于第三P型填充阱区（33）上方，在方向变换时采用圆弧过渡。
5.根据权利要求4所述的一种具有超结结构的半导体器件，其特征在于，所述的中间多晶硅场板结构（63）在终端结构区域T的长度方向上与对应的第三P型填充阱区（33）向外呈错位设置。
6.根据权利要求1所述的一种具有超结结构的半导体器件，其特征在于，所述的P型填充阱区（3）采用深槽腐蚀和硅回填工艺，表面平坦化处理后形成。
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