CN103744213A - Array base-plate and preparation method thereof - Google Patents
Array base-plate and preparation method thereof Download PDFInfo
- Publication number
- CN103744213A CN103744213A CN201310736155.7A CN201310736155A CN103744213A CN 103744213 A CN103744213 A CN 103744213A CN 201310736155 A CN201310736155 A CN 201310736155A CN 103744213 A CN103744213 A CN 103744213A
- Authority
- CN
- China
- Prior art keywords
- array base
- metal layer
- metal level
- base palte
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Liquid Crystal (AREA)
- Electroluminescent Light Sources (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array base-plate and a preparation method thereof, belonging to the display field, wherein the array base-plate can solve the problems that the larger segment difference of each subsequent functional layer and worse liquid crystal orientation are caused by a deeper opening area formed above an organic film due to the fact that a hole is formed in the thicker organic film. The array base-plate provided by the invention comprises an organic film which is arranged on the base-plate, wherein the organic film is provided with a first through hole area, the direction of the first through hole area far away from the base-plate is provided with an opening area, and the opening area is provided with a first metal layer. The opening area is filled with the first metal layer, and the whole orientation layer is provided with a small segment difference in the opening area, so that the bad liquid crystal orientation can be beneficially prevented; and meanwhile, the first metal layer completely covers a lower third metal layer, so that the corrosion of the third metal layer can be prevented due to the fact that the third metal layer is avoided being naked outside the array base-plate and is not in contact with moist air.
Description
Technical field
The invention belongs to demonstration field, be specifically related to a kind of array base palte and preparation method thereof.
Background technology
As shown in Figure 1, in array base palte preparation technology of the prior art, due to organic film 4 thicker (thicker organic film can reduce electric capacity, reduce substrate load, thereby reduce power consumption), when organic film 4 is offered the first via area 9, the degree of depth of this first via area 9 is larger, causes the section of each functional layer of subsequent deposition to differ from larger.For example, the 3rd metal level 6(ITO layer for example), passivation layer 5(PVX layer for example) all caused larger section poor.Meanwhile, the top of the 3rd metal level 6 has formed darker open area 11, if subsequent technique applies oriented layer on the 3rd metal level 6, whole oriented layer can be in open area 11 to have larger section poor, more easily cause liquid crystal aligning bad.Meanwhile, the 3rd exposed outside at array base palte of metal level 6, touch malaria and corrode.
Summary of the invention
The object of the invention is to solve that in prior art, because organic film is thicker, on organic film, to hold the open area of via hole above can causing darker, thereby cause the section of follow-up each functional layer poor larger, the problem that liquid crystal aligning is bad, provides a kind of array base palte that above-mentioned open area is filled.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, comprise the functional layer being arranged on substrate, described functional layer has the first via area, in the direction away from substrate of the first described via area, there is open area, it is characterized in that, described open area is provided with the first metal layer.
Because the first metal layer has been filled above-mentioned open area, if subsequent technique applies oriented layer on above-mentioned the first metal layer, it is poor that whole oriented layer can have in above-mentioned open area less section, is more conducive to avoid liquid crystal aligning bad.Meanwhile, the first metal layer covers the 3rd metal level of below completely, can make the 3rd metal level avoid the exposed outside at array base palte, touch malaria and corrode.
Preferably, described functional layer is organic film.
Preferably, the first via area of described functional layer is provided with the second metal level near a side of substrate.
Further preferably, the second described metal level is that metal level is leaked in source.
Preferably, between the second described metal level and described the first metal layer, be provided with the 3rd metal level, the 3rd described metal level is connected by being arranged on the second via hole of insulation course between the two with the second metal level.
Preferably, the material of described the first metal layer is any one in tin indium oxide, gold, silver, copper, aluminium, titanium, chromium, molybdenum, cadmium, nickel, cobalt, electrical conductivity alloy.
Another object of the present invention is to provide a kind of preparation method of above-mentioned array base palte, comprises and by composition technique, in described open area, forms the step of the first metal layer.
Preferably, further comprising the steps of before the step that forms the first metal layer:
S1. by composition technique, in the organic film part corresponding with the second metal level, form the first via area;
S2. at organic film and the first via area depositing insulating layer;
S3. by composition technique, in the insulation course part corresponding with the first via area, offer the second via hole;
S4. at insulation course and the second via hole, form the 3rd metal level.
Further preferably, form the first metal layer employing negative photoresist, form the first via area and adopt eurymeric photoresist, in the step of formation the first metal layer and formation the first via area, use same mask plate.
Array base palte of the present invention is due to above-mentioned open area is filled, and during follow-up coating oriented layer, poor being reduced of the whole section of oriented layer, can cause the liquid crystal aligning of oriented layer bad by avoiding.Meanwhile, the first metal layer covers the 3rd metal level of below completely, can make the 3rd metal level avoid the exposed outside at array base palte, touch malaria and corrode.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of array base palte in prior art.
Fig. 2 has the schematic cross-section of the array base palte of the first metal layer in the embodiment of the present invention 1.
Fig. 3 is the schematic cross-section that has formed the array base palte of insulation course and the second metal level in the embodiment of the present invention 2.
Fig. 4 is the schematic cross-section that has formed the array base palte of the first via area in the embodiment of the present invention 2.
Fig. 5 is the schematic cross-section that has formed the array base palte of the second via hole in the embodiment of the present invention 2.
Fig. 6 is the schematic cross-section that has formed the array base palte of the 3rd metal level in the embodiment of the present invention 2.
Fig. 7 has formed the schematic cross-section of the array base palte of the first metal layer in the embodiment of the present invention 2.
Wherein: 1. substrate; 2. insulation course; 3. the second metal level; 4. organic film; 5. passivation layer; 6. the 3rd metal level; 7. the first metal layer; 8. mask plate; 9. the first via area; 10. the second via hole; 11. open areas.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 2, the present embodiment provides a kind of array base palte, comprises substrate 1, and the insulation course 2 arranging on substrate 1, and the first via area 9 that patterned the second metal level 3, the second metal levels 3 are arranged on organic film 4 is set on insulation course 2; Then set gradually patterned passivation layer 5, patterned the 3rd metal level 6, the second metal levels 3 are connected with the 3rd metal level 6 by second via hole 10 that is positioned at the first via area 9 of passivation layer 5; The 3rd metal level 6 is arranged in and in the direction away from substrate 1 of the first via area 9, has open area 11(figure and overlap with the first metal layer 7), in open area 11, be provided with patterned the first metal layer 7.
Because the first metal layer 7 has been filled open area 11, if subsequent technique applies oriented layer on the first metal layer 7, whole oriented layer can be in open area 11 to have less section poor, be more conducive to avoid liquid crystal aligning bad.
As shown in Figure 2, preferred, the second metal level 3 is for leaking metal level in source; Preferably, the material of the first metal layer 7 is any one in tin indium oxide, gold, silver, copper, aluminium, titanium, chromium, molybdenum, cadmium, nickel, cobalt, electrical conductivity alloy.The first metal layer 7 covers the 3rd metal level 6 of below completely, can make the 3rd metal level 6 avoid the exposed outside at array base palte, touch malaria and corrode.
As shown in Fig. 3-7, the present embodiment provides a kind of preparation method of above-mentioned array base palte, comprises the following steps:
A. as shown in Figure 3, depositing insulating layer 2 and the second metal level 3 successively on substrate 1, deposition process is prior art category, for example, can adopt vapour deposition process.Substrate 1 can glass substrate, plastic base etc.; The material of insulation course 2 can be silicon dioxide or silicon nitride; The second metal level 3 can be that metal level is leaked in source, and the material that metal level is leaked in source is chosen as prior art category.Then the second metal level 3 is carried out graphically, graphical technique comprises the steps such as mask exposure, development, etching, is the category of prior art, and this is no longer going to repeat them.
B. as shown in Figure 4, on substrate 1, form organic film 4, be paved with whole substrate 1.The material that the material of organic film 4 is known to the skilled person, formation method can spin coating, spraying etc.Organic film 4 can prevent that upper and lower two conductive layers from crosstalking etc.; But the thickness of other functional layer prepared by the Thickness Ratio of organic film 4 employing deposition process is larger.The part that organic film 4 is corresponding with the first metal layer 7 forms the first via area 9 by graphical technique.Preferably, in the graphical technique of organic film 4, adopt eurymeric photoresist.
C. as shown in Figure 5, then in organic film 4 and the first via area 9 deposit passivation layer 5, the preparation method of passivation layer 5 can be identical with the preparation method of insulation course 2.Then passivation layer 5 is carried out graphically, in the part that passivation layer 5 is corresponding with the first via area 9, offering the second via hole 10.Wherein, graphical technique comprises the steps such as mask exposure, development, etching, is the category of prior art, and this is no longer going to repeat them.
D. as shown in Figure 6, the preparation method at passivation layer 5 and the second via hole 10 area depositions the 3rd metal level 6, the three metal levels 6 can be identical with the preparation method of the second metal level 3.
E. as shown in Figure 7, on the second metal level 3, deposit the first metal layer 7, wherein, the preparation method of the first metal layer 7 can be identical with the preparation method of the second metal level 3.Preferably, graphical technique forms the first metal layer 7 and adopts negative photoresist, and the mask plate 8 that graphical technique formation the first metal layer 7 adopts can be the mask plate 8 in step B.Adopt same mask 8 more can simplify technique, save cost.
Be understandable that, functional layer of the present invention can be also one deck arbitrarily in array base palte, as long as this functional layer is thicker, when this functional layer is opened via hole, the open area of formation is deep, has influence on follow-up functional layer and all belongs to protection scope of the present invention; " filling " of the present invention refers to that the use that does not affect follow-up function layer all belongs to protection scope of the present invention as long as the degree of depth of above-mentioned open area is reduced.
Be understandable that, above embodiment is only used to principle of the present invention is described and the illustrative embodiments that adopts, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (9)
1. an array base palte, comprise the functional layer being arranged on substrate, described functional layer has the first via area, in the direction away from substrate of the first described via area, has open area, it is characterized in that, described open area is provided with the first metal layer.
2. array base palte as claimed in claim 1, is characterized in that, described functional layer is organic film.
3. array base palte as claimed in claim 1, is characterized in that, the first via area of described functional layer is provided with the second metal level near a side of substrate.
4. array base palte as claimed in claim 2, is characterized in that, the second described metal level is that metal level is leaked in source.
5. array base palte as claimed in claim 1, it is characterized in that, between the second described metal level and described the first metal layer, be provided with the 3rd metal level, the 3rd described metal level is connected by being arranged on the second via hole of insulation course between the two with the second metal level.
6. array base palte as claimed in claim 1, is characterized in that, the material of described the first metal layer is any one in tin indium oxide, gold, silver, copper, aluminium, titanium, chromium, molybdenum, cadmium, nickel, cobalt, electrical conductivity alloy.
7. a preparation method for the array base palte as described in as arbitrary in claim 1-6, is characterized in that, comprises and by composition technique, in described open area, forms the step of the first metal layer.
8. a preparation method for array base palte as claimed in claim 7, is characterized in that, further comprising the steps of before the step that forms the first metal layer:
S1. by composition technique, in the organic film part corresponding with the second metal level, form the first via area;
S2. at organic film and the first via area depositing insulating layer;
S3. by composition technique, in the insulation course part corresponding with the first via area, offer the second via hole;
S4. at insulation course and the second via hole, form the 3rd metal level.
9. the preparation method of array base palte as claimed in claim 8, it is characterized in that, form the first metal layer employing negative photoresist, form the first via area and adopt eurymeric photoresist, in the step of formation the first metal layer and formation the first via area, use same mask plate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310736155.7A CN103744213B (en) | 2013-12-25 | 2013-12-25 | A kind of array base palte and preparation method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310736155.7A CN103744213B (en) | 2013-12-25 | 2013-12-25 | A kind of array base palte and preparation method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103744213A true CN103744213A (en) | 2014-04-23 |
CN103744213B CN103744213B (en) | 2016-08-17 |
Family
ID=50501245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310736155.7A Active CN103744213B (en) | 2013-12-25 | 2013-12-25 | A kind of array base palte and preparation method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103744213B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105629617A (en) * | 2016-04-01 | 2016-06-01 | 京东方科技集团股份有限公司 | Display base plate and display device |
CN106681069A (en) * | 2017-01-03 | 2017-05-17 | 京东方科技集团股份有限公司 | Display baseplate, preparation method for same, and display device |
WO2019095214A1 (en) * | 2017-11-16 | 2019-05-23 | 深圳市柔宇科技有限公司 | Tft array structure and binding region thereof, and method for manufacturing binding region |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005352456A (en) * | 2004-05-14 | 2005-12-22 | Nec Kagoshima Ltd | Active matrix type substrate and manufacturing method for the same |
CN101919043A (en) * | 2008-01-21 | 2010-12-15 | 日本电气株式会社 | Display device |
US20110309364A1 (en) * | 2002-04-09 | 2011-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
CN102394231A (en) * | 2011-10-25 | 2012-03-28 | 友达光电股份有限公司 | Chip connecting structure used for liquid crystal display |
-
2013
- 2013-12-25 CN CN201310736155.7A patent/CN103744213B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110309364A1 (en) * | 2002-04-09 | 2011-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
JP2005352456A (en) * | 2004-05-14 | 2005-12-22 | Nec Kagoshima Ltd | Active matrix type substrate and manufacturing method for the same |
CN101919043A (en) * | 2008-01-21 | 2010-12-15 | 日本电气株式会社 | Display device |
CN102394231A (en) * | 2011-10-25 | 2012-03-28 | 友达光电股份有限公司 | Chip connecting structure used for liquid crystal display |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105629617A (en) * | 2016-04-01 | 2016-06-01 | 京东方科技集团股份有限公司 | Display base plate and display device |
CN106681069A (en) * | 2017-01-03 | 2017-05-17 | 京东方科技集团股份有限公司 | Display baseplate, preparation method for same, and display device |
WO2019095214A1 (en) * | 2017-11-16 | 2019-05-23 | 深圳市柔宇科技有限公司 | Tft array structure and binding region thereof, and method for manufacturing binding region |
Also Published As
Publication number | Publication date |
---|---|
CN103744213B (en) | 2016-08-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107808895B (en) | Transparent OLED display and preparation method thereof | |
CN101630640B (en) | Photoresist burr edge-forming method and TFT-LCD array substrate-manufacturing method | |
CN103293790B (en) | Pixel cell and preparation method thereof, array base palte, display device | |
TWI281746B (en) | Liquid crystal display and method of manufacturing the same | |
CN103715267A (en) | TFT, TFT array substrate, manufacturing method of TFT array substrate and display device | |
CN102637636A (en) | Organic thin-film transistor array substrate, method for manufacturing same and display device | |
CN109244086A (en) | A kind of array substrate and preparation method thereof, display panel, display device | |
CN103972046B (en) | Method for manufacturing capacitor and the display equipment including the capacitor | |
CN105374748A (en) | Preparing method of film transistor substrate and prepared film transistor substrate | |
CN102842587B (en) | Array base palte and preparation method thereof, display device | |
CN103915444B (en) | Array substrate, preparation method thereof and liquid crystal display panel | |
CN107818990B (en) | Flexible substrate, preparation method thereof and display | |
CN103545319A (en) | Low-temperature polycrystalline silicon thin film transistor array substrate, manufacturing method thereof and display device | |
CN105607365A (en) | COA substrate and fabrication method therefor | |
CN106019751A (en) | Array substrate and manufacturing method thereof and display device | |
CN204028524U (en) | Display base plate and display device | |
CN107946322A (en) | Array base palte and its manufacture method, display device | |
CN104795407A (en) | Array substrate, production method thereof, display panel and display device | |
CN105097548A (en) | Oxide thin film transistor, array substrate, and respective preparation method and display device | |
CN103744213A (en) | Array base-plate and preparation method thereof | |
CN103489874A (en) | Array substrate, manufacturing method thereof and display device | |
CN105047677A (en) | Display substrate, manufacturing method thereof and display device | |
CN106549022A (en) | Array substrate, manufacturing method thereof, display panel and electronic equipment | |
TW201618168A (en) | Method for manufacturing display panel | |
CN104617049B (en) | A kind of array base palte and preparation method thereof, display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |