CN103489874A - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN103489874A CN103489874A CN201310451037.1A CN201310451037A CN103489874A CN 103489874 A CN103489874 A CN 103489874A CN 201310451037 A CN201310451037 A CN 201310451037A CN 103489874 A CN103489874 A CN 103489874A
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Abstract
The invention provides an array substrate, a manufacturing method thereof, and a display device, and belongs to the technical field of display. The manufacturing method of the array substrate can solve the problems that the array substrate is complex in manufacturing technology and low in transmittance. The manufacturing method of the array substrate comprises the steps that a graph comprising a grid line, a grid, a grid insulating layer, a semiconductor layer and a pixel electrode is formed on a substrate body through a step exposure composition technology; the grid insulating layer does not exceed the upper portion of the grid line and the upper portion of the grid; an isolation layer is formed on the substrate body undergoing the prior steps and a source via hole and a drain via hole which are connected with the semiconductor layer and a first via hole connected with the pixel electrode are formed in the isolation layer; a graph comprising a source and a drain is formed on the substrate body undergoing the prior steps through a composition technology; the source and the drain are electrically connected with the semiconductor layer through the source via hole and the drain via hole, and the drain is electrically connected with the pixel electrode through the first via hole.
Description
Technical field
The invention belongs to the Display Technique field, be specifically related to a kind of array base palte and preparation method thereof, display unit.
Background technology
The liquid crystal indicator of TN (twisted-nematic) pattern has fast response time, low cost and other advantages, is a kind of important model of liquid crystal indicator.
As shown in Figure 1, in the array base palte of TN pattern, grid 21/ grid line 22 of thin-film transistor is formed in substrate 9, gate insulation layer 31 cover gate 21/ grid lines 22, gate insulation layer 31 is provided with semiconductor layer 41 (semiconductor layer 41 adds that ohmic contact layer, transition zone etc. form the active area of thin-film transistor), pixel electrode 11, source electrode 71, drains 72, source electrode 71, draining 72 is electrically connected to semiconductor layer 41, drains 72 also with pixel electrode 11, to be electrically connected to.Simultaneously, also can be provided with other structure (not shown)s such as data wire, public electrode wire, alignment film in array base palte; And with the color membrane substrates of array base palte to box on, also be provided with other structures such as public electrode.
As shown in Figure 1, in the array base palte of existing TN pattern, grid 21/ grid line 22, semiconductor layer 41 pixel electrodes 11 need in different composition technique, to manufacture respectively, and being these structures of manufacture at least needs to carry out 3 photoetching, so its complicated process of preparation.
Simultaneously, gate insulation layer 31 has covered whole substrate 9, and gate insulation layer 31 also has distribution at pixel electrode 11 places, and the gate insulation layer 31 of this position can affect printing opacity, thereby reduces the transmitance of array base palte.
Summary of the invention
Technical problem to be solved by this invention comprises, the low problem for array base palte complicated process of preparation, the transmitance of existing TN pattern, provide array base palte that a kind of preparation technology is simple, transmitance is high and preparation method thereof, display unit.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte preparation method, and it comprises:
Step 1: in substrate, by the composition technique of using the ladder exposure, form the figure that comprises grid line, grid, gate insulation layer, semiconductor layer, pixel electrode; Wherein, gate insulation layer does not exceed the top of grid line and grid;
Step 2: form separator in the substrate that completes abovementioned steps, form source electrode via hole and the drain via be connected with semiconductor layer and the first via hole be connected with pixel electrode in separator;
Step 3: in the substrate that completes abovementioned steps, by composition technique, form the figure that comprises source electrode, drain electrode; Wherein, source electrode, drain electrode are electrically connected to semiconductor layer by source electrode via hole, drain via respectively, and drain electrode is electrically connected to pixel electrode by the first via hole.
Wherein, " composition technique " comprises steps such as forming rete, coating photoresist, exposure, development, etching, stripping photoresist, and it can remove unwanted part in rete by above-mentioned steps, thereby makes the remainder of rete form required figure.
Wherein, " ladder exposure " refers to that the diverse location to photoresist layer carries out exposure in various degree, thereby the photoresist layer after making to develop is in the thickness difference of diverse location, in order to complete follow-up composition technique.
In array base palte preparation method of the present invention, grid line/grid, gate insulation layer, semiconductor layer, pixel electrode form in a composition technique simultaneously, i.e. its needs single exposure (1Mask) technique, so its preparation technology is simple, efficiency is high; Simultaneously, because the gate insulation layer of its array base palte does not exceed grid and grid line top, therefore its pixel electrode place does not have gate insulation layer, so gate insulation layer can not exert an influence to seeing through of light, and transmitance is high.
Preferably, described step 1 specifically comprises:
Step 12, the photoresist layer ladder is exposed and develops, make gate location retain the photoresist layer of the first thickness, the grid line position retains the photoresist layer of the second thickness, the pixel electrode position retains the photoresist layer of the 3rd thickness, all the other positions are without the photoetching glue-line, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness;
Step 13, remove semiconductor material layer, insulation material layer, transparent conductive material layer without the photoresist zone;
Step 14, remove the photoresist layer of the 3rd thickness, the semiconductor material layer of pixel electrode position is exposed;
Step 15, the semiconductor material layer of removing the pixel electrode position, insulation material layer, the figure of formation pixel electrode;
Step 16, remove the photoresist layer that thickness equals grid line position remaining photoresist layer thickness, the semiconductor layer of grid line position is exposed;
Step 17, remove the semiconductor material layer of grid line position, form the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
Further preferably, described step 17 specifically comprises: remove the semiconductor material layer of grid line position, and remove the insulation material layer of grid line position, form the figure of grid line.
Further preferably, described step 11 also comprises: at transparent conductive material layer and insulating material interlayer, form the grid metal level; Described step 13 also comprises: remove the grid metal level without the photoresist zone; Described step 15 also comprises: the grid metal level of removing the pixel electrode position.
Further preferably, the exposure of described ladder realizes by gray scale mask plate or intermediate tone mask plate.
Preferably, described separator is any one in planarization layer, passivation layer, etching barrier layer.
Further preferably, described separator is planarization layer, and is made by the photosensitive resin material.
Preferably, described semiconductor layer is made by metal oxide semiconductor material.
Preferably, described step 3 specifically comprises:
Metal level is leaked in step 31, formation source;
Step 32, formation photoresist layer exposure, retain photoresist layer in separated source electrode position and drain locations, and all the other positions are without the photoetching glue-line; Wherein, the source electrode position comprises the source electrode via hole, and drain locations comprises drain via and the first via hole;
Step 33, remove without the source in photoetching glue-line zone and leak metal level, then remove photoresist layer, form the figure of source electrode and drain electrode.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, and it comprises grid, grid line, gate insulation layer, semiconductor layer, pixel electrode, separator, source electrode, drain electrode, and
Described grid, grid line comprise transparent conductive material layer;
Described gate insulation layer does not exceed the top of grid line and grid;
Described separator cover gate, gate insulation layer, semiconductor layer, grid line, pixel electrode;
Described source electrode, drain electrode are positioned at the separator top, and by source electrode via hole, drain via in separator, with semiconductor layer, are electrically connected to respectively; Drain electrode also is electrically connected to pixel electrode by the first via hole in separator.
Array base palte of the present invention can be with above-mentioned method manufacture, so its manufacture method is simple, and efficiency is high; Simultaneously, its gate insulation layer does not exceed grid and grid line top, therefore its pixel electrode place does not have gate insulation layer, so gate insulation layer can not exert an influence to seeing through of light, and transmitance is high.
Preferably, described gate insulation layer is identical with the semiconductor layer figure, and only is positioned at the grid top.
Preferably, described grid, grid line also comprise the grid metal level be positioned on transparent conductive material layer.
Preferably, described semiconductor layer is made by metal oxide semiconductor material.
Preferably, described separator is any one in planarization layer, passivation layer, etching barrier layer.
Further preferably, described separator is planarization layer, and described separator is made by the photosensitive resin material.
Preferably, described source electrode, drain electrode are positioned on separator.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display unit, and it comprises above-mentioned array base palte.
Because display unit of the present invention comprises above-mentioned array base palte, so its preparation technology is simple, efficiency is high, transmitance is high.
Wherein, array base palte preparation method of the present invention, array base palte, display unit are preferably all for liquid crystal display, it is the LCD array substrate that its array base palte is preferably the TN type, display unit is preferably the liquid crystal indicator of TN type, but be to be understood that, the present invention also can be used for Organic Light Emitting Diode (OLED) display unit, and the pixel electrode in its array base palte can be equivalent to the male or female of Organic Light Emitting Diode.
The accompanying drawing explanation
The cross-sectional view that Fig. 1 is existing TN pattern array substrate;
The plan structure schematic diagram of the array base palte that Fig. 2 is embodiments of the invention 2 in preparation process;
The cross-sectional view along AA ' face that Fig. 3 is Fig. 2;
The plan structure schematic diagram of the array base palte that Fig. 4 is embodiments of the invention 2 in preparation process;
The cross-sectional view along AA ' face that Fig. 5 is Fig. 4;
The plan structure schematic diagram of the array base palte that Fig. 6 is embodiments of the invention 2 in preparation process;
The cross-sectional view along AA ' face that Fig. 7 is Fig. 6;
The plan structure schematic diagram of the array base palte that Fig. 8 is embodiments of the invention 2 in preparation process;
The cross-sectional view along AA ' face that Fig. 9 is Fig. 8;
The plan structure schematic diagram of the array base palte that Figure 10 is embodiments of the invention 2 in preparation process;
The cross-sectional view along AA ' face that Figure 11 is Figure 10;
The plan structure schematic diagram of the array base palte that Figure 12 is embodiments of the invention 2 in preparation process;
The cross-sectional view along AA ' face that Figure 13 is Figure 12;
The plan structure schematic diagram of the array base palte that Figure 14 is embodiments of the invention 2 in preparation process;
The cross-sectional view along AA ' face that Figure 15 is Figure 14;
The cross-sectional view of the array base palte that Figure 16 is embodiments of the invention 2 in preparation process;
The cross-sectional view of the array base palte that Figure 17 is embodiments of the invention 2 in preparation process;
The plan structure schematic diagram of the array base palte that Figure 18 is embodiments of the invention 2;
The cross-sectional view along AA ' face that Figure 19 is Figure 18;
Wherein Reference numeral is: 1, transparent conductive material layer; 11, pixel electrode; 2, grid metal level; 21, grid; 22, grid line; 3, insulation material layer; 31, gate insulation layer; 4, semiconductor material layer; 41, semiconductor layer; 5, planarization layer; 51, source electrode via hole; 52, drain via; 53, the first via hole; 7, metal level is leaked in source; 71, source electrode; 72, drain electrode; 8, photoresist layer; 9, substrate; Q1, gate location; Q2, grid line position; Q3, pixel electrode position; Q4, all the other positions; Q71, source electrode position; Q72, drain locations.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte preparation method, and it comprises:
Step 1: in substrate, by the composition technique of using the ladder exposure, form the figure that comprises grid line, grid, gate insulation layer, semiconductor layer, pixel electrode; Wherein, gate insulation layer does not exceed the top of grid line and grid;
Step 2: form separator in the substrate that completes abovementioned steps, form source electrode via hole and the drain via be connected with semiconductor layer and the first via hole be connected with pixel electrode in separator;
Step 3: in the substrate that completes abovementioned steps, by composition technique, form the figure that comprises source electrode, drain electrode; Wherein, source electrode, drain electrode are electrically connected to semiconductor layer by source electrode via hole, drain via respectively, and drain electrode is electrically connected to pixel electrode by the first via hole.
In the array base palte preparation method of the present embodiment, grid line/grid, gate insulation layer, semiconductor layer, pixel electrode form in a composition technique simultaneously, i.e. its needs single exposure (1Mask) technique, so its preparation technology is simple, efficiency is high; Simultaneously, because the gate insulation layer of its array base palte does not exceed grid and grid line top, therefore its pixel electrode place does not have gate insulation layer, so gate insulation layer can not exert an influence to seeing through of light, and transmitance is high.
Embodiment 2:
The present embodiment provides a kind of preparation method of array base palte, and as shown in Fig. 2 to Figure 19, it comprises the following steps:
S101, form successively transparent conductive material layer 1, insulation material layer 3, semiconductor material layer 4 in substrate 9, and on semiconductor material layer 4 coating photoresist layer 8.
Preferably, between transparent conductive material layer 1 and insulation material layer 3, also can form grid metal level 2.
Wherein, transparent conductive material layer 1 is that the material by transparent and electrically conductive forms, tin indium oxide (ITO) for example, and it is used to form pixel electrode 11, grid 21, grid line 22.
Obviously, owing to thering is transparent conductive material layer 1, therefore also can not form grid metal level 2 in theory, and directly with transparent conductive material layer 1, form grid 21, grid line 22.Do not form grid metal level 2 if should be appreciated that in this step, the operation of in subsequent step, " removing grid metal level 2 " is also no longer carried out accordingly.
Wherein, the known structure such as resilient coating also can be pre-formed in substrate 9; Each layer also can adopt other known materials; The method that forms each layer can be the known techniques such as sputter, evaporation, chemical vapour deposition (CVD), coating.Because the material of the above-mentioned various retes of formation, technique, parameter etc. are all known, therefore these contents all are not described in detail in the present embodiment.
S102, as shown in Figure 2 and Figure 3, photoresist layer 8 ladders are exposed and develop, the photoresist layer 8 that retains the first thickness at gate location Q1, grid line position Q2 retains the photoresist layer 8 of the second thickness, pixel electrode position Q3 retains the photoresist layer 8 of the 3rd thickness, all the other position Q4 are without photoetching glue-line 8, and wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness.
That is to say, by the diverse location to photoresist layer 8, carry out exposure in various degree, the photoresist layer 8 after making to develop is divided into three kinds of different thickness as shown in Figure 3, also has in addition subregion without photoetching glue-line 8.
Preferably, the ladder exposure can realize by gray scale mask plate or intermediate tone mask plate.
S103, remove semiconductor material layer 4, insulation material layer 3, grid metal level 2, transparent conductive material layer 1 without the photoresist zone, obtain structure as shown in Figure 4, Figure 5.
That is to say, by methods such as etchings, remove successively semiconductor material layer 4, insulation material layer 3, grid metal level 2, transparent conductive material layer 1 without photoresist zone Q4, thereby the transparent conductive material layer of pixel electrode area Q1 1 and other regional transparent conductive material layers 1 are separated.
Wherein, etching can adopt known method to carry out, and according to the difference of layers of material and etching technics, can be to remove a plurality of retes in an etching simultaneously, can be also that each etching is only removed a rete; Because etching technics, etching parameters etc. is all known, therefore these contents all are not described in detail in the present embodiment.
S104, remove the photoresist layer 8 of the 3rd thickness, the semiconductor material layer 4 of pixel electrode position Q3 is exposed, obtain structure as shown in Figure 6, Figure 7.
That is to say, remove the photoresist layer 8 of the 3rd thickness according to the thickness difference of photoresist layer 8 by ashing (Ashing) technique, the photoresist layer 8 of pixel electrode position Q3 is thoroughly removed like this, its semiconductor material layer 4 exposes, and the photoresist layer 8 of gate location Q1 and grid line position Q2 is corresponding attenuate, thereby obtain structure as shown in Figure 6, Figure 7.
Wherein, due to the characteristic of cineration technics, therefore the photoresist layer 8 area reality of gate location Q1 and grid line position Q2 also can dwindle a little, but because its structure to final products can not produce materially affect, therefore not shown.
S105, as shown in Figure 8, Figure 9, remove semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of pixel electrode position Q3, forms the figure of pixel electrode 11.
Now, because the photoresist layer 8 of pixel electrode position Q3 has been removed, therefore can remove successively semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of this position by etching technics, transparent conductive material layer 1 is exposed, form the figure of transparent pixels electrode 11.
S106, remove the photoresist layer 8 that thickness equals grid line position Q2 remaining photoresist layer 8 thickness, the semiconductor layer 41 of grid line position Q2 is exposed, obtain structure as shown in Figure 10, Figure 11.
That is to say, remove the remaining photoresist layer 8 of grid line position Q2 (its thickness can equal the second thickness and deduct the 3rd thickness) by cineration technics, the semiconductor layer 41 at this place is exposed, simultaneously, the photoresist layer 8 of gate location Q1 continues attenuate, thereby obtains structure as shown in Figure 10, Figure 11.
S107, remove the semiconductor material layer 4 of grid line position Q2, and preferably remove the insulation material layer 3 of this position simultaneously, form the figure of grid line 22, obtain structure as shown in Figure 12 and Figure 13.
That is to say, remove semiconductor material layer 4, the insulation material layer 3 of grid line position Q2 by etching technics, grid metal level 2 is exposed, form the figure of grid line 22.
Wherein, in this step, the insulation material layer 3 of grid line position Q2 has also been removed together, thereby in final products, grid line 22 tops do not have gate insulation layer 31, the graphs coincide of gate insulation layer 31 and semiconductor layer 41, and all only be positioned at grid 21 tops; The advantage of this technique is, can select certain corrosive agent directly once semiconductor material layer 4 and insulation material layer 3 to be removed, thereby simplifies technique.
But, should be appreciated that if in this step, only remove the semiconductor material layer 4 of grid line position Q2, and retain insulation material layer 3, be also feasible; Like this, in final products, still have gate insulation layer 31 (but semiconductor layer 41 only is positioned at grid 21 tops) above grid line 22, this gate insulation layer 31 can increase grid line 22 and data wire spacing, thereby reduces the coupling capacitance of the two.
Wherein, the present embodiment is what to have the situation of grid metal level 2 be example, and its grid line 22 consists of jointly grid metal level 2 and transparent conductive material layer 1, thereby improves the electric conductivity of grid line 22; But should be appreciated that now grid line position Q2 only remains transparent conductive material layer 1 if do not form grid metal level 2 in step S101, grid line 22 also can directly consist of transparent conductive material.
S108, as shown in Figure 14, Figure 15, remove whole remaining photoresist layers 8, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
That is to say, peel off whole remaining photoresist layers 8 (being the photoresist layer 8 of gate location Q1), semiconductor layer 41 is exposed, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
Visible, in the present embodiment, only by single exposure, just prepared the figure of grid line 22/ grid 21, gate insulation layer 31, semiconductor layer 41, pixel electrode 11 simultaneously, therefore its exposure frequency obviously reduces, the preparation method is simple, efficiency is high.
Simultaneously, in the array base palte of the present embodiment, gate insulation layer 31 does not exceed the top of grid 21 and grid line 22, and its pixel electrode 11 places do not have gate insulation layer 31, so gate insulation layer 31 can not exert an influence to seeing through of light, and transmitance is high.
S109, as shown in figure 16, form separator, and form source electrode via hole 51 and the drain via 52 be connected with semiconductor layer 41 in separator, and the first via hole 53 be connected with pixel electrode.
Preferably, described separator can be planarization layer 5, planarization layer 5 is made by materials such as resins usually, it is except buffer action, the section poor " filling and leading up " that also structures such as thin-film transistor can be caused, make to be tending towards smooth on the surface integral of array base palte, so that follow-up alignment films even film layer forms, and be beneficial to the even friction of friction orientation technique.
Certainly, if separator is not planarization layer 5, it also can be the etching barrier layer for preventing that semiconductor layer 41 is etched, or is other structures such as passivation layer for insulation; Etching barrier layer, passivation layer etc. mainly consist of inorganic material such as silicon nitride, silica, and their Thickness Ratio planarization layer 5 is thin, therefore it is poor usually not work to eliminate section, and only for by source electrode 71, draining 72 etc. separates with other structures.
Concrete, each above-mentioned via hole can form by composition technique, can on planarization layer 5, be coated with photoresist, is exposed successively afterwards, development, etching, photoresist lift off etc.
Be generally the materials such as resin due to planarization layer 5, and the semiconductor layer 41, pixel electrode 11 of its below etc. are the inorganic material such as semiconductor, conductor, the etching selection gender gap of the two is very large, although therefore the hole depth difference excessively of diverse location can not produce the destruction to semiconductor layer 41, pixel electrode 11 etc. yet during etching.
But preferred, can be also that planarization layer 5 itself is just made by the photosensitive resin material, now can not be coated with photoresist, but directly planarization layer 5 be exposed, develops, thereby form via hole therein.
In a word, the method that forms via hole in planarization layer 5 is known, at this, is not described in detail.
Metal level 7 is leaked in S110, formation source.
Source is leaked metal level 7 and is made by the conducting metal such as molybdenum, aluminium or alloy, is used to form source electrode 71 and drain electrode 72.
Wherein, owing on planarization layer 5, having via hole, Gu Yuan leaks metal level 7 natures and can be connected with semiconductor layer 41 with drain via 52 by source electrode via hole 51, and is connected with pixel electrode 11 by the first via hole 53.
S111, formation photoresist layer 8 exposure, retain photoresist layer 8 at separated source electrode position Q71 and drain locations Q72, and all the other positions are without photoetching glue-line 8; Wherein, source electrode position Q71 comprises source electrode via hole 51, and drain locations Q72 comprises drain via 52 and the first via hole 53; Obtain the structure as shown in Figure 17,18.
That is to say, only finally will forming source electrode 71,72 the position of draining retains photoresist layer 8, and the photoresist layer of all the other positions 8 is removed, wherein source electrode position Q71 and drain locations Q72 are separated from each other, and source electrode position Q71 is contained source electrode via hole 51, drain locations Q72 is contained drain via 52 and the first via hole 53.
Typically, because data wire need to be connected with source electrode 71, and public electrode wire is parallel and non-intersect with data wire, therefore, preferably can make data wire and public electrode wire and source electrode 71, drain and 72 synchronize formation; When removing photoresist layer 8, also retain the linear position data photoresist layer 8 of (Q72 is connected with the source electrode position), and the photoresist layer 8 of public electrode line position (independent position), thereby form data wire and public electrode wire in follow-up etch step simultaneously.
Of course it is to be understood that data wire and/or public electrode wire also can form by independent composition technique in subsequent step, do not limit at this.
S112, remove the source covered without photoresist and leak metal level 7, then remove remaining photoresist layer 8, form data wire, public electrode wire (not shown), source electrode 71 and 72 the figure of draining, obtain structure as shown in figure 19.
That is to say, the source leakage metal level 7 that etching is removed exposure, leak metal levels 7 thereby remain two sources that separate, and wherein one is electrically connected to semiconductor layer 41, is source electrode 71, and another piece links together semiconductor layer 41 and pixel electrode 11, for draining 72.
Certainly, if also retained the photoresist layer 8 of linear position data and public electrode line position in the S111 step, in this step, can form data wire and public electrode wire simultaneously.
S113, continuation form the structures such as alignment film (not shown), complete the preparation of array base palte.
Embodiment 3:
As shown in Fig. 2 to 19, the present embodiment provides a kind of array base palte, and it comprises grid 21, grid line 22, gate insulation layer 31, semiconductor layer 41, pixel electrode 11, source electrode 71, drain 72, separator.
As shown in figure 19, in the array base palte of the present embodiment, grid 21, grid line 22 comprise transparent conductive material layer 1.
That is to say, the grid 21 of the array base palte of the present embodiment, grid line 22 can consist of the material of pixel electrode 11, therefore they can synchronize with pixel electrode 11 formation, thereby simplify preparation technology.
Preferably, grid 21, grid line 22 also comprise the grid metal level 2 be positioned on transparent conductive material layer 1, and grid 21, grid line 22 can jointly be comprised of transparent conductive material layer 1 and grid metal level 2, thereby strengthen its electric conductivity.
Certainly, can there is no grid metal level 2 in theory yet, and directly with transparent conductive material layer 1, form grid 21, grid line 22.
Wherein, gate insulation layer 31 does not exceed on grid 21 and grid line 22; Therefore, its pixel electrode 11 places do not have gate insulation layer 31, and transmitance is high.
Preferably, gate insulation layer 31 is identical with semiconductor layer 41 figures, and only is positioned at grid 21 tops.
Because gate insulation layer 31 is identical with semiconductor layer 41 figures, therefore they can form in an etching simultaneously, preparation efficiency is high.
Certainly, gate insulation layer 31 also can be different from semiconductor layer 41 figures, and distribution (41 of semiconductor layers are positioned at grid 21 tops) is also arranged above grid line 22, can increase the distance between grid line 22 and data wire like this, reduce the coupling capacitance of the two.
Preferably, semiconductor layer 41 is made by metal oxide semiconductor material.
Wherein, separator cover gate 21, gate insulation layer 31, semiconductor layer 41, grid line 22, pixel electrode 11.
Preferably, separator is planarization layer 5, and it is except isolating, the section poor " filling and leading up " that also can be used for thin-film transistor etc. is caused, make to be tending towards smooth on the surface integral of array base palte, so that follow-up alignment films even film layer forms, and be beneficial to the even friction of friction orientation technique.
Preferably, above-mentioned planarization layer 5 is made by the photosensitive resin material, thereby while forming via hole thereon, needn't make to wait with photoresist, and technique is simple.
Preferably, separator also can be the etching barrier layer for preventing that semiconductor layer 41 is etched, or is other structures such as passivation layer for insulation; Etching barrier layer, passivation layer etc. mainly consist of inorganic material such as silicon nitride, silica, and their Thickness Ratio planarization layer 5 is thin, therefore it is poor usually not work to eliminate section, and only for by source electrode 71, draining 72 etc. separates with other structures.
Certainly, in the array base palte of the present embodiment, also should there are other known structure such as data wire, public electrode wire, alignment film (not shown), these structures can be arranged on relevant position as required, as long as finally can realize that data wire is electrically connected to source electrode, public electrode wire is electrically connected to and gets final product with public electrode on color membrane substrates, and the present embodiment is not described in detail it.
Embodiment 4:
The present embodiment provides a kind of display unit, and it comprises above-mentioned array base palte.
Because the display unit of the present embodiment comprises above-mentioned array base palte, so its preparation technology is simple, efficiency is high, transmitance is high.
The display unit of the present embodiment can be: any product or parts with Presentation Function such as display panels, OLED display floater, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Be understandable that, above execution mode is only the illustrative embodiments adopted for principle of the present invention is described, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement also are considered as protection scope of the present invention.
Claims (17)
1. an array base palte preparation method, is characterized in that, comprising:
Step 1: in substrate, by the composition technique of using the ladder exposure, form the figure that comprises grid line, grid, gate insulation layer, semiconductor layer, pixel electrode; Wherein, gate insulation layer does not exceed the top of grid line and grid;
Step 2: form separator in the substrate that completes abovementioned steps, form source electrode via hole and the drain via be connected with semiconductor layer and the first via hole be connected with pixel electrode in separator;
Step 3: in the substrate that completes abovementioned steps, by composition technique, form the figure that comprises source electrode, drain electrode; Wherein, source electrode, drain electrode are electrically connected to semiconductor layer by source electrode via hole, drain via respectively, and drain electrode is electrically connected to pixel electrode by the first via hole.
2. array base palte preparation method according to claim 1, is characterized in that, described step 1 specifically comprises:
Step 11, form successively transparent conductive material layer, insulation material layer, semiconductor material layer, photoresist layer in substrate;
Step 12, the photoresist layer ladder is exposed and develops, make gate location retain the photoresist layer of the first thickness, the grid line position retains the photoresist layer of the second thickness, the pixel electrode position retains the photoresist layer of the 3rd thickness, all the other positions are without the photoetching glue-line, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness;
Step 13, remove semiconductor material layer, insulation material layer, transparent conductive material layer without the photoresist zone;
Step 14, remove the photoresist layer of the 3rd thickness, the semiconductor material layer of pixel electrode position is exposed;
Step 15, the semiconductor material layer of removing the pixel electrode position, insulation material layer, the figure of formation pixel electrode;
Step 16, remove the photoresist layer that thickness equals grid line position remaining photoresist layer thickness, the semiconductor layer of grid line position is exposed;
Step 17, remove the semiconductor material layer of grid line position, form the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
3. array base palte preparation method according to claim 2, is characterized in that, described step 17 specifically comprises:
Remove the semiconductor material layer of grid line position, and remove the insulation material layer of grid line position, form the figure of grid line.
4. array base palte preparation method according to claim 2, is characterized in that,
Described step 11 also comprises: at transparent conductive material layer and insulating material interlayer, form the grid metal level;
Described step 13 also comprises: remove the grid metal level without the photoresist zone;
Described step 15 also comprises: the grid metal level of removing the pixel electrode position.
5. array base palte preparation method according to claim 2, is characterized in that,
Described ladder exposure realizes by gray scale mask plate or intermediate tone mask plate.
6. array base palte preparation method according to claim 1, is characterized in that,
Described separator is any one in planarization layer, passivation layer, etching barrier layer.
7. array base palte preparation method according to claim 6, is characterized in that,
Described separator is planarization layer, and is made by the photosensitive resin material.
8. array base palte preparation method according to claim 1, is characterized in that,
Described semiconductor layer is made by metal oxide semiconductor material.
9. according to the described array base palte preparation method of any one in claim 1 to 8, it is characterized in that, described step 3 specifically comprises:
Metal level is leaked in step 31, formation source;
Step 32, formation photoresist layer exposure, retain photoresist layer in separated source electrode position and drain locations, and all the other positions are without the photoetching glue-line; Wherein, the source electrode position comprises the source electrode via hole, and drain locations comprises drain via and the first via hole;
Step 33, remove without the source in photoetching glue-line zone and leak metal level, then remove photoresist layer, form the figure of source electrode and drain electrode.
10. an array base palte, it comprises grid, grid line, gate insulation layer, semiconductor layer, pixel electrode, separator, source electrode, drain electrode, it is characterized in that,
Described grid, grid line comprise transparent conductive material layer;
Described gate insulation layer does not exceed the top of grid line and grid;
Described separator cover gate, gate insulation layer, semiconductor layer, grid line, pixel electrode;
Described source electrode, drain electrode are positioned at the separator top, and by source electrode via hole, drain via in separator, with semiconductor layer, are electrically connected to respectively; Drain electrode also is electrically connected to pixel electrode by the first via hole in separator.
11. array base palte according to claim 10, is characterized in that,
Described gate insulation layer is identical with the semiconductor layer figure, and only is positioned at the grid top.
12. array base palte according to claim 10, is characterized in that,
Described grid, grid line also comprise the grid metal level be positioned on transparent conductive material layer.
13. array base palte according to claim 10, is characterized in that,
Described semiconductor layer is made by metal oxide semiconductor material.
14. array base palte according to claim 10, is characterized in that,
Described separator is any one in planarization layer, passivation layer, etching barrier layer.
15. array base palte according to claim 14, is characterized in that,
Described separator is planarization layer, and described separator is made by the photosensitive resin material.
16. array base palte according to claim 10, is characterized in that,
Described source electrode, drain electrode are positioned on separator.
17. a display unit, is characterized in that, comprising:
Array base palte as described as any one in claim 10 to 16.
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