CN103700397A - Static random access memory (SRAM) storage unit, writing operation method of SRAM storage unit and SRAM memory - Google Patents
Static random access memory (SRAM) storage unit, writing operation method of SRAM storage unit and SRAM memory Download PDFInfo
- Publication number
- CN103700397A CN103700397A CN201310674701.9A CN201310674701A CN103700397A CN 103700397 A CN103700397 A CN 103700397A CN 201310674701 A CN201310674701 A CN 201310674701A CN 103700397 A CN103700397 A CN 103700397A
- Authority
- CN
- China
- Prior art keywords
- storage unit
- sram
- data latches
- sram storage
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Static Random-Access Memory (AREA)
Abstract
The invention discloses a static random access memory (SRAM), a writing operation method of the SRAM storage unit and an SRAM memory. The SRAM storage unit comprises a data latch, a selection controller, a first transmission tube and a second transmission tube, wherein the selection controller is connected with a power supply of the data latch and used for controlling a power supply of the data latch to be connected with power supply voltage or connected with ground level. The writing operation method comprises the following step: clearing the SRAM storage unit before carrying out a writing operation on the SRAM storage unit, so that a first storage node and a second storage node are discharged to the ground level. By adopting the writing operation method of the SRAM storage unit, the reliability of the writing operation of the SRAM storage unit can be improved, and the instantaneous power consumption in the writing operation is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of SRAM storage unit, a kind of SRAM memory cell write-operation method and a kind of SRAM storer.
Background technology
Semiconductor memory is different according to the mode of storage data, can be divided into the large class of random-access memory (ram) and ROM (read-only memory) (ROM) two.Random-access memory (ram) can be divided into again static RAM (SRAM) and dynamic RAM (DRAM).Compare with DRAM, SRAM has read or write speed faster.And SRAM do not need periodic refresh canned data, its Design and manufacture is relatively simple.
Storage unit is the most basic, most important ingredient in SRAM storer, has occupied the major part of whole SRAM memory area.The stability of storage unit has determined the data reliability of storer.
The SRAM storage unit of main flow is six transistor units (6T).As shown in Figure 1, described 6T storage unit has symmetry, 6 metal-oxide-semiconductors, consists of.Wherein metal-oxide-semiconductor M1～M4 forms two cross-linked phase inverters, is used for latch stores node
signal.Metal-oxide-semiconductor M5, M6 are transfer tubes, and they play the effect that described storage unit is connected or is disconnected with bit line when SRAM storer is carried out to read/write operation.
Described SRAM storage unit one has 3 states, is respectively: reading and writing and data keep.
During read data, bit line
first be charged to high level, then word line WL be charged to high level, make transfer tube M5/M6 conducting, memory node bit/bit_ is to bit line
electric discharge, makes a bit-line voltage decline Δ V and another bit line keeps high level constant, and sense amplifier amplifies this voltage difference delta V is read out data.
While writing data, the data that first basis will be write are by a certain bit line preliminary filling to high level, and another root bit line discharges is to ground level simultaneously.Then make word line WL charge to high level, conducting transfer tube M5/M6, bit line discharges and recharges to memory node bit/bit_.At this moment to guarantee that charge/discharge current is greater than the lower/upper path current that draws, make the voltage of memory node bit/bit_ be enough to make the degree of phase inverter reversion, otherwise be exactly write (the fail write) of once failure.
In prior art, by the size design of each metal-oxide-semiconductor, make each metal-oxide-semiconductor exist certain strong or weak relation to write to guarantee the success of data.Once and each metal-oxide-semiconductor charging and discharging capabilities power changes, data still may write error.
Summary of the invention
Technical matters to be solved by this invention is how to improve the reliability of SRAM memory cell write-operation.
In order to address the above problem, the invention provides a kind of SRAM storage unit, comprising:
Data latches, described data latches comprises the first memory node and the second memory node;
Selection control, described selection control is connected with the power supply of described data latches, for controlling the power supply of described data latches, is connected or is connected with ground level with supply voltage;
The first transfer tube, described the first transfer tube is between the first bit line and described the first memory node;
The second transfer tube, described the second transfer tube is between the second bit line and described the second memory node;
The grid of the grid of described the first transfer tube and described the second transfer tube is all connected with word line.
Alternatively, described selection control is controlled by the write control signal of described SRAM storage unit, and the power supply of described data latches is connected with ground level before described write control signal is effective, when write control signal is effective, is connected with supply voltage.
Alternatively, described selection control is controlled by reseting controling signal; Described reseting controling signal is effective, and described selection control makes the power supply of described data latches be connected with ground level, and described reseting controling signal is invalid, and described selection control makes the power supply of described data latches be connected with supply voltage.
Alternatively, described SRAM storage unit is standard 6T storage unit;
Described data latches comprises: the first phase inverter and the second phase inverter, described the first phase inverter and described the second phase inverter cross-coupled;
Described the first phase inverter comprises: a PMOS transistor and the first nmos pass transistor;
Described the second phase inverter comprises: the 2nd PMOS transistor and the second nmos pass transistor;
The power supply of described data latches comprises: the transistorized source electrode of a described PMOS and the transistorized source electrode of described the 2nd PMOS.
The present invention also provides a kind of SRAM memory cell write-operation method, is applicable to above-mentioned SRAM storage unit, comprising:
Before described SRAM storage unit is carried out to write operation, to the zero clearing of described SRAM storage unit, make described the first memory node and described the second memory node be discharged to ground level.
It is alternatively, described that to described SRAM storage unit, zero clearing comprises:
Described the first bit line is connected with ground level with described the second bit line;
The power supply of described data latches is connected with ground level;
Described word line is connected with supply voltage.
Alternatively, describedly described SRAM storage unit carried out to write operation comprise:
The power supply of described data latches is connected with supply voltage;
Described the first bit line and described the second bit line are written into data to be written.
Alternatively, described zero clearing at least continues 3ns.
The present invention also provides a kind of SRAM storer, comprising: above-mentioned SRAM storage unit.
Compared with prior art, technical scheme of the present invention has the following advantages:
The present invention is before writing SRAM storage unit, first remove former deposit data, the voltage of two memory nodes of SRAM storage unit is all dropped to ground level, the data that while making write operation, bit line is sent into can not exist to discharge and recharge with the data of former memory node conflicts, and then the instantaneous power consumption while reducing write operation, improve the yield of SRAM storer integral body.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation of SRAM storage unit of prior art;
Fig. 2 is the structural representation of SRAM storage unit one embodiment of the present invention;
Fig. 3 is the schematic flow sheet of SRAM memory cell write-operation method of the present invention one embodiment;
Fig. 4 is the sequential chart of SRAM memory cell write-operation method of the present invention one embodiment.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, so the present invention is not subject to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the present invention is described in detail in detail, for ease of explanation, described schematic diagram is example, and it should not limit the scope of protection of the invention at this.
Inventor analyzes and researches to writing the situation of failure, finds: why writing failure, is because may there is the conflict that discharges and recharges of each pipe in ablation process.
During due to write operation, two bit lines are always one high and one low.And previous write operation makes the voltage of two memory nodes in SRAM storage unit also keep one high and one low.When the bit line of high level discharges to low level memory node, the NMOS in transfer tube and data latches manages and forms a path, and bit-line voltage is dragged down, and low level storage node voltage raises but be not enough so that another NMOS manages unlatching.When low level bit line is charged by high level memory node, PMOS pipe and transfer tube form a path, and high level storage node voltage drops to while making another PMOS pipe conducting, and latch stores state switches, and has write.In this process,, there is quiescent current in the conducting simultaneously of PMOS, NMOS pipe for some time.And strictly, just can make each pipe by correct current trend successively conducting to strong and weak requirement of 6 pipe abilities, otherwise will write error.
Therefore, inventor provides a kind of new wiring method, can effectively avoid the conflict that discharges and recharges in ablation process, improves and writes reliability.
In order to solve the technical matters in background technology, the invention provides a kind of SRAM storage unit.Fig. 2 is the structural representation of SRAM storage unit one embodiment of the present invention.As shown in Figure 2, the present embodiment is a standard 6T storage unit, comprising: the data latches consisting of a PMOS pipe M3, a NMOS pipe M1, the 2nd PMOS pipe M4 and the 2nd NMOS pipe M2 cross-coupled; The first transfer tube M5; The second transfer tube M6 and selection control S.
A described PMOS pipe M3 and a described NMOS pipe M1 form the first phase inverter.Described the 2nd PMOS pipe M4 and described the 2nd NMOS pipe M2 form the second phase inverter.
The first memory node bit, between the drain electrode of a described PMOS pipe M3 and the drain electrode of a described NMOS pipe M1, is coupled between the grid of described the 2nd PMOS pipe M4 and the grid of described the 2nd NMOS pipe M2 simultaneously.
The second memory node bit_, between the drain electrode of described the 2nd PMOS pipe M4 and the drain electrode of described the 2nd NMOS pipe M2, is coupled between the grid of a described PMOS pipe M3 and the grid of a described NMOS pipe M1 simultaneously.
Described the first transfer tube M5 is between described the first memory node bit and the first bit line BL.
Described the second transfer tube M6 is positioned at described the second memory node bit_ and the second bit line
between.
The grid M6 of the grid of described the first transfer tube M5 and described the second transfer tube is all connected with word line WL.
The power supply latch(of described data latches is the source electrode of a described PMOS pipe M3 and the source electrode of described the 2nd PMOS pipe M4) be connected described selection control S.
Described selection control S controls power supply latch access supply voltage VDD or the access ground level of described data latches.
In the present embodiment, described selection control S is controlled by reseting controling signal RST.When described reseting controling signal RST is effective, start the former deposit data of zero clearing.Particularly, described the first bit line BL and described the second bit line
be admitted to ground level, described selection control S is connected the power supply latch of described data latches with ground level, and described word line WL is admitted to supply voltage VDD.When described reseting controling signal RST is invalid, described selection control S is connected the power supply latch of described data latches with supply voltage VDD, and new data can be write.It will be appreciated by those skilled in the art that, the SRAM storage unit of the present embodiment is before write operation, increased the step of the former deposit data of zero clearing, so, in other embodiments, described selection control S also can be controlled by the write control signal (not shown) of described SRAM storage unit, and the power supply latch of described data latches is connected with ground level before described write control signal is effective, when write control signal is effective, is connected with supply voltage VDD.
The SRAM storage unit of the present embodiment can be before write operation, the former deposit data of zero clearing, and then effectively avoid in ablation process the conflict that discharges and recharges between each pipe.
It should be noted that, although it will be understood by those skilled in the art that the SRAM storage unit of the present embodiment is standard 6T unit, should not be construed as the restriction to SRAM storage unit.In other embodiments, the SRAM storage unit of other types, such as: 4T, 8T etc., all applicable the present invention.
Correspondingly, the present invention also provides a kind of SRAM memory cell write-operation method.Fig. 3 is the schematic flow sheet of SRAM memory cell write-operation method of the present invention one embodiment.As shown in Figure 3, the present embodiment comprises the following steps:
Particularly, can be first by described the first bit line BL and described the second bit line
be connected with ground level.Again the power supply latch of described data latches is connected with ground level, makes the voltage of described the first memory node and the voltage continuous decrease of described the second memory node.Finally described word line WL is connected with supply voltage VDD, with the first transfer tube M5 described in conducting and described the second transfer tube M6.After conducting, the ground level of described the first bit line BL and described the second bit line
ground level will write respectively described the first memory node and described the second memory node.
Particularly, described zero clearing at least continues 3ns, and to guarantee that the voltage of described the first memory node and the voltage of described the second memory node has been down to ground level, former deposit data is cleared.
Perform step afterwards 102, SRAM storage unit is carried out to write operation.
Particularly, the power supply latch of described data latches can be connected with supply voltage VDD.Then, described the first bit line BL and described the second bit line are written into data to be written, start write operation.
The present embodiment before write operation first by former deposit data zero clearing, in write operation process after zero clearing, there will not be and discharge and recharge conflict, reduced and write fashionable instantaneous power consumption, improved the reliability that writes SRAM storage unit, and then improved the yield of SRAM storer integral body.
Fig. 4 is the sequential chart of SRAM memory cell write-operation method of the present invention one embodiment.Below in conjunction with Fig. 4, the course of work embodiment illustrated in fig. 2 is described.
Before SRAM storage unit shown in Fig. 2 is carried out to write operation, first to the zero clearing of described SRAM storage unit.
In the zero clearing stage of Fig. 4 dotted line a in SRAM storage unit, described zero clearing comprises: by described the first bit line BL and described the second bit line
(not shown) is connected with ground level.By power supply latch earth level (the being V(latch) waveform of data latches).Word line WL is connect to high level (being V(WL) waveform).
Visible in figure, the voltage of the first memory node bit and the second memory node bit_ is down to rapidly ground level (being V(bit) waveform and V(bit_) waveform), former deposit data is cleared.
Afterwards, the state that the voltage of the first memory node bit and the second memory node bit_ is ground level has kept one end after the time, enters the write phase of SRAM file unit.By the power supply latch access high level of data latches, by word line WL access high level, the first bit line BL and the second bit line
according to the data that write, input respectively one high and one low two voltage (not shown).The data that finally, write are stored with one high and one low voltage form at the first memory node bit and the second memory node bit_.After Fig. 4 dotted line b place shows and has write, the voltage of the first memory node bit and the second memory node bit_.As shown in the figure, the voltage of the first memory node bit is low, and the voltage of the second memory node bit_ is high.
The present invention also provides a kind of SRAM storer (not shown), comprising: above-mentioned SRAM storage unit.
It should be noted that, the present invention can be used in numerous general or special purpose computingasystem environment or configuration.Such as: personal computer, server computer, handheld device or portable set, plate equipment, multicomputer system, system, set top box, programmable consumer-elcetronics devices, network PC, small-size computer, mainframe computer based on microprocessor, comprise the distributed computing environment of above any system or equipment etc.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (9)
1. a SRAM storage unit, is characterized in that, comprising:
Data latches, described data latches comprises the first memory node and the second memory node;
Selection control, described selection control is connected with the power supply of described data latches, for controlling the power supply of described data latches, is connected or is connected with ground level with supply voltage;
The first transfer tube, described the first transfer tube is between the first bit line and described the first memory node;
The second transfer tube, described the second transfer tube is between the second bit line and described the second memory node;
The grid of the grid of described the first transfer tube and described the second transfer tube is all connected with word line.
2. SRAM storage unit according to claim 1, it is characterized in that, described selection control is controlled by the write control signal of described SRAM storage unit, the power supply of described data latches is connected with ground level before described write control signal is effective, when write control signal is effective, is connected with supply voltage.
3. SRAM storage unit according to claim 1, is characterized in that, described selection control is controlled by reseting controling signal; Described reseting controling signal is effective, and described selection control makes the power supply of described data latches be connected with ground level, and described reseting controling signal is invalid, and described selection control makes the power supply of described data latches be connected with supply voltage.
4. SRAM storage unit according to claim 1, is characterized in that, described SRAM storage unit is standard 6T storage unit;
Described data latches comprises: the first phase inverter and the second phase inverter, described the first phase inverter and described the second phase inverter cross-coupled;
Described the first phase inverter comprises: a PMOS transistor and the first nmos pass transistor;
Described the second phase inverter comprises: the 2nd PMOS transistor and the second nmos pass transistor;
The power supply of described data latches comprises: the transistorized source electrode of a described PMOS and the transistorized source electrode of described the 2nd PMOS.
5. a SRAM memory cell write-operation method, is applicable to the SRAM storage unit described in arbitrary claim in claim 1～4, it is characterized in that, comprising:
Before described SRAM storage unit is carried out to write operation, to the zero clearing of described SRAM storage unit, make described the first memory node and described the second memory node be discharged to ground level.
6. SRAM memory cell write-operation method according to claim 5, is characterized in that, described to described SRAM storage unit, zero clearing comprises:
Described the first bit line is connected with ground level with described the second bit line;
The power supply of described data latches is connected with ground level;
Described word line is connected with supply voltage.
7. SRAM memory cell write-operation method according to claim 5, is characterized in that, describedly described SRAM storage unit is carried out to write operation comprises:
The power supply of described data latches is connected with supply voltage;
Described the first bit line and described the second bit line are written into data to be written.
8. SRAM memory cell write-operation method according to claim 5, is characterized in that, described zero clearing at least continues 3ns.
9. a SRAM storer, is characterized in that, comprising: the SRAM storage unit in claim 1～4 described in arbitrary claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310674701.9A CN103700397B (en) | 2013-12-11 | 2013-12-11 | SRAM memory cell, SRAM memory cell write operation method and SRAM memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310674701.9A CN103700397B (en) | 2013-12-11 | 2013-12-11 | SRAM memory cell, SRAM memory cell write operation method and SRAM memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103700397A true CN103700397A (en) | 2014-04-02 |
| CN103700397B CN103700397B (en) | 2017-11-10 |
Family
ID=50361897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310674701.9A Active CN103700397B (en) | 2013-12-11 | 2013-12-11 | SRAM memory cell, SRAM memory cell write operation method and SRAM memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103700397B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971733A (en) * | 2014-05-08 | 2014-08-06 | 苏州无离信息技术有限公司 | Low power consumption SRAM (Static Random Access Memory) unit circuit structure |
| CN107369466A (en) * | 2017-06-19 | 2017-11-21 | 宁波大学 | A kind of three wordline memory cell based on FinFET |
| CN107681768A (en) * | 2017-11-01 | 2018-02-09 | 浙江工业大学 | A kind of high power selection circuit being easily integrated |
| CN110718255A (en) * | 2018-07-13 | 2020-01-21 | 合肥格易集成电路有限公司 | Nonvolatile memory processing method and device |
| CN111243638A (en) * | 2019-12-24 | 2020-06-05 | 格科微电子（上海）有限公司 | Method for implementing high-performance state memory unit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030231538A1 (en) * | 2001-12-28 | 2003-12-18 | Stmicroelectronics S.R.I. | Static ram with flash-clear function |
| US20040179406A1 (en) * | 2003-02-25 | 2004-09-16 | Keiichi Kushida | Semiconductor memory device |
| CN101615424A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | 8 t low leakage sram cell |
| CN102376351A (en) * | 2010-08-04 | 2012-03-14 | 飞思卡尔半导体公司 | Memory with low voltage mode operation |
-
2013
- 2013-12-11 CN CN201310674701.9A patent/CN103700397B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030231538A1 (en) * | 2001-12-28 | 2003-12-18 | Stmicroelectronics S.R.I. | Static ram with flash-clear function |
| US20040179406A1 (en) * | 2003-02-25 | 2004-09-16 | Keiichi Kushida | Semiconductor memory device |
| CN101615424A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | 8 t low leakage sram cell |
| CN102376351A (en) * | 2010-08-04 | 2012-03-14 | 飞思卡尔半导体公司 | Memory with low voltage mode operation |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971733A (en) * | 2014-05-08 | 2014-08-06 | 苏州无离信息技术有限公司 | Low power consumption SRAM (Static Random Access Memory) unit circuit structure |
| CN103971733B (en) * | 2014-05-08 | 2017-04-05 | 苏州无离信息技术有限公司 | Low-power consumption SRAM element circuit structure |
| CN107369466A (en) * | 2017-06-19 | 2017-11-21 | 宁波大学 | A kind of three wordline memory cell based on FinFET |
| CN107369466B (en) * | 2017-06-19 | 2019-09-10 | 宁波大学 | A kind of three wordline storage units based on FinFET |
| CN107681768A (en) * | 2017-11-01 | 2018-02-09 | 浙江工业大学 | A kind of high power selection circuit being easily integrated |
| CN110718255A (en) * | 2018-07-13 | 2020-01-21 | 合肥格易集成电路有限公司 | Nonvolatile memory processing method and device |
| CN110718255B (en) * | 2018-07-13 | 2022-03-29 | 合肥格易集成电路有限公司 | Nonvolatile memory processing method and device |
| CN111243638A (en) * | 2019-12-24 | 2020-06-05 | 格科微电子（上海）有限公司 | Method for implementing high-performance state memory unit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103700397B (en) | 2017-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10672461B2 (en) | Write assist negative bit line voltage generator for SRAM array | |
| CN105679359B (en) | Semiconductor memory device with a plurality of memory cells | |
| US9355710B2 (en) | Hybrid approach to write assist for memory array | |
| CN109448768B (en) | Sensitive amplifier circuit with ultralow offset | |
| CN103700397A (en) | Static random access memory (SRAM) storage unit, writing operation method of SRAM storage unit and SRAM memory | |
| JP2021168225A (en) | Data caching | |
| CN102834869B (en) | Semiconductor storage | |
| CN103943141A (en) | System and method for performing address-based SRAM access assists | |
| CN108028062A (en) | Adaptively negative bit line write-in auxiliary | |
| TW201511002A (en) | Ternary content addressable memory | |
| CN102034533B (en) | Static random storage unit with resetting function | |
| CN103956184A (en) | Improved SRAM (Static Random Access Memory) memory cell based on DICE (Dual Interlocked Storage Cell) structure | |
| CN209168744U (en) | A kind of sensitive amplifier circuit with Low-offset | |
| CN110176264A (en) | A kind of high-low-position consolidation circuit structure calculated interior based on memory | |
| CN104157303A (en) | Anti-interference circuit and storage element of static random access memory unit | |
| US11450359B1 (en) | Memory write methods and circuits | |
| CN203276858U (en) | SRAM (Static Random Access Memory) | |
| CN104157304A (en) | Anti-jamming storage element | |
| WO2006121491A3 (en) | Method and apparatus for low voltage write in a static random access memory | |
| CN104409094B (en) | The transistor memory unit of subthreshold value 6 | |
| US10818335B2 (en) | Memory storage apparatus and operating method with multiple modes for refresh operation | |
| CN213519272U (en) | Reading circuit of memory | |
| CN114999545A (en) | NRHC-14T radiation-resistant SRAM memory cell, chip and module | |
| CN105336360B (en) | The control circuit and SRAM memory of SRAM storage arrays | |
| CN206505723U (en) | STT-MTJ (spin-transfer torque-magnetic tunnel junction) -based MRAM (magnetic random Access memory) unit control circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |