CN110718255B

CN110718255B - Nonvolatile memory processing method and device

Info

Publication number: CN110718255B
Application number: CN201810772569.8A
Authority: CN
Inventors: 李琪; 林子曾
Original assignee: GigaDevice Semiconductor Beijing Inc; Hefei Geyi Integrated Circuit Co Ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd; Hefei Geyi Integrated Circuit Co Ltd
Priority date: 2018-07-13
Filing date: 2018-07-13
Publication date: 2022-03-29
Anticipated expiration: 2038-07-13
Also published as: CN110718255A

Abstract

The embodiment of the invention provides a nonvolatile memory processing method and a nonvolatile memory processing device, wherein the method comprises the following steps: determining first data of a first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation; and if the first data is in the first state, performing discharge operation on the bit line BL corresponding to the memory cell to be detected. In the embodiment of the invention, first data in the first register is determined, if the first data is in a first state, the data is data which does not need programming, and at this time, if the voltage of the BL is maintained, current is continuously supplied to the first to-be-detected cell, so that useless power consumption is caused.

Description

Nonvolatile memory processing method and device

Technical Field

The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for processing a nonvolatile memory.

Background

With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), and the NAND Memory stores data by performing read-write erasing operations on the cells.

In the prior art, a detection unit is usually configured for a nonvolatile memory to perform a write operation on a memory cell, all cells are erased before writing data (Program, PGM), data "1" is obtained in a cell after erasing, then a cycle of PGM + PV (Program Verify) is performed for multiple times, and finally data "0" input by a user is written in the cell.

However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: when the existing detection unit carries out write operation on the storage unit, the power consumption is large, especially the power consumption of a large-capacity NAND memory is very large, and the application of the large-capacity NAND memory in a low-power consumption environment is severely limited.

Disclosure of Invention

In view of the foregoing problems, embodiments of the present invention provide a nonvolatile memory processing method and apparatus to reduce power consumption of a detection unit when writing to a memory cell.

According to a first aspect of the present invention, there is provided a non-volatile memory processing method, the method comprising:

determining first data of a first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation;

and if the first data is in the first state, performing discharge operation on the bit line BL corresponding to the memory cell to be detected.

Preferably, the method further comprises:

and if the first data is in a second state, carrying out charging operation on the bit line BL corresponding to the memory cell to be detected.

Copying data in the second register to the first register through the BUS; the second register is used for storing data input by a user or result data after programming verification;

the BUS is charged.

Establishing a current loop between the BUS and the memory cell to be detected;

if the voltage of the BUS is maintained at a high level, performing programming verification operation on the memory cell to be detected;

if the voltage value of the BUS decreases, the BUS is discharged to 0.

If the voltage of the BUS is high level, writing the level state of the BUS into the first register, and enabling the first register to store second data;

storing the second data in the second register via an OR operation.

According to a second aspect of the present invention, there is provided a non-volatile memory processing apparatus, the apparatus comprising:

the first data determining module is used for determining first data of the first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation;

and the first discharging module is used for performing discharging operation on the bit line BL corresponding to the memory cell to be detected if the first data is in the first state.

Preferably, the apparatus further comprises:

and the first charging module is used for charging the bit line BL corresponding to the memory cell to be detected if the first data is in the second state.

The copying module is used for copying the data in the second register to the first register through the BUS BUS; the second register is used for storing data input by a user or result data after programming verification;

and the second charging module is used for charging the BUS BUS.

The current loop establishing module is used for establishing a current loop between the BUS and the storage unit to be detected;

the verification module is used for performing programming verification operation on the memory cell to be detected if the voltage of the BUS is maintained at a high level;

and the second discharging module is used for discharging the BUS to be 0 if the voltage value of the BUS is reduced.

The write-in module is used for writing the level state of the BUS into the first register if the voltage of the BUS is high level, so that second data are stored in the first register;

and the OR operation module is used for storing the second data in the second register through OR operation.

In the embodiment of the present invention, it is found that the reason that the power consumption is large when the nonvolatile memory performs the write operation in the prior art is as follows: since the cells in the first state "1" are mostly inside one page of the initial PV, since the "1" cells have current flowing through the bit line BL of the nonvolatile memory during the reading process of the PV, assuming that the capacity of the page is 16KB, about 16 × 1024 × 8 × i _ string current flows from the power supply VDD of the SA, even if the current i _ string of one cell is 1uA (or less), the power consumption of hundreds of milliamperes level will exist during the initial PV, and the power consumption is very large. Therefore, in the embodiment of the present invention, first data in the first register is determined, and if the first data is in the first state, it indicates that the data does not need to be programmed, and at this time, if the voltage of the BL is maintained, current is continuously supplied to the first to-be-detected cell, which causes useless power consumption.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a flow chart of a method for processing a non-volatile memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a detection unit circuit according to the present invention;

FIG. 3 is a flowchart illustrating a method for processing a non-volatile memory according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a detection unit circuit applied in a nonvolatile memory processing method according to an embodiment of the present invention;

FIG. 5 is a block diagram of a non-volatile memory processing apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.

Example one

Referring to fig. 1, a flow chart of a nonvolatile memory processing method according to an embodiment of the present invention is shown.

In specific application, referring to fig. 2, a schematic structure diagram of a Nand flash detection unit is shown. The Nand flash has different storage capacities and different sizes of each page, and 1KB/2KB/8KB/16KB and the like are common. Each (or every two) strings (memory cell strings) in the Nand flash is connected with a detection unit (SA) for performing read-write operation on the memory cell. The SA includes a detection module 100 and a register module 200, where the register module is used to store read or write page data. In a specific application, the register module 200 may include a plurality of registers, as shown in fig. 2, a first register S _ RG shown in fig. 2 may store result data of pv (program verify) or READ (READ) each time, and a second register T _ RG may store data to be written.

As shown in fig. 2, the detection module 100 includes: a P-type transistor P1; n-type transistors N1, N2, N3; a resistance R; a capacitance C. The register module 200 includes: BUS, first register S _ RG, second register T _ RG, N-type transistors N4, N5, N6, N7.

In the detection module 100, the source of the P1 is connected to a high level; the drain of the P1 and the drain of the N2 are connected with the BUS; the drain of the N1 is connected with high level; the source of the N1, the source of the N2 and the drain of the N3 are connected; the source of the N3 and one end of the resistor R are connected with one end of the capacitor C; the other end of the R is connected with a memory cell string; the other end of the capacitor C is grounded.

In the register module 200, the sel pin of the first register (for controlling the first register to be selected or not selected) is connected to the BUS, the drain of the N4 is connected to the BUS, the source of the N4 is connected to the drain of the N5, the source of the N5 is grounded, and the gate of the N5 is connected to the inv pin of the first register (which is opposite to the level state of the flgs pin and can reflect the state of data stored in the first register); the sel pin of the second register (for controlling the second register to be selected or not selected) is connected with the BUS, the drain of the N6 is connected with the BUS, the source of the N6 is connected with the drain of the N7, the source of the N7 is grounded, and the gate of the N7 is connected with the inv pin of the second register (which is opposite to the level state of the flgs pin and can reflect the state of data stored in the second register).

The voltage applied to the gate of the P1 is VPRE; the voltage applied to the gate of N1 is VCOMC; the voltage applied to the gate of the N2 is VSENS; the voltage applied to the gate of the N3 is VBLC; the voltage applied to the gate of the N4 is R _ SRG; the voltage applied to the gate of N6 is R _ TRG.

The process of performing READ operation or PV operation on the memory cell to be detected in string is as follows:

the first stage is as follows: by setting VPRE to low, P1 is turned on, the BUS line is precharged to VDD, and P1 is turned off after the BUS charging is completed.

And a second stage: VCOMC and VBLC are kept at high level, N1 and N3 are conducted, and the voltage of VBL is maintained by supplying current through N1 and N3.

And a third stage: setting VSENS to be high level, conducting N2, enabling a current loop to exist between BUS and BL, judging whether BL has current transfer to enable the high level of BUS to change, if BL has current (1 in cell) BUS to be 0, and if BL has no current (0 in cell) BUS to be VDD. Whether a 1 or a 0 is stored in the cell can be known by determining the level of the BUS.

A fourth stage: the SETS pin of the first register is controlled to store the BUS value into the FLG (flag bit) of the S _ RG.

The reading operation of the data from the cell to the register of the SA can be completed once through the four stages.

However, after a great deal of research on the above circuit, the applicant found that: since the "1" cell has current flowing through the bit line BL of the nonvolatile memory during the PV reading process, assuming that the capacity of the page is 16KB, about 16 × 1024 × 8 × i _ string current flows from the power supply VDD of the SA, even if the current i _ string of one cell is 1uA (or less), the power consumption of one hundred milliamperes will be consumed during the initial PV process, and the power consumption is very large.

In view of the above finding, an embodiment of the present invention provides a nonvolatile memory processing method, which specifically includes the following steps:

step 101: determining first data of a first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation.

In the embodiment of the present invention, the first register corresponds to a to-be-detected memory cell, and the first register is used for storing result data of each program verification when the to-be-detected memory cell is subjected to a write operation, specifically, if the result data of each program verification is in a first state "1", it indicates that the data does not need to be programmed, and if the result data of each program verification is in a second state "0", it indicates that the data needs to be programmed.

In specific application, the first data stored in the first register S _ RG can be determined according to the level state of the flgs pin of the first register S _ RG, for example, if the level of the flgs pin is high, it can be reflected that the first data stored in the S _ RG is in the first state "1"; the level of the flgs pin is low, which reflects that the first data stored in the S _ RG is in the second state "0".

Step 102: and if the first data is in the first state, performing discharge operation on the bit line BL corresponding to the memory cell to be detected.

In the embodiment of the present invention, if the first data of the first register S _ RG is in the first state "1", it indicates that PGM is not required, and therefore, the bit line BL corresponding to the first detection unit is discharged, and the voltage of BL is reduced to 0, and no current is supplied to the string of the cell whose data is "1" at PV, thereby achieving the purpose of reducing power consumption.

In a specific application, the bit line BL corresponding to the first detection unit may be connected in parallel to a grounded NMOS transistor, and the first data is input as a gate of the NMOS transistor connected in parallel, so that when the first data is in the first state "1", the NMOS transistor connected in parallel is turned on, and the BL is grounded, so that the voltage drop of the BL is 0. It is understood that a person skilled in the art may also use other ways to associate the voltage of the BL with the first data, and when the first data is "1", the discharging of the BL is implemented, which is not specifically limited in this embodiment of the present invention.

Example two

Referring to fig. 3, a specific flowchart of a processing method of a non-volatile memory according to an embodiment of the present invention is shown, and for more clearly illustrating an implementation method of the implementation of the present invention, the embodiment of the present invention is described with reference to a circuit diagram.

As shown in fig. 4, a P-type transistor P0 and an N-type transistor N0 are added to the embodiment of the present invention based on fig. 2. Wherein the source of the P0 replaces the drain of the N1 to be connected high, and the drain of the P0 is connected with the drain of the N1; the drain electrode of the N0 is connected with the ungrounded end of the capacitor C; the source of the N0 is grounded; the gates of both the P0 and the N0 can receive the level state of flgs in the first register, and the other connections in fig. 4 are the same as those in fig. 2, and are not repeated here.

It should be understood that the circuit diagram is only for clearly explaining the present invention, and is not used for limiting the present invention, and a person skilled in the art may combine with common general knowledge in the art or conventional technical means to build other circuits to implement the nonvolatile memory processing method of the embodiment of the present invention, and the embodiment of the present invention does not specifically limit the actual circuit and the scenario applied.

The method may specifically comprise the steps of:

step 201: copying data in the second register to the first register through the BUS; the second register is used for storing data input by a user or result data after programming verification.

In the embodiment of the invention, firstly, data input by a user in the second register or result data after last programming verification is copied into the first register through the BUS BUS, namely, the data input by the user in the T _ RG or the result of last PV is copied into the S _ RG, so that the register operation of the S _ RG and the T _ RG is realized. Taking fig. 4 as an example, the register operation method may specifically be:

firstly, VPRE is set to be low level, P1 is conducted, BUS is precharged to be high level, P1 is turned off after BUS charging is finished, BUS is connected with sel pin of S _ RG, BUS is high level, S _ RG can be selected, and in specific application, an S _ RG register can be cleared to zero through a reset pin RSTS of S _ RG.

Then, R _ TRG reads out the data of T _ RG to BUS, and then controls SETS pin of S _ RG to write the T _ RG data of BUS into S _ RG.

Step 202: the BUS is charged.

In the embodiment of the invention, after the data input by the user in the second register or the result data after the last programming verification is copied to the first register through the BUS, the BUS may have level change, the level of the BUS can be changed into high level through setting VPRE to be low level, conducting P1, recharging the BUS line, and turning off P1 after the BUS is charged.

Step 203: determining first data of a first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation.

Step 204: and if the first data is in the first state, performing discharge operation on the bit line BL corresponding to the memory cell to be detected.

Step 205: and if the first data is in a second state, carrying out charging operation on the bit line BL corresponding to the memory cell to be detected.

In the embodiment of the present invention, as shown in fig. 4, if S _ RG is the first state "1" data not requiring PGM, N0 is turned on, and the corresponding BL is discharged to zero through N0. Therefore, current is not provided for string of the 1 cell during PV, and the purpose of reducing power consumption is achieved.

If the first data in S _ RG is the second state "0" data requiring PGM, P0 is turned on while VCOMC, VBLC is set high, N1, N3 are turned on, BL is charged through P0, N1, N3 and string current is supplied to maintain the voltage of BL.

Step 206: and establishing a current loop between the BUS and the storage unit to be detected.

In the embodiment of the present invention, as shown in fig. 4, VSENS is set to a high level, N2 is turned on, and a current loop exists between BUS and BL.

Step 207: and if the voltage of the BUS is maintained at a high level, performing programming verification operation on the memory cell to be detected.

In the embodiment of the present invention, as shown in fig. 4, when PV is performed by "0" cell of PGM, if string current is small enough to keep BUS at VDD when N2 is turned on, it can be determined that the cell threshold reaches the target value.

Step 208: and if the voltage of the BUS is at a high level, writing the level state of the BUS into the first register so as to store second data in the first register.

In the embodiment of the present invention, if BUS is VDD, which indicates that cell PGM has been successfully put into "0" state, S _ RG is written into 1, so that the second data stored in the first register is "1". The SETS pin can be controlled to write BUS into S _ RG.

Step 209: storing the second data in the second register via an OR operation.

In the embodiment of the present invention, storing the second data in the second register through an or operation may specifically be implemented in the following manner: the register operation T _ RG is T _ RG | S _ RG, and the result S _ RG of this time PV is "or" entered into T _ RG. The cell that has successfully PGM to "0" state has S _ RG of 1 or T _ RG of 1 after calculation, and the cell will not participate in the process of PGM and PV during the next PGM + PV, further achieving reduced power consumption.

In the specific application, the OR operation method comprises the following steps: by setting VPRE to low, P1 is turned on, BUS is made VDD, S _ RG is selected, R _ SRG reads data of S _ RG to BUS, and then SETT pin of T _ RG is controlled to put result of S _ RG on BUS or into T _ RG.

It can be understood that the embodiment of the present invention is not limited to the foregoing implementation of embodying the data of the S _ RG on the BUS, and a person skilled in the art may select other manners according to practical application scenarios, and the embodiment of the present invention is not limited to this.

Step 210: if the voltage value of the BUS decreases, the BUS is discharged to 0.

If the voltage value of BUS decreases, indicating that the cell may not yet have PGM in the target "0" state, S _ RG maintains the original value of "0", and the cycle of PGM + PV continues.

If the voltage value of BUS decreases, which may also be "1" in the cell for which PGM is not expected, when PV is performed on the cell: FLGS acts on N0 and discharges BUS to 0 through N2, N3, so that S _ RG of "1" cell is not selected. In a specific application, the process of discharging the BUS to 0 can also be realized by changing the circuit of FIG. 4, specifically: and connecting the output flgs of the S _ RG to the grid of the N5 to realize the discharge of the BUS of the 1 cell.

It can be understood that, according to an actual application scenario, a person skilled in the art may also discharge the BUS to 0 in other manners when the voltage value of the BUS decreases, which is not specifically limited in the embodiment of the present invention.

According to the scheme, through register operation, 1 cells which do not need PGM and 0 cells which do not need PGM and reach the target state are screened out through S _ RG, BL charging is not carried out during next PV, current is not provided for string, and therefore the purpose of reducing power consumption is achieved.

It should be noted that the foregoing method embodiments are described as a series of acts or combinations for simplicity in explanation, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

EXAMPLE III

Referring to fig. 5, there is shown a block diagram of a non-volatile memory processing apparatus, which may specifically include:

a first data determining module 310 for determining first data of the first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation;

the first discharging module 320 is configured to perform a discharging operation on the bit line BL corresponding to the memory cell to be detected if the first data is in the first state.

Preferably, the apparatus further comprises:

and the second charging module is used for charging the BUS BUS.

For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

In a typical configuration, the computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), electrically-processable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (fransitory media), such as modulated data signals and carrier waves.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable non-volatile memory processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable non-volatile memory processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable non-volatile processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable non-volatile memory processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The present invention provides a nonvolatile memory processing method and a nonvolatile memory processing apparatus, which have been described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A non-volatile memory processing method, the method comprising:

copying data input by a user in the second register or result data after last programming verification into the first register through the BUS; the first register and the second register both belong to a detection unit SA, and the first register corresponds to a storage unit to be detected;

determining first data in a first register according to the level state of a flgs pin of the first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation; the level state of the flgs pin of the first register is a high level, which reflects that the first data stored in the first register is a first state, and the level state of the flgs pin of the first register is a low level, which reflects that the first data stored in the first register is a second state, and the second state is '0';

if the first data is in a first state, performing discharge operation on a bit line BL corresponding to the memory cell to be detected; wherein the first state is "1", which indicates that the first data is data that does not require program verification.

2. The method of claim 1, further comprising:

3. The method of claim 2, wherein the step of determining the first data of the first register is preceded by the step of:

copying data in the second register to the first register through the BUS; the second register is used for storing data input by a user or data after programming verification;

the BUS is charged.

4. The method of claim 3, further comprising:

establishing a current loop between the BUS and the memory cell to be detected;

if the voltage value of the BUS decreases, the BUS is discharged to 0.

5. The method of claim 4, further comprising:

storing the second data in the second register via an OR operation.

6. A non-volatile memory processing apparatus, the apparatus comprising:

the first data determining module is used for determining first data of the first register according to the level state of the flgs pin of the first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation; the level state of the flgs pin of the first register is a high level, which reflects that the first data stored in the first register is a first state, and the level state of the flgs pin of the first register is a low level, which reflects that the first data stored in the first register is a second state, and the second state is '0';

the first discharging module is used for performing discharging operation on the bit line BL corresponding to the memory cell to be detected if the first data is in the first state; wherein the first state is "1", which indicates that the first data is data that does not require program verification.

7. The apparatus of claim 6, further comprising:

8. The apparatus of claim 7, further comprising:

and the second charging module is used for charging the BUS BUS.

9. The apparatus of claim 8, further comprising:

10. The apparatus of claim 9, further comprising: