CN104157304A - Tamper resistant memory element - Google Patents
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- CN104157304A CN104157304A CN201410378139.XA CN201410378139A CN104157304A CN 104157304 A CN104157304 A CN 104157304A CN 201410378139 A CN201410378139 A CN 201410378139A CN 104157304 A CN104157304 A CN 104157304A
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- 230000014759 maintenance of location Effects 0.000 claims description 2
- 101150110971 CIN7 gene Proteins 0.000 description 7
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- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Abstract
The invention provides a tamper resistant memory element. The tamper resistant storage element includes: a static random access memory cell comprising first and second inverters, the outputs of the first and second inverters being respectively a first storage node and a second storage node, the values stored in the first and second storage nodes together representing data stored by the static random access memory cell; the output of the first inverter and the output of the second inverter are respectively connected to the control end of the other side through the first CMOS complementary transmission gate and the second CMOS complementary transmission gate. The embodiment of the invention improves the noise margin when reading 1 or 0, and simultaneously the threshold voltage loss is not too large.
Description
Technical field
The present invention relates to static RAM (SRAM) technical field, more specifically, relate to anti-interference memory element.
Background technology
According to data storage method, semiconductor memory is divided into dynamic RAM (DRAM), non-volatility memorizer and static RAM (SRAM).SRAM can realize operating speed fast in a kind of mode simple and low-power consumption, thereby sets up its unique advantage.And compared with DRAM, because SRAM does not need periodic refresh canned data, Design and manufacture is relatively easy.
Conventionally, sram cell is made up of two driving transistorss, two load devices and two access transistors, according to the type of contained load device, SRAM itself can be divided into again complete complementary metal-oxide semiconductor (MOS) (CMOS) SRAM, high capacity resistance (High Load Resistor) SRAM and thin film transistor (TFT) (Thin FilmTransistor) SRAM.CMOS SRAM uses PMOS transmission transistor as load device completely, and HLRSRAM uses high capacity resistance as load device, and TFT SRAM uses multi-crystal TFT as load device.
The circuit of a traditional complete CMOS SRAM is shown in Figure 1.As shown in Figure 1, phase inverter (NMOS transmission transistor M1 and PMOS transmission transistor M5 form a phase inverter, and NMOS transmission transistor M2 and PMOS transmission transistor M6 form a phase inverter) and two transmission transistors (NMOS transmission transistor M3 and NMOS transmission transistor M4) that its basic structure contains two clampers.Word line WL controls M3 and M4, in the time reading with write operation, and M3 and M4 conducting.While reading, two bit line BLB and BL are all precharged to high level.Write at 0 o'clock, BL=1, BLB=0; Write at 1 o'clock, BL=0, BLB=1.
Existing sram cell, in read operation, BL and BLB are precharged to Vdd/2.Due to transistorized voltage divider principle, cause storing 0 node voltage and rise, thereby static noise margin is reduced.As shown in Figure 1, in the time of read operation, two bit lines BL and BLB charge to respectively Vdd/2, if left side memory node Q storing value is 1, the right memory node QB storing value is 0, in the time of read operation, and WL=1, M3 conducting, due to 1 of Q storage, M2 transistor gate voltage is always in opening.BLB reads 0 o'clock that in QB, stores, and itself is charged to high level, and therefore M2 and M4 form a discharge path, and QB voltage is from 0 rising.Then, if QB voltage rises to a certain degree, the grid that is connected to M1 due to QB voltage, as control signal, can make M1 conducting, thus drop-down Q point current potential, and whole sram memory storage data all can be overturn.
Thus, in maintenance after read operation operation, the node voltage of storage 0 rise to 0 to Vdd/2 between certain level, this depends on the conducting resistance between M2 and M4.At this moment,, if this node is subject to the disturbance of a noise voltage again, just more easily overturn, thereby static noise margin reduces.
Equally, the problem that also exists storage node voltage to change in the time reading " 1 ".In Fig. 1, BL and BLB were precharged to Vdd/2 before reading storage data, if Q=1, QB=0, M3 and M5 form path, Q point current potential certain level between Vdd/2 and Vdd, this depends on the size of M3 and M5 conducting resistance.At this moment,, if this node is subject to the disturbance of a noise voltage again, also easily overturn, thereby static noise margin reduces.
In order to increase noise margin, people have proposed ten pipe sram cells, and this sram cell is on original SRAM six tubular constructions, to have increased by tetra-MOS transistor of M7～M10, and remains unlatching.As shown in Figure 2, if memory node overturns, the transmission transistor of these four conductings all the time serves as resistance and electric capacity, RC path can postpone the flip-flop transition of node, thereby makes PMOS transistor M3, the M4 and pull-down NMOS transistor M1, the M2 that draw can have time enough to recover the level of storage node.But because this sram cell has following shortcoming, make it fail to be widely used.There is threshold voltage loss in first, independent NMOS or PMOS; In Fig. 2 there is voltage difference in the drain terminal of M1 and M3, thereby make memory node easily be subject to the impact of noise.
Summary of the invention
The present invention is directed to the problems referred to above that prior art exists, proposed a kind of new sram cell of high reliability, read 1 or the noise margin of 0 o'clock thereby improve, threshold voltage loss is simultaneously unlikely to excessive.
According to one embodiment of present invention, a kind of anti-interference memory element is provided, comprise: static random access memory cell, comprise the first and second phase inverters, the output of described the first and second phase inverters is respectively the first memory node and the second memory node, and the value of described the first and second memory node storages represents the data of described static random access memory cell storage altogether; The one CMOS complementary transmission gate, the 2nd CMOS complementary transmission gate, wherein the output of the first and second phase inverters is linked the other side's control end through a CMOS complementary transmission gate, the 2nd CMOS complementary transmission gate respectively.
Alternatively, the one CMOS complementary transmission gate is formed in parallel by a NMOS transmission transistor and a PMOS transmission transistor, the 2nd CMOS complementary transmission gate is formed in parallel by the 2nd NMOS transmission transistor and the 2nd PMOS transmission transistor, a described NMOS transmission transistor, the grid of the 2nd NMOS transmission transistor connects voltage source, a described PMOS transmission transistor, the grid of the 2nd PMOS transmission transistor connects ground, the drain electrode of a described NMOS transmission transistor and a PMOS transmission transistor is connected in the first memory node, the source electrode of a described NMOS and a PMOS transmission transistor is connected in the control end of the second phase inverter, the drain electrode of described the 2nd NMOS transmission transistor and the 2nd PMOS transmission transistor is connected in the control end of the first phase inverter, the source electrode of described the 2nd NMOS transmission transistor and the 2nd PMOS transmission transistor is connected in the second memory node QB.
Alternatively, the first phase inverter comprises the 3rd PMOS transmission transistor, the 3rd NMOS transmission transistor in parallel, the source electrode of the 3rd PMOS transmission transistor connects voltage source, the drain electrode of the drain electrode of the 3rd PMOS transmission transistor and the 3rd NMOS transmission transistor is connected together and forms the first memory node, the source electrode of the 3rd NMOS transmission transistor connects ground, and the grid of the 3rd PMOS transmission transistor, the 3rd NMOS transmission transistor is connected together and forms the control end of the first phase inverter.The second phase inverter comprises the 4th PMOS transmission transistor, the 4th NMOS transmission transistor in parallel, the source electrode of the 4th PMOS transmission transistor connects voltage source, the drain electrode of the drain electrode of the 4th PMOS transmission transistor and the 4th NMOS transmission transistor is connected together and forms the second memory node, the source electrode of the 4th NMOS transmission transistor connects ground, and the grid of the 4th PMOS transmission transistor, the 4th NMOS transmission transistor are connected together and form the control end of the second phase inverter.
Alternatively, the first memory node connects the drain electrode of the 5th NMOS transmission transistor, the source electrode of the 5th NMOS transmission transistor connects the first bit line, the second memory node connects the source electrode of the 6th NMOS transmission transistor, the drain electrode of the 6th NMOS transmission transistor connects the second bit line, and the grid of the 5th NMOS transmission transistor, the 6th NMOS transmission transistor connects word line.
Alternatively, the equivalent capacity of a CMOS complementary transmission gate, the 2nd CMOS complementary transmission gate is identical.
Because the output of the first and second phase inverters of the embodiment of the present invention is linked the other side's control end through a CMOS complementary transmission gate, the 2nd CMOS complementary transmission gate respectively, the one CMOS complementary transmission gate, the 2nd CMOS complementary transmission gate serve as resistance and electric capacity in the time that upset occurs memory node, resistance and capacitance path can extend the flip-flop transition of memory node, thereby make the transistor in the first and second phase inverters have time enough to recover the level of memory node, read 1 or the noise margin of 0 o'clock thereby improve.Meanwhile, adopt complementary transmission gate design, compared with single metal-oxide-semiconductor, the loss of threshold voltage while not having memory node through transmission gate.
Brief description of the drawings
Fig. 1 is the circuit connection diagram of the complete CMOS SRAM that prior art is traditional;
Fig. 2 is the circuit connection diagram of ten pipe SRAM of prior art;
Fig. 3 is the circuit diagram of the anti-interference memory element that provides of one embodiment of the invention.
Embodiment
Clear for object of the present invention, technical scheme and advantage are understood more, below in conjunction with drawings and Examples, the present invention is described in more detail.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Fig. 3 shows anti-interference according to an embodiment of the invention memory element.This anti-interference memory element comprises: static random access memory cell, comprise the first and second phase inverter INV1, INV2, described the first and second phase inverter INV1, the output of INV2 is respectively the first memory node Q and the second memory node QB, described the first and second memory node Q, the value of QB storage represents the data of described static random access memory cell storage altogether; The one CMOS complementary transmission gate M7, M8, the 2nd CMOS complementary transmission gate M9, M10, wherein the first and second phase inverter INV1, the output of INV2 is respectively through a CMOS complementary transmission gate M7, M8, the 2nd CMOS complementary transmission gate M9, M10 link the other side's control end Q ', QB '.
Alternatively, the one CMOS complementary transmission gate M7, M8 is formed in parallel by a NMOS transmission transistor M7 and a PMOS transmission transistor M8, and the 2nd CMOS complementary transmission gate M9, M10 are formed in parallel by the 2nd NMOS transmission transistor M9 and the 2nd PMOS transmission transistor M10.The grid of the one NMOS transmission transistor M7, the 2nd NMOS transmission transistor M9 connects voltage source V
dD, the grid of a described PMOS transmission transistor M8, the 2nd PMOS transmission transistor M10 connects ground GND.The drain electrode of a described NMOS transmission transistor M7 and a PMOS transmission transistor M8 is connected in the first memory node Q, and the source electrode of a described NMOS transmission transistor M7 and a PMOS transmission transistor M8 is connected in the control end Q ' of the second phase inverter INV2.The drain electrode of described the 2nd NMOS transmission transistor M9 and the 2nd PMOS transmission transistor M10 is connected in the control end QB ' of the first phase inverter INV1, and the source electrode of described the 2nd NMOS transmission transistor M9 and the 2nd PMOS transmission transistor M10 is connected in the second memory node QB.
Alternatively, the first phase inverter INV1 comprises the 3rd PMOS transmission transistor M5, the 3rd NMOS transmission transistor M1 in parallel.The source electrode of the 3rd PMOS transmission transistor M5 connects voltage source V
dD, the drain electrode of the drain electrode of the 3rd PMOS transmission transistor M5 and the 3rd NMOS transmission transistor M1 is connected together and forms the first memory node Q, and the source electrode of the 3rd NMOS transmission transistor M1 connects ground GND.The grid of the 3rd PMOS transmission transistor M5, the 3rd NMOS transmission transistor M1 is connected together and forms the control end QB ' of the first phase inverter INV1.
Alternatively, the second phase inverter INV2 comprises the 4th PMOS transmission transistor M6, the 4th NMOS transmission transistor M2 in parallel.The source electrode of the 4th PMOS transmission transistor M6 connects voltage source V
dD, the drain electrode of the drain electrode of the 4th PMOS transmission transistor M6 and the 4th NMOS transmission transistor M2 is connected together and forms the second memory node QB, and the source electrode of the 4th NMOS transmission transistor M2 connects ground GND.The grid of the 4th PMOS transmission transistor M6, the 4th NMOS transmission transistor M2 are connected together and form the control end Q ' of the second phase inverter INV2.
Alternatively, the first memory node Q connects the drain electrode of the 5th NMOS transmission transistor M3, and the source electrode of the 5th NMOS transmission transistor M3 meets the first bit line BL.The second memory node QB connects the source electrode of the 6th NMOS transmission transistor M4, and the drain electrode of the 6th NMOS transmission transistor M4 meets the second bit line BLB.The grid of the 5th NMOS transmission transistor M3, the 6th NMOS transmission transistor M4 meets word line WL.
Alternatively, a CMOS complementary transmission gate M7, the equivalent capacity of M8, the 2nd CMOS complementary transmission gate M9, M10 is identical.The beneficial effect doing is like this, because a CMOS complementary transmission gate, the 2nd CMOS complementary transmission gate are in the time there is upset in memory node, because its equivalent capacity is identical, the degree of the flip-flop transition of prolongation memory node is identical, in the time reading 1 or 0, can have roughly balanced noise margin like this, be unlikely to make to read 1 noise margin fine and read 0 noise margin slightly a little less than, otherwise or, that is to say, be unlikely to show different interference free performances for reading 1 and 0.
The first and second phase inverter INV1 in Fig. 3, INV2, the 5th NMOS transmission transistor M3, the 6th NMOS transmission transistor M4 are identical with Fig. 1, are traditional static random access memory cells, have two node Q, QB.The topmost difference of Fig. 3 and Fig. 1 is, has added a CMOS complementary transmission gate M7, M8, the 2nd CMOS complementary transmission gate.
The principle of work of this anti-interference memory element is as follows.
The in the situation that of storage node voltage generation saltus step, this anti-interference memory element structure has enough time to make saltus step node recover initial value.For example, in the time that the voltage of memory node Q is 0 from 1 saltus step, a because CMOS complementary transmission gate M7, in M8, metal-oxide-semiconductor dead resistance and stray capacitance are equivalent to a RC circuit, thereby gate capacitance, node capacitor etc. to metal-oxide-semiconductor charge, therefore the change in voltage of memory node Q can be delayed a period of time and just become 0.During this period of time, because saltus step does not occur the voltage of memory node QB, the 2nd CMOS complementary transmission gate M9 that can not be attached thereto, the RC circuit of M10 carry out charging and discharging, therefore life period is not delayed, the voltage of memory node QB remains 0, the voltage of QB ' also remains 0, and the grid voltage of NMOS transmission transistor M1 and PMOS transmission transistor M5 remains 0.The voltage of memory node Q is pulled to high level 1 by PMOS transmission transistor M5 conducting, and therefore whole anti-interference memory element has time enough to revert to 1 by the voltage of memory node Q from 0 in the situation that of storage node voltage generation saltus step.In like manner can analyze other saltus step situation.Therefore, the present invention has effectively strengthened the stability of storage unit, has improved antijamming capability when data write or read.
There is threshold value loss in NMOS transmission transistor, do not have threshold value loss when transmission low level in the time of transmission high level; There is threshold value loss in PMOS transmission transistor, do not have threshold value loss when transmission high level in the time of transmission low level.CMOS complementary transmission gate is " complementation " characteristic based on NMOS transmission transistor and PMOS transmission transistor just, conducting NMOS transmission transistor in the time of transmission low level,, therefore in the time of the high and low level of transmission, there is not threshold value loss in conducting PMOS transmission transistor when transmission high level.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned example embodiment, and in the situation that not deviating from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Any Reference numeral in claim should be considered as limiting related claim.
Claims (5)
1. an anti-interference memory element, is characterized in that comprising:
Static random access memory cell, comprise the first and second phase inverter (INV1, INV2), described the first and second phase inverter (INV1, INV2) output is respectively the first memory node (Q) and the second memory node (QB), the value of described the first and second memory node (Q, QB) storages represents the data of described static random access memory cell storage altogether;
The one CMOS complementary transmission gate (M7, M8), the 2nd CMOS complementary transmission gate (M9, M10), wherein the first and second phase inverter (INV1, INV2) output is respectively through a CMOS complementary transmission gate (M7, M8), the 2nd CMOS complementary transmission gate (M9, M10) is linked the other side's control end (Q ', QB ').
2. anti-interference memory element according to claim 1, it is characterized in that, the one CMOS complementary transmission gate (M7, M8) be formed in parallel by a NMOS transmission transistor (M7) and a PMOS transmission transistor (M8), the 2nd CMOS complementary transmission gate (M9, M10) is formed in parallel by the 2nd NMOS transmission transistor (M9) and the 2nd PMOS transmission transistor (M10), and the grid of a described NMOS transmission transistor (M7), the 2nd NMOS transmission transistor (M9) connects voltage source (V
dD), a described PMOS transmission transistor (M8), the grid of the 2nd PMOS transmission transistor (M10) connects ground (GND), the drain electrode of a described NMOS transmission transistor (M7) and a PMOS transmission transistor (M8) is connected in the first memory node (Q), the source electrode of a described NMOS transmission transistor (M7) and a PMOS transmission transistor (M8) is connected in the control end (Q ') of the second phase inverter (INV2), the drain electrode of described the 2nd NMOS transmission transistor (M9) and the 2nd PMOS transmission transistor (M10) is connected in the control end (QB ') of the first phase inverter (INV1), the source electrode of described the 2nd NMOS transmission transistor (M9) and the 2nd PMOS transmission transistor (M10) is connected in the second memory node QB.
3. anti-interference memory element according to claim 1, it is characterized in that, the first phase inverter (INV1) comprises the 3rd PMOS transmission transistor (M5), the 3rd NMOS transmission transistor (M1) in parallel, and the source electrode of the 3rd PMOS transmission transistor (M5) meets voltage source (V
dD), the drain electrode of the drain electrode of the 3rd PMOS transmission transistor (M5) and the 3rd NMOS transmission transistor (M1) is connected together and forms the first memory node (Q), the source electrode of the 3rd NMOS transmission transistor (M1) connects ground (GND), the grid of the 3rd PMOS transmission transistor (M5), the 3rd NMOS transmission transistor (M1) is connected together and forms the control end (QB ') of the first phase inverter (INV1)
The second phase inverter (INV2) comprises the 4th PMOS transmission transistor (M6), the 4th NMOS transmission transistor (M2) in parallel, and the source electrode of the 4th PMOS transmission transistor (M6) meets voltage source (V
dD), the drain electrode of the drain electrode of the 4th PMOS transmission transistor (M6) and the 4th NMOS transmission transistor (M2) is connected together and forms the second memory node (QB), the source electrode of the 4th NMOS transmission transistor (M2) connects ground (GND), and the grid of the 4th PMOS transmission transistor (M6), the 4th NMOS transmission transistor (M2) are connected together and form the control end (Q ') of the second phase inverter (INV2).
4. anti-interference memory element according to claim 1, it is characterized in that, the first memory node (Q) connects the drain electrode of the 5th NMOS transmission transistor (M3), the source electrode of the 5th NMOS transmission transistor (M3) connects the first bit line (BL), the second memory node (QB) connects the source electrode of the 6th NMOS transmission transistor (M4), the drain electrode of the 6th NMOS transmission transistor (M4) connects the second bit line (BLB), and the grid of the 5th NMOS transmission transistor (M3), the 6th NMOS transmission transistor (M4) connects word line (WL).
5. anti-interference memory element according to claim 1, is characterized in that, the equivalent capacity of a CMOS complementary transmission gate (M7, M8), the 2nd CMOS complementary transmission gate (M9, M10) is identical.
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Cited By (5)
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| WO2016154824A1 (en) * | 2015-03-27 | 2016-10-06 | 中国科学院自动化研究所 | Resistor-capacitor reinforcement-based memory cell of static random access memory |
| WO2016154826A1 (en) * | 2015-03-27 | 2016-10-06 | 中国科学院自动化研究所 | Storage unit of static random access memory based on resistance reinforcement |
| CN107103928A (en) * | 2017-04-27 | 2017-08-29 | 苏州无离信息技术有限公司 | A kind of new 8TSRAM element circuits system |
| CN107123440A (en) * | 2017-04-27 | 2017-09-01 | 苏州无离信息技术有限公司 | A kind of new 9TSRAM element circuits system |
| CN109903796A (en) * | 2019-01-10 | 2019-06-18 | 中国人民武装警察部队海警学院 | Using 10 transistor memory units of P-P-N and P-N-N mixed structure |
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| WO2016154824A1 (en) * | 2015-03-27 | 2016-10-06 | 中国科学院自动化研究所 | Resistor-capacitor reinforcement-based memory cell of static random access memory |
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| CN107123440A (en) * | 2017-04-27 | 2017-09-01 | 苏州无离信息技术有限公司 | A kind of new 9TSRAM element circuits system |
| CN109903796A (en) * | 2019-01-10 | 2019-06-18 | 中国人民武装警察部队海警学院 | Using 10 transistor memory units of P-P-N and P-N-N mixed structure |
| CN109903796B (en) * | 2019-01-10 | 2021-01-15 | 中国人民武装警察部队海警学院 | 10-tube storage unit adopting P-P-N and P-N-N mixed structure |
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Application publication date: 20141119 |