CN103650180A - 用于光学器件的基板 - Google Patents

用于光学器件的基板 Download PDF

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Publication number
CN103650180A
CN103650180A CN201280034858.9A CN201280034858A CN103650180A CN 103650180 A CN103650180 A CN 103650180A CN 201280034858 A CN201280034858 A CN 201280034858A CN 103650180 A CN103650180 A CN 103650180A
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optical element
substrate
element substrate
optics
base board
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CN103650180B (zh
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南基明
全永哲
宋台焕
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Pu Yinte Engineering Co Ltd
Point Engineering Co Ltd
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Pu Yinte Engineering Co Ltd
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  • Optical Couplings Of Light Guides (AREA)

Abstract

本发明涉及一种用于光学器件的基板，其配置成以装配方式连接光学元件基板和电极基板，并且同时配置成在光学元件基板上形成一个或多个桥垫，该桥垫通过水平绝缘层与光学元件基板绝缘。根据本发明的第一方面的用于光学器件的基板包括：光学元件基板，其由金属板制成并且其中包含多个光学元件；一对电极基板，其由绝缘材料制成以在其上表面的至少一部分上形成传导层，分别连接至光学元件基板的两个侧表面，以及引线结合至光学元件的电极；以及装配装置，其形成在电极基板和光学元件基板的侧表面上，以装配光学元件基板和电极基板。根据本发明的第二方面的用于光学器件的基板包括：光学元件基板，其由金属板制成并且其中设置有多个光学元件；一对电极基板，其由金属材料制成以分别连接至光学元件基板的两个侧表面，以及引线结合至光学元件的电极；装配装置，其形成在电极基板和光学元件基板的侧表面上，以装配光学元件基板和电极基板；以及装配型垂直绝缘层，其***在光学元件基板和电极基板之间，以便连接至装配装置。

Description

用于光学器件的基板
技术领域
本发明涉及一种用于光学器件的基板，并且更具体地，涉及一种用于光学器件的基板，该光学器件配置成以装配方式连接光学元件基板和电极基板，并且同时配置成在光学元件基板上形成一个或多个桥垫（bridgepad），该桥垫通过水平绝缘层与光学元件基板绝缘。
背景技术
通常，作为半导体发光器件的发光二极管（LED）已经吸引了相当多的关注，原因在于有利于环境保护的光源在各个领域都不会造成环境污染。最近，随着LED的使用扩展到各个领域，例如，室内和室外照明、车辆前灯、显示器的背光单元（BLU）等，已经要求LED具有高的效率和卓越的散热特性。为了获得高效LED，必须改进LED原材料或结构，并且也要求改进LED封装的结构和在LED封装中使用的原材料。
因为高效LED产生高热，当高热没有被有效消散时，LED的温度变高，因此LED的特性破坏，从而减少了LED的寿命。因此，已经致力于有效地消散从这种LED产生的热。
在下文中，将各个发光元件（例如，LED等）称为“光学元件”，并且将各个产品（每个包括一个或多个光学元件）称为“光学器件”。
图1A至1D是解释光学器件的传统制造方法的透视图。首先，如图1A中所示，为了形成用于安装光学元件的传统基板10，将具有预定厚度的传导板11（例如，铜板等）和绝缘板12（例如，玻璃环氧板等）在平面方向上彼此交替附接，以形成块主体13（参照图1B）。这里，传导板11和绝缘板12的附接可以通过粘合剂、热压等进行。
随后，如图1B中所示，当沿着垂直于传导板11平面的方向切割（即，垂直切割）如图1A中的块主体13，如图1C所示，获得包括交替布置的传导条10a和绝缘条10b的基板10。
随后，如图1D所示，在基板10的传导条（10a-①、10a-②、10a-③）上分别设置有以规则间隔布置的LED芯片2，设置在传导条（10a-①、10a-②、10a-③）上的每个LED芯片2通过引线3重复地连接至后续的传导条，以获得LED阵列，并且然后用透明树脂模制成型LED阵列，以制备板形LED阵列。
同时，板形LED阵列的行彼此并联地电连接，并且其列彼此并联地电连接。该板形LED阵列可以直接地制成产品，或者可以通过将行和列划分成合适的行和列单元或者单个行和列单元制成产品。此外，当直接使用板形LED阵列时，将它安装在金属PCB上或者用散热板设置在其下部。
然而，上述传统的用于光学器件的基板的问题在于其传导条和绝缘条通过粘合剂或热压附接，因而传导条和绝缘条之间的连接容易被处理中粗心导致的轻微的冲击、弯曲或者歪斜损坏。
发明内容
技术问题
因此，本发明致力于解决上述问题，并且本发明的目的在于提供一种用于光学器件的基板，其不会被处理中粗心导致的冲击、弯曲或歪斜损坏，原因在于其配置成以装配方式连接光学元件基板和电极基板，并且同时不形成用于将光学元件基板绝缘成多个区域的水平绝缘层。
本发明的另一目的在于提供一种用于光学器件的基板，其不会被处理中粗心导致的冲击、弯曲或歪斜损坏，原因在于其配置成以装配方式连接光学元件基板和电极基板，并且同时在光学元件基板上形成一个或多个桥垫，该桥垫通过水平绝缘层与光学元件基板绝缘。
技术方案
为了实现上述目的，本发明的第一方面提供了一种用于光学器件的基板，包括：光学器件基板，其由金属板制成并且其中设置有多个光学元件；一对电极基板，其由绝缘材料制成以在其上表面的至少一部分上形成传导层，该对电极基板分别连接至光学元件基板的两个侧表面，以及引线结合至光学元件的电极；以及装配装置，其形成在电极基板和光学元件基板的侧表面上，以装配光学元件基板和电极基板。
在根据本发明的第一方面的用于光学器件的基板中，光学元件基板可以设置有腔，该腔包括矩形凹槽，该矩形凹槽中安装有多个光学元件。此外，光学元件基板可以设置有多个腔，每个腔包括凹槽，该凹槽中安装有光学元件。
本发明的第二方面提供了一种用于光学器件的基板，包括：光学元件基板，其由金属板制成并且其中设置有多个光学元件；一对电极基板，其由金属材料制成，分别连接至光学元件基板的两个侧表面，以及引线结合至光学元件的电极；装配装置，其形成在电极基板和光学元件基板的侧表面上，以装配光学元件基板和电极基板；以及装配型垂直绝缘层，其***在光学元件基板和电极基板之间，以便连接至装配装置。
在根据本发明的第二方面的用于光学器件的基板中，装配型垂直绝缘层可以通过使光学元件基板和电极基板的包括装配装置的侧表面阳极氧化而形成。
此外，光学元件基板可以设置有腔，该腔包括矩形凹槽，该矩形凹槽中安装有多个光学元件。进一步地，光学元件基板可以设置有多个腔，每个腔包括凹槽，该凹槽中安装有光学元件。
在根据本发明的第一或第二方面的用于光学器件的基板中，光学元件基板可以包括形成在其上表面上的镀层。根据本发明的第一或第二方面的用于光学器件的基板还可以包括：水平绝缘层，其形成在光学元件基板的至少一个镀层已去除的区域上，以与镀层电连接；以及桥垫，其布置在水平绝缘层上以允许光学元件的电极通过引线电连接。在这种情况下，水平绝缘层可以形成在凹槽中，该凹槽形成在光学元件基板的镀层已去除的区域中。
有益效果
根据本发明的光学器件的基板的优点在于：其不会被处理中粗心导致的冲击、弯曲或歪斜损坏，原因在于其配置成以装配方式连接光学元件基板和电极基板，并且同时在光学元件基板上形成一个或多个桥垫，该桥垫通过水平绝缘层与光学元件基板绝缘。
附图说明
图1A至1D是解释光学器件的传统制备方法的透视图。
图2是根据本发明的实施方式通过用于光学器件的基板制备的光学器件的截面图。
图3是根据本发明的另一实施方式通过用于光学器件的基板制备的光学器件的截面图。
图4是通过用于图2的光学器件的局部修改的基板制备的光学器件的截面图，以及图5是通过用于图3的光学器件的局部修改的基板制备的光学器件的截面图。
图6是在不***桥垫的情况下通过芯片对芯片引线结合光学元件的电极制备的光学器件的截面图。
图7A是根据本发明的另一实施方式的光学器件的平面图，以及图7B是沿着图7A的线A-A截取的光学器件的截面图。
图8A是根据本发明的另一实施方式的光学器件的平面图，以及图8B是沿着图8A的线A-A截取的光学器件的截面图。
具体实施方式
在下文中，将参照附图详细描述本发明的优选实施方式。
图2是根据本发明的实施方式通过用于光学器件的基板制备的光学器件的截面图。如图2中所示，根据本发明的实施方式的光学器件包括：光学元件基板110-1，其位于光学器件的中心处并且安装有多个光学元件160；以及一对电极基板120-1，其以装配方式连接至光学元件基板110-1的两侧并且充当光学器件的电极，即，阳极和阴极。
如上所述，光学元件基板110-1可以由金属板形成，金属板由具有高导热性的金属制成，例如，铝（Al）、镁（Mg）、铜（Cu）或铁（Fe）或其合金，以快速地消散光学元件160产生的热。此外，每个电极基板120-1可以具有由合成树脂制成的主体，该合成树脂具有良好的可处理性和可加工性，例如，聚合物、塑料或其合成物，原因在于电极基板120-1与光学元件基板110-1相比，不需要卓越的散热性能。因此，图2示出了具有由合成树脂制成的主体的电极基板120-1。
同时，在本发明中，为了加强光学元件基板110-1和电极基板120-1之间的附接，光学元件基板110-1的两个侧面设置有突出物112，并且每个电极基板120-1的一个侧面设置有凹槽122（参照虚线圈“A”中的结构），因此光学元件基板110-1通过将突出物112装配在凹槽122中附接至每个电极基板120-1。这种情况下，突出物112和凹槽122可以交叉地分别形成在光学元件基板110-1和电极基板120-1的整个或部分侧面上。同时，如图2的虚线圈“B”所示，每个电极基板120-1可以设置在其一个侧面设置有突出物123，而光学元件基板110-1可以在其两个侧面设置有凹槽113。此外，光学元件基板110-1可以在其每个侧面垂直设置有两个或更多个突出物，而每个电极基板120-1可以在其一个侧面设置有两个或更多个凹槽。此外，光学元件基板110-1可以在其每个侧面垂直设置有两个或更多个凹槽，而每个电极基板120-1可以在其一个侧面设置有两个或更多个突出物。与以上相比，光学元件基板110-1可以在其一个侧面设置有突出物，并且可以在其另一个侧面设置有凹槽。突出物112和凹槽122可以通过加工工艺形成。
同时，如图2中所示，当电极基板120-1的主体由合成树脂制成时，传导层134必须形成在电极基板主体的整个或部分上表面上，从而使得该主体充当电极基板120-1。同时，可以将光学元件160直接附接至金属板的上表面，该金属板构成将安装在光学元件基板110-1上的光学元件基板110-1，但是，在这种情况下，入射在光学元件基板110-1上表面上的光的反射率可能会由于干涉而被降低，所以优选的是具有高的光学反射率的镀层132形成在光学元件基板110-1的上表面上。镀层132可以由具有高光学反射率的银（Ag）制成。
在本发明中，为了防止光学元件基板110-1被设置有垂直绝缘层，光学元件基板110-1上设置有与该光学元件基板110-1电绝缘的至少一个水平绝缘层140，并且该水平绝缘层140上设置有桥垫150，其用于电连接两个相邻的光学元件160。
在这里，水平绝缘层140可以通过使用粘合剂或热压将合成树脂片附接至光学元件基板110-1上、通过固化液态环氧或硅粘合剂或者通过将陶瓷直接热喷镀在光学元件基板110-1上而形成。在这种情况下，为了增强水平绝缘层140和光学元件基板110-1之间的粘合，可以在使光学元件基板110-1的表面粗糙的预处理之后，形成水平绝缘层140。同时，为了防止水平绝缘层140破坏光学元件基板110-1的光学反射效率，如果可能，可以减小水平绝缘层140的尺寸。
桥垫150可以由具有良好导电性、光反射率和与引线的粘合性的金属或合金片形成，其选自以下：金（Au）、银（Ag）、铜（Cu）、铝（Al）、镍（Ni）及其合金。优选地，桥垫150可以通过使用粘合剂将银（Ag）片附接在水平绝缘层140上形成。桥垫150可以具有各种形状，例如，圆形、四边形等。
此外，桥垫150可以通过以下步骤形成：使用喷溅、电镀或无电镀用金属材料处理硅晶片或者使用电镀或无电镀用金属材料处理塑料或FR4板以形成镀层，适当地切割镀层，以及然后使用粘合剂将切割的镀层附接在水平绝缘层140上。此外，可以通过使用丝网印刷将银（Ag）糊状物直接印刷在水平绝缘层140上形成桥垫150。同时，为了增强引线结合的可靠性，可以将无电镀镍（Ni）镀层附加地形成在桥垫150的表面上。优选地，桥垫150的尺寸小于水平绝缘层140的尺寸，从而使得光学元件基板110-1的相邻的镀层132之间的电绝缘充分进行。
同时，在将光学元件基板110-1附接至电极基板120之后，在其上形成单个镀层130。通过机械工艺（例如，切割工艺）或者化学工艺（例如，蚀刻工艺）将该单个镀层130分离成传导层134和镀层132以及一区域，水平绝缘层140将占据该区域，并且然后可以执行后续工艺。
通过上述工艺，完成用于光学器件的基板。在下文中，将光学元件160安装在镀层132上，在镀层132和光学元件160之间通过粘合剂等设置有桥垫150，然后光学元件160通过桥垫150的中间介入用引线彼此电连接。在这种情况下，最左的和最右的光学元件160的各个电极通过引线165电连接至相应的电极基板120-1。在图2中，参考标号“190”表示用于保护光学元件160和引线165的包含透明或荧光材料的密封体，而参考标号“180”表示用于限制液态密封体190的拦坝。
图3是根据本发明的另一实施方式通过用于光学器件的基板制备的光学器件的截面图。在图3中，与图2中部件相同的部件用相同的参考标号表示，并且其详细描述将省略。根据图3中所示的光学器件100-2，电极基板120-2可以由金属板（例如，与光学元件基板110-1的金属板相同的金属板）而不是合成树脂形成。在这种情况下，出于说明电极基板120-2和光学元件基板110-1的目的，必须将具有横向放置盖形的装配型垂直绝缘层124***在这些基板之间，从而使得光学元件基板110-1的突出物112与电极基板120-2的凹槽122装配。这样的装配型垂直绝缘层124由合成树脂制成，并且通过粘合剂附接至光学元件基板110-1和电极基板120-2。同时，可以通过使光学元件基板110-1具有突出物112的侧面或使电极基板120-2具有凹槽122的侧面阳极氧化，或者通过使光学元件基板110-1具有凹槽122的侧面或使电极基板120-2具有突出物112的侧面阳极氧化，使装配型垂直绝缘层与光学元件基板110-1或电极基板120-2成一体。在这里，装配结构与图2中所示的装配结构相同。
图4是通过用于图2的光学器件的局部修改的基板制备的光学器件的截面图，以及图5是通过用于图3的光学器件的局部修改的基板制备的光学器件的截面图。在图4和5中，与图2和3中部件相同的部件用相同的参考标号表示，并且其详细描述将省略。在图4和5所示的光学器件（100-3和100-4）中，为了在桥垫150的上表面由于水平绝缘层140的厚度而高于镀层132的上表面时，防止光学反射率降低，将安装凹槽形成光学元件基板110-2的上部中直至与水平绝缘层140的厚度对应的深度，并且然后将该水平绝缘层140安装在该安装凹槽中。因此，即使在桥垫150布置在水平绝缘层140上时，桥垫150的上表面也与镀层132的上表面齐平或者比镀层132的上表面低，这样防止光学反射率降低。在图2至5中，为了方便，示出了每个具有两个光学元件160的光学器件，也可以制备每个具有两个或更多个光学元件160的光学器件。此外，当如在图6中所示的下述光学器件中一样，光学元件之间的距离足够大以至不能够执行芯片至芯片引线结合时，可以优选地应用图2至5中所示的光学器件。
图6是在不***桥垫的情况下通过芯片对芯片引线结合光学元件的电极制备的光学器件的截面图。在图6中，与图2至5中部件相同的部件用相同的参考标号表示，并且其详细描述将省略。在图6所示的光学器件100-5中，该光学器件100-5不包括桥垫，所以其不需要水平绝缘层，并且因此镀层可以形成在光学元件基板的整个区域上。根据该实施方式的光学器件可以应用于需要保持光学元件之间的间隔狭窄的光学器件。在图6中，参考标号“195”表示用于将从光学元件发出的光聚焦的透镜（凸透镜）（在发散光的情况下：凹透镜）。这样的透镜可以直接应用于图7和8所示的下述的光学器件以及图2至5所示的上述光学器件。
图7A是根据本发明的另一实施方式的光学器件的平面图，以及图7B是沿着图7A的线A-A截取的光学器件的截面图。在图7A和7B中，与图2至5中部件相同的部件用相同的参考标号表示，并且其详细描述将省略。如图7A至7B中所示，在根据本发明的实施方式的光学器件100-6中，具有矩形凹槽的单个腔形成在光学元件基板110-3的上部分中，并且该腔中安装有多个光学元件160。在这种情况下，当以倾斜形状形成腔，从而使得腔的壁的上部分的宽度大于其壁的下部分的宽度时，可以提高光学反射率。
同时，在这种配置中，优选的是将密封体190充入该腔中直至该腔的上表面的水平面。在这种情况下，可以在其间包括装配型垂直绝缘层124的光学元件基板110-3和电极基板120-3的部分上设置台阶，从而使得连接至电极基板120-3的引线165嵌入在密封体190中。可以在光学元件基板110-3和电极基板120-3通过装配而附接的情况下，通过按压、切割或蚀刻工艺形成腔。与此不同，在光学元件基板110-3和电极基板120-3彼此分离的情况下形成腔和台阶，然后通过装配使光学元件基板110-3和电极基板120-3附接。
图8A是根据本发明的另一实施方式的光学器件的平面图，以及图8B是沿着图8A的线A-A截取的光学器件的截面图。在图8A和8B中，与图2至5中部件相同的部件用相同的参考标号表示，并且其详细描述将省略。如图8A和8B中所示，在根据本发明的实施方式的光学器件100-7中，为了进一步增加光学反射率，将光学元件安装在相应的腔中，每个腔由具有斜面的凹槽形成，该斜面的上部分宽并且其下部分窄。因此，光学元件基板设置有多个腔。同时，在该实施方式中，在腔之间形成通道型凹槽（channel groove），每个通道型凹槽具有比腔小的宽度，在每个通道型凹槽中形成水平绝缘层，并且在水平绝缘层上布置桥垫，因而腔的上平面与桥垫的上表面齐平，从而增加光学反射率。
在图2至8中，除非特别解释，否则相同的材料和功能部件用相同的剖面线表示。
在本发明的技术思想下，可以对根据本发明的用于光学器件的基板进行各种修改，而不限于上述实施方式。也可以将根据本发明的用于光学器件的基板用于背光单元的光源，其中多个光学元件以串联连接的方式连续排成一线。
<附图中的参考标号说明>
100-1～100-7：光学器件
110-1～110-4：光学元件基板
112：突出物
120-1～120-4：电极基板
122：凹槽
124：装配型垂直绝缘层
130：镀层
132：镀层
134：传导层
140：水平绝缘层
150：桥垫
160：光学元件
165：引线
180：密封体拦坝
190：密封体
195：透镜

Claims (10)

1.一种用于光学器件的基板，其包括：
光学元件基板，其由金属板制成并且其中设置有多个光学元件；
一对电极基板，其由绝缘材料制成以在其上表面的至少一部分上形成传导层，该对电极基板分别连接至光学元件基板的两个侧表面，并且引线结合至光学元件的电极；以及
装配装置，其形成在电极基板和光学元件基板的侧表面上，以装配光学元件基板和电极基板。
2.根据权利要求1所述的用于光学器件的基板，其中光学元件基板设置有腔，该腔包括矩形凹槽，该矩形凹槽中安装有多个光学元件。
3.根据权利要求1所述的用于光学器件的基板，其中光学元件基板设置有多个腔，每个腔包括凹槽，该凹槽中安装有光学元件。
4.一种用于光学器件的基板，其包括：
光学元件基板，其由金属板制成并且其中设置有多个光学元件；
一对电极基板，其由金属材料制成，分别连接至光学元件基板的两个侧表面，并且引线结合至光学元件的电极；
装配装置，其形成在电极基板和光学元件基板的侧表面上，以装配光学元件基板和电极基板；以及
装配型垂直绝缘层，其***在光学元件基板和电极基板之间，以便连接至装配装置。
5.根据权利要求4所述的用于光学器件的基板，其中装配型垂直绝缘层通过使光学元件基板和电极基板的包括装配装置的侧表面阳极氧化而形成。
6.根据权利要求5所述的用于光学器件的基板，其中光学元件基板设置有腔，该腔包括矩形凹槽，该矩形凹槽中安装有多个光学元件。
7.根据权利要求5所述的用于光学器件的基板，其中光学元件基板设置有多个腔，每个腔包括凹槽，该凹槽中安装有光学元件。
8.根据权利要求1至7中任一项所述的用于光学器件的基板，其中光学元件基板包括形成在其上表面上的镀层。
9.根据权利要求8所述的用于光学器件的基板，还包括：
水平绝缘层，其形成在光学元件基板的至少一个镀层已去除的区域上，以与镀层电连接；以及
桥垫，其布置在水平绝缘层上以允许光学元件的电极通过引线电连接。
10.根据权利要求9所述的用于光学器件的基板，其中水平绝缘层形成在凹槽中，该凹槽形成在光学元件基板的镀层已去除的区域中。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107078131A (zh) * 2014-11-12 2017-08-18 欧司朗光电半导体有限公司 光电子半导体组件和用于制造光电子半导体组件的方法
CN110959199B (zh) * 2017-08-28 2023-12-15 奥斯兰姆奥普托半导体有限责任公司 光电子半导体器件和用于形成光电子半导体器件的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058924A (ja) * 1998-08-06 2000-02-25 Shichizun Denshi:Kk 表面実装型発光ダイオード及びその製造方法
JP2002335019A (ja) * 2001-03-05 2002-11-22 Nichia Chem Ind Ltd 発光装置
CN101252164A (zh) * 2007-02-22 2008-08-27 夏普株式会社 表面安装型发光二极管及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058924A (ja) * 1998-08-06 2000-02-25 Shichizun Denshi:Kk 表面実装型発光ダイオード及びその製造方法
JP2002335019A (ja) * 2001-03-05 2002-11-22 Nichia Chem Ind Ltd 発光装置
CN101252164A (zh) * 2007-02-22 2008-08-27 夏普株式会社 表面安装型发光二极管及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107078131A (zh) * 2014-11-12 2017-08-18 欧司朗光电半导体有限公司 光电子半导体组件和用于制造光电子半导体组件的方法
CN107078131B (zh) * 2014-11-12 2019-04-23 欧司朗光电半导体有限公司 光电子半导体组件和用于制造光电子半导体组件的方法
CN110959199B (zh) * 2017-08-28 2023-12-15 奥斯兰姆奥普托半导体有限责任公司 光电子半导体器件和用于形成光电子半导体器件的方法

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