CN103616681A - Radar imaging method based on Zynq-series FPGA - Google Patents
Radar imaging method based on Zynq-series FPGA Download PDFInfo
- Publication number
- CN103616681A CN103616681A CN201310648828.3A CN201310648828A CN103616681A CN 103616681 A CN103616681 A CN 103616681A CN 201310648828 A CN201310648828 A CN 201310648828A CN 103616681 A CN103616681 A CN 103616681A
- Authority
- CN
- China
- Prior art keywords
- data
- radar
- signal
- distance
- kernel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9004—SAR image acquisition techniques
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
Landscapes
- Engineering & Computer Science (AREA)
- Remote Sensing (AREA)
- Radar, Positioning & Navigation (AREA)
- Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses a radar imaging method based on a Zynq-series FPGA. The method mainly solves the problems that an existing imaging system is complex in structure, long in development period and not transportable. The method includes the implementation steps that data required for radar imaging are generated with Matlab software and introduced into Vidado HLS software, and the data undergo pulse compression in the software so as to achieve radar imaging; the progress for achieving radar imaging is optimized, an optimized result is converted into a register transfer level; time sequence simulation is performed on the RTL through Modelsim software so as to meet requirements of a handshaking mechanism; the RTL meeting the requirements of the handshaking mechanism is led out with Vivado HLS software, so that the register transfer level becomes a universal IP core having the radar imaging function; the generated IP core is called in the FPGA, data are input at the input end of the IP core according to the time sequence, radar imaging data are obtained at the output end of the IP core, and therefore radar imaging in the FPGA is completed. According to the method, the structure of the radar imaging system is simplified, the development period is shortened, and the radar imaging system is transportable.
Description
Technical field
The invention belongs to digital signal processing technique field, relate to and a kind ofly by Zynq Series FPGA, realize radar imaging method, can be widely used in the fields such as target following, remote sensing, Video processing.
Background technology
Synthetic-aperture radar SAR has distance and bearing two dimension high resolving power, can make high-resolution two-dimensional imaging to scene.Can be round-the-clock, round-the-clock, target detected and locate at a distance, play an important role in a lot of fields.The most basic step of radar imagery algorithm is exactly pulse compression, when transponder pulse, pulse is narrower, signal band is wider, but launch very narrow pulse, have very high peak power, practical difficulty is very large, conventionally all adopt broadband signal wide when large, after reception, by pulse compression, obtain burst pulse.
In existing technology, major part is all to go to realize radar imagery with DSP, in the signal-processing board card of up-to-date making, eight core DSP of the up-to-date release of main Shi Yong TI company go to realize radar imagery, although this method development efficiency is high, realizes mass ratio poor, processing speed is slow, and system architecture is complicated, power consumption is very large.There is realizing with FPGA the method for radar imagery for this reason, for example Jiang Wei China in 2009 describes how with FPGA, to realize orientation pulse compression at the interim paper < < delivering of < < electronics science > > magazine the 22nd volume the 10th in detail in the design > > based on FPGA radar imagery orientation pulse compression system, although this method has also obtained good effect, but the implementation procedure complexity of the method is loaded down with trivial details, resource utilization is not high, and necessarily require developer to possess very abundant RTL commissioning experience, need to carry out the effect that debugging repeatedly just can obtain providing in document to FPGA program, this makes the construction cycle very long, and the method does not possess portability, can only be applicable to specific FPGA.
Summary of the invention
The object of the invention is to the deficiency for prior art, a kind of method that realizes radar imagery by Zynq Series FPGA is provided, to simplify signal processing system structure, shorten the construction cycle, and realize its portability.
For achieving the above object, implement as follows:
(1) the carrier frequency f of input radar signal
c, pulse width T and frequency modulation width B, target is to the vertical range R of radar, in Matlab software, generate respectively the echo signal data, distance of radar to the data of adaptation function and the data of azimuth match function, and these three data are left in respectively in three different .dat files;
(2) the Vivado HLS software carrying by Zynq Series FPGA is read three data in .dat file, and by the echo signal data of reading, to adaptation function data and azimuth match function data, carry out pulse compression with the distance of reading respectively, to realize the radar imagery in Vivado HLS software;
(3) to realize the process of radar imagery in Vivado HLS software, be optimized, make that its resource utilization is minimum, throughput is maximum, processing speed is the fastest, and be converted into the Method at Register Transfer Level RTL that can be loaded into FPGA;
(4) the Method at Register Transfer Level RTL generating in step (3) is carried out to sequential emulation, whether the sequential that judges Method at Register Transfer Level RTL meets handshake mechanism, if met, execution step (5), otherwise, return to step (3) process of radar imagery is optimized again, until the sequential of Method at Register Transfer Level RTL meets handshake mechanism;
(5) with Vivado HLS software, with the form of IP-XACT, derive the Method at Register Transfer Level RTL that meets handshake mechanism, Method at Register Transfer Level RTL is become and there is the universal I P core of radar imagery function, then IP kernel is added in the IP kernel bank of Zynq Series FPGA;
(6) be invoked at the IP kernel in FPGA, and at the input end of IP kernel, input radar echo signal data, distance to adaptation function data, azimuth match function data according to sequential, at the output terminal of IP kernel, obtain the data of radar imagery, complete the radar imagery in FPGA.
The present invention compared with prior art has the following advantages:
The first, first extendible Zynq Series FPGA of the whole world that the present invention adopts company of match SEL to release, this novel FPGA closely integrates complete arm processor SOC (system on a chip) SoC and 28nm low-power consumption FPGA (Field Programmable Gate Array).Zynq Series FPGA has abundant internal resource and external interface, and processing speed is fast, and dirigibility is good, low in energy consumption.
Second, the higher synthesis instrument Vivado HLS that the present invention utilizes Zynq Series FPGA to carry, directly the radar imagery code of realizing is converted to the Method at Register Transfer Level RTL that can be loaded into FPGA in Vivado HLS software, and this process development personnel do not need to understand any knowledge about Method at Register Transfer Level RTL.This has saved, and developer manually writes, the complicated processes of debug registers transmitting stage RTL, greatly shortens the construction cycle, and Performance Ratio realizes same algorithm and improve 40 times in multi-core DSP, and power consumption is also less.
The 3rd, the present invention is due to the radar imagery code of realizing in Vivado HLS software is optimized, its performance is close with the Method at Register Transfer Level RTL manually writing, reduced resource utilization, improved throughput, but the method than the Method at Register Transfer Level RTL manually writing is simple, and greatly improved development efficiency.
The 4th, the universal I P core with radar imagery function that the present invention derives with the form of IP-XACT with Vivado HLS software, is not only applicable to Zynq Series FPGA, but also is applicable to the FPGA of other companies of match SEL, has extraordinary portability.
Accompanying drawing explanation
Fig. 1 is the general flow chart of realizing of the present invention;
When being Optimized code of the present invention, Fig. 2 makes the data stream dataflow pattern diagram that processing speed is fast adopted;
Fig. 3 is radar imagery figure of the present invention;
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
With reference to Fig. 1, specific embodiment of the invention step is as follows:
Step 1. generates the required data of radar imagery in Matlab software.
(1a) by the carrier frequency f of radar signal
c, pulse width T, frequency modulation width B, carrier aircraft speed V and target be to the vertical range R of radar, inputs to commercial Matlab software, by this Software Create radar emission signal, be:
s
t(t
1)＝a
r(t
1)*exp(jπK(t
1)
2)，
Wherein, t
1for fast time, a
r(t
1) be the envelope of radar emission signal,
frequency modulation rate for radar emission signal;
(1b) according to radar echo signal, be the characteristic of the delay of radar emission signal, the expression formula of radar echo signal slow time domain in m-orientation when distance is fast is:
Wherein, t
mfor slow time, a
r(.) and a
athe distance that (.) is respectively radar echo signal is to window function and orientation to window function,
centered by wavelength corresponding to frequency, c is the light velocity, exp (.) represents to get exponent arithmetic;
(1c), according to radar echo signal, show that the distance of radar echo signal is to adaptation function s
r(t
1) be radar emission signal s
t(t
1) conjugation symmetrical,
(1d), according to radar echo signal, show that the azimuth match function of radar echo signal is:
s
a(t
m;R)＝a
a(t
m)*exp(-jπK
m(R)(t
m)
2)，
Wherein,
For doppler frequency rate;
(1e) according to the expression formula s (t of above-mentioned radar echo signal slow time domain in m-orientation when distance is fast
1, t
m; R), the distance of radar echo signal is to the expression formula s of adaptation function
r(t
1), the expression formula s of the azimuth match function of radar echo signal
a(t
m; R), in Matlab software, generate radar echo signal data d1, distance to adaptation function data d2, azimuth match function data d3, and these three data that generate are left in respectively in three different .dat files.
Step 2. realizes radar imagery in Vivado HLS software.
(2a) the Vivado HLS software carrying by Zynq Series FPGA is read three data in .dat file;
(2b) the radar echo signal data d1 reading is carried out to distance to Fast Fourier Transform (FFT), the distance of reading is carried out to Fast Fourier Transform (FFT) to adaptation function data d2, and by the result conjugate multiplication of both Fast Fourier Transform (FFT)s, again its product is carried out to distance to inverse fast fourier transform, obtain the distance of radar echo signal to pulse compression data d4;
(2c) distance of radar echo signal is carried out to orientation to Fast Fourier Transform (FFT) to pulse compression data d4, the azimuth match function data d3 reading is carried out to Fast Fourier Transform (FFT), and by the result conjugate multiplication of both Fast Fourier Transform (FFT)s, again its product is carried out to orientation to inverse fast fourier transform, obtain the orientation of radar echo signal to pulse compression data d5.
Through above-mentioned to radar echo signal data d1 carry out distance to orientation to pulse compression, just realized the radar imagery in Vivado HLS software.
The process that step 3. pair realizes radar imagery in Vivado HLS software is optimized.
In order to make to realize in Vivado HLS software, the resource utilization of radar imagery is minimum, throughput is maximum, processing speed is the fastest, need to be optimized the process of imaging, and concrete steps are as follows:
(3a) limit the use of operational character, force to make program sharing multiplier, so that operational character usage quantity is minimum.Multiplying is in radar imagery program, to use maximum computings, multiplying in FPGA, to need to utilize multiplier to realize, but the multiplier resources of FPGA is very in short supply, thus force to make program sharing multiplier, so that operational character usage quantity is minimum.In Vivado HLS software, input instruction config_bind min_op mul, just can realize the object that makes program sharing multiplier, wherein config_bind represents to arrange binding, and min_op represents to make operational character usage quantity minimum, and mul represents it is multiplying operator;
(3b) launch the loop statement in radar imagery program completely, realize and execute all circulations within a clock period.Utilize in Vivado HLS software and there is the function that the loop statement in program is launched, according to the degree of launching, can be divided into completely and launch, partly launch and do not launch three classes.For making throughput reach maximum, in the present invention the loop statement in program is launched completely, in Vivado HLS software, input launches instruction set_directive_unroll completely, just can complete loop statement and launch completely, realizes and execute all circulations within a clock period.
(3c) radar imagery programming is become to pattern of traffic, so that the function executed in parallel in program.Utilizing FPGA is this feature of device of complete parallel, and programming is become to data stream dataflow pattern, and the principle of work of data stream dataflow pattern as shown in Figure 3.If usage data does not flow dataflow pattern, radar imagery program is exactly that order is carried out, as shown in figure (2a), three function f unA, funB, funC is that order is carried out, after funA function executes, start to carry out funB function, carry out again funC function after executing funB function; But the previous function such as in data stream dataflow pattern, just do not need to execute completely, only need to wait previous function to carry out after the clock period, next function just can start to carry out, and has so just greatly shortened the stand-by period, makes processing speed the fastest, as shown in figure (2b), three function f unA, funB, funC is executed in parallel, as long as can start to carry out funB function while waiting funA function to have output, just start to carry out funC function while waiting funB function to have output.Input traffic instruction set_directive_dataflow in Vivado HLS software, just can complete a radar imagery programming is data stream dataflow pattern.
Step 4. couple Method at Register Transfer Level RTL carries out sequential emulation.
In the present invention, use professional emulation tool Modelsim software to carry out sequential emulation to Method at Register Transfer Level RTL, judge whether the sequential of Method at Register Transfer Level RTL meets handshake mechanism.Described handshake mechanism refers to that transmit leg is before sending data to take over party, must first send out a request signal to take over party, and whether inquiry take over party has been ready to receive data; If take over party has been ready to receive data, return to a confirmation signal to transmit leg; Transmit leg just starts to send data after receiving the confirmation signal.If the sequential of Method at Register Transfer Level RTL meets handshake mechanism, perform step (5), otherwise, return to step (3) radar imagery process is re-started to optimization, until the sequential of Method at Register Transfer Level RTL meets handshake mechanism.
Step 5. derives the Method at Register Transfer Level RTL through sequential emulation.
(5a) with Vivado HLS software, with the form of IP-XACT, derive Method at Register Transfer Level RTL, Method at Register Transfer Level RTL is become have the universal I P core of radar imagery function, this IP kernel comprises: clock signal sys_clk, reset signal sys_reset, commencing signal ap_start, settling signal ap_done, idle signal ap_idle, radar echo signal data echo_data, distance is to adaptation function data rg_data, azimuth match function data az_data, output data ap_return;
(5b) above-mentioned IP kernel is added in the IP kernel bank of Zynq Series FPGA, the form of derivation is not only confined to IP-XACT form, can also be the Pcore form that is applicable to embedded system, and the System Generator form that is applicable to Matlab software.
Step 6. is called IP kernel in FPGA.
Sequential is called in setting, is about to radar imagery in FPGA and is divided into two stages and carries out;
First stage: at the clock signal sys_clk of IP kernel rising edge, if commencing signal ap_start is high level, start to input radar echo signal data echo_data, distance to adaptation function data rg_data, azimuth match function data az_data to IP kernel simultaneously, on the contrary inoperation;
Subordinate phase: after a clock period, commencing signal ap_start becomes low level, then according to the idle signal ap_idle in IP kernel, judge whether IP kernel finishes the work:
If idle signal ap_idle is low level, show that IP kernel works;
If idle signal ap_idle is high level, and settling signal ap_done is also high level, shows that IP kernel finishes the work, and now the output data ap_return of IP kernel is the data of final radar imagery.
Effect of the present invention by experiment result further embodies.
1. experiment condition
If there are five point targets in scene, and they are identical to electromagnetic reflection potential, and radar is positive side-looking work, does not consider the impact of range migration;
2. experiment content
Method of the present invention is carried out radar imagery to five point targets, and result is as Fig. 3.Fig. 3 shows that five point targets are very clear.Visible, utilize Vivado HLS software in Znyq Series FPGA, to realize radar imagery and can meet the demands completely, and avoided manually writing, the complicated processes of debug registers transmitting stage RTL, greatly shorten the construction cycle.
Claims (5)
1. the radar imaging method based on Zynq Series FPGA, comprises the steps:
(1) the carrier frequency f of input radar signal
c, pulse width T and frequency modulation width B, target is to the vertical range R of radar, in Matlab software, generate respectively the echo signal data, distance of radar to the data of adaptation function and the data of azimuth match function, and these three data are left in respectively in three different .dat files;
(2) the Vivado HLS software carrying by Zynq Series FPGA is read three data in .dat file, and by the echo signal data of reading, to adaptation function data and azimuth match function data, carry out pulse compression with the distance of reading respectively, to realize the radar imagery in Vivado HLS software;
(3) to realize the process of radar imagery in Vivado HLS software, be optimized, make that its resource utilization is minimum, throughput is maximum, processing speed is the fastest, and be converted into the Method at Register Transfer Level RTL that can be loaded into FPGA;
(4) the Method at Register Transfer Level RTL generating in step (3) is carried out to sequential emulation, whether the sequential that judges Method at Register Transfer Level RTL meets handshake mechanism, if met, execution step (5), otherwise, return to step (3) process of radar imagery is optimized again, until the sequential of Method at Register Transfer Level RTL meets handshake mechanism;
(5) with Vivado HLS software, with the form of IP-XACT, derive the Method at Register Transfer Level RTL that meets handshake mechanism, Method at Register Transfer Level RTL is become and there is the universal I P core of radar imagery function, then IP kernel is added in the IP kernel bank of Zynq Series FPGA;
(6) be invoked at the IP kernel in FPGA, and at the input end of IP kernel, input radar echo signal data, distance to adaptation function data, azimuth match function data according to sequential, at the output terminal of IP kernel, obtain the data of radar imagery, complete the radar imagery in FPGA.
2. the radar imaging method based on Zynq Series FPGA according to claim 1, wherein step (2) described by the echo signal data of reading, to adaptation function data and azimuth match function data, carry out pulse compression with the distance of reading respectively, carry out as follows:
(2a) echo signal data of reading is carried out to distance to Fast Fourier Transform (FFT), the distance of reading is carried out to Fast Fourier Transform (FFT) to adaptation function data, by the result conjugate multiplication of both Fast Fourier Transform (FFT)s, again its product is carried out to distance to inverse fast fourier transform, obtain the distance of echoed signal to pulse compression data;
(2b) distance of echoed signal is carried out to orientation to Fast Fourier Transform (FFT) to pulse compression data, the azimuth match function data of reading is carried out to Fast Fourier Transform (FFT), by the result conjugate multiplication of both Fast Fourier Transform (FFT)s, again its product is carried out to orientation to inverse fast fourier transform, obtain the orientation of echoed signal to pulse compression data.
3. the radar imaging method based on Zynq Series FPGA according to claim 1, what wherein step (3) was described being optimized realize the process of radar imagery in Vivado HLS software, carries out as follows:
(3a) by share multiplier, reduce operational character usage quantity, make resource utilization minimum;
(3b), by the loop statement in program is launched, make it within a clock period, just can execute all circulations, to reach throughput maximum;
(3c), by being data stream dataflow pattern program setting, make the program can executed in parallel, so that processing speed is the fastest.
4. the radar imaging method based on Zynq Series FPGA according to claim 1, the IP kernel in wherein said step (5), it comprises following signal:
Clock signal sys_clk,
Reset signal sys_reset,
Commencing signal ap_start,
Settling signal ap_done,
Idle signal ap_idle,
Radar echo signal data echo_data,
Distance to adaptation function data rg_data,
Azimuth match function data az_data,
Output data ap_return.
5. the radar imaging method based on Zynq Series FPGA according to claim 1, the sequential in wherein said step (6), comprises two stages:
First stage: at the rising edge of clock signal sys_clk, if commencing signal ap_start is high level, start simultaneously to input radar echo signal data, distance to adaptation function data, azimuth match function data to IP kernel;
Subordinate phase: after a clock period, commencing signal ap_start becomes low level, according to idle signal ap_idle, judges whether IP kernel finishes the work:
If idle signal ap_idle is low level, show that IP kernel works;
If idle signal ap_idle is high level and settling signal ap_done is also high level, show that IP kernel finished the work, the value of now exporting data ap_return is the data of final radar imagery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310648828.3A CN103616681B (en) | 2013-12-04 | 2013-12-04 | Radar imaging method based on Zynq-series FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310648828.3A CN103616681B (en) | 2013-12-04 | 2013-12-04 | Radar imaging method based on Zynq-series FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103616681A true CN103616681A (en) | 2014-03-05 |
| CN103616681B CN103616681B (en) | 2015-07-15 |
Family
ID=50167385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310648828.3A Active CN103616681B (en) | 2013-12-04 | 2013-12-04 | Radar imaging method based on Zynq-series FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103616681B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105534546A (en) * | 2015-12-30 | 2016-05-04 | 哈尔滨工业大学 | Ultrasonic imaging method based on ZYNQ FPGAs |
| CN106556831A (en) * | 2016-10-21 | 2017-04-05 | 西安电子科技大学 | GRADIENT PROJECTION METHODS based on FPGA |
| CN106844900A (en) * | 2016-12-31 | 2017-06-13 | 上海交通大学 | The erection method of electromagnetic transient simulation system |
| CN108885263A (en) * | 2016-03-21 | 2018-11-23 | 威力登激光雷达有限公司 | With the duplicate 3D imaging based on LIDAR of variable pulse |
| CN108920825A (en) * | 2018-07-03 | 2018-11-30 | 山东芯革电子科技有限公司 | A kind of SoC visual data manager based on IP kernel |
| CN109444886A (en) * | 2018-12-30 | 2019-03-08 | 成都汇蓉国科微***技术有限公司 | A kind of parallel computation processing method, system and the medium of Bistatic SAR real time imagery |
| CN109445366A (en) * | 2018-12-27 | 2019-03-08 | 南京胜跃新材料科技有限公司 | A kind of screening test method of FPGA programmable logic resource |
| CN110263470A (en) * | 2019-06-26 | 2019-09-20 | 中国科学院电子学研究所 | STOLT interpolation implementation method and device |
| CN110321581A (en) * | 2019-03-19 | 2019-10-11 | 南京航空航天大学 | A kind of design method of the two-dimensional Fourier transform IP kernel based on HLS |
| CN110412569A (en) * | 2019-07-05 | 2019-11-05 | 中国科学院电子学研究所 | Based on high-level language comprehensive radar imaging method and device |
| CN111337896A (en) * | 2020-03-25 | 2020-06-26 | 上海无线电设备研究所 | Method for realizing moving target detection acceleration |
| CN112924966A (en) * | 2021-01-25 | 2021-06-08 | 电子科技大学 | Terahertz video SAR real-time processing system |
| CN113281733A (en) * | 2021-05-19 | 2021-08-20 | 天津大学 | ZYNQ-based radar speed and distance measuring system and method |
| CN113434457A (en) * | 2021-06-29 | 2021-09-24 | 广州极飞科技股份有限公司 | High output frame rate data processing method, device, equipment, system and storage medium |
| CN113434458A (en) * | 2021-06-29 | 2021-09-24 | 广州极飞科技股份有限公司 | High output frame rate data processing method, device, equipment, system and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103197317A (en) * | 2013-03-26 | 2013-07-10 | 西安电子科技大学 | Synthetic aperture radar (SAR) imaging method based on field programmable gate array (FPGA) |
-
2013
- 2013-12-04 CN CN201310648828.3A patent/CN103616681B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103197317A (en) * | 2013-03-26 | 2013-07-10 | 西安电子科技大学 | Synthetic aperture radar (SAR) imaging method based on field programmable gate array (FPGA) |
Non-Patent Citations (3)
| Title |
|---|
| 姜玮华 等: "基于FPGA雷达成像方位脉冲压缩***的设计", 《电子科技》, vol. 22, no. 10, 31 December 2009 (2009-12-31), pages 36 - 39 * |
| 李刚 等: "基于FPGA实现实时SAR成像***设计", 《火控雷达技术》, vol. 36, 31 December 2007 (2007-12-31), pages 21 - 25 * |
| 杨磊 等: "高效机载SAR实时成像处理***设计", 《电路与***学报》, vol. 18, no. 1, 28 February 2013 (2013-02-28) * |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105534546B (en) * | 2015-12-30 | 2018-09-07 | 哈尔滨工业大学 | A kind of ultrasonic imaging method based on ZYNQ Series FPGAs |
| CN105534546A (en) * | 2015-12-30 | 2016-05-04 | 哈尔滨工业大学 | Ultrasonic imaging method based on ZYNQ FPGAs |
| CN108885263A (en) * | 2016-03-21 | 2018-11-23 | 威力登激光雷达有限公司 | With the duplicate 3D imaging based on LIDAR of variable pulse |
| CN108885263B (en) * | 2016-03-21 | 2024-02-23 | 威力登激光雷达有限公司 | LIDAR-based 3D imaging with variable pulse repetition |
| CN106556831A (en) * | 2016-10-21 | 2017-04-05 | 西安电子科技大学 | GRADIENT PROJECTION METHODS based on FPGA |
| CN106844900A (en) * | 2016-12-31 | 2017-06-13 | 上海交通大学 | The erection method of electromagnetic transient simulation system |
| CN108920825A (en) * | 2018-07-03 | 2018-11-30 | 山东芯革电子科技有限公司 | A kind of SoC visual data manager based on IP kernel |
| CN109445366B (en) * | 2018-12-27 | 2020-10-13 | 南京市梵林科技有限公司 | FPGA programmable logic resource screening and testing method |
| CN109445366A (en) * | 2018-12-27 | 2019-03-08 | 南京胜跃新材料科技有限公司 | A kind of screening test method of FPGA programmable logic resource |
| CN109444886A (en) * | 2018-12-30 | 2019-03-08 | 成都汇蓉国科微***技术有限公司 | A kind of parallel computation processing method, system and the medium of Bistatic SAR real time imagery |
| CN110321581A (en) * | 2019-03-19 | 2019-10-11 | 南京航空航天大学 | A kind of design method of the two-dimensional Fourier transform IP kernel based on HLS |
| CN110263470A (en) * | 2019-06-26 | 2019-09-20 | 中国科学院电子学研究所 | STOLT interpolation implementation method and device |
| CN110412569A (en) * | 2019-07-05 | 2019-11-05 | 中国科学院电子学研究所 | Based on high-level language comprehensive radar imaging method and device |
| CN110412569B (en) * | 2019-07-05 | 2023-06-23 | 中国科学院电子学研究所 | Radar imaging method and device based on high-level language synthesis |
| CN111337896A (en) * | 2020-03-25 | 2020-06-26 | 上海无线电设备研究所 | Method for realizing moving target detection acceleration |
| CN112924966A (en) * | 2021-01-25 | 2021-06-08 | 电子科技大学 | Terahertz video SAR real-time processing system |
| CN112924966B (en) * | 2021-01-25 | 2022-04-22 | 电子科技大学 | Terahertz video SAR real-time processing system |
| CN113281733A (en) * | 2021-05-19 | 2021-08-20 | 天津大学 | ZYNQ-based radar speed and distance measuring system and method |
| CN113434457A (en) * | 2021-06-29 | 2021-09-24 | 广州极飞科技股份有限公司 | High output frame rate data processing method, device, equipment, system and storage medium |
| CN113434458A (en) * | 2021-06-29 | 2021-09-24 | 广州极飞科技股份有限公司 | High output frame rate data processing method, device, equipment, system and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103616681B (en) | 2015-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103616681B (en) | Radar imaging method based on Zynq-series FPGA | |
| CN108051786A (en) | A kind of broadband target simulator verification platform and verification method | |
| CN103235749A (en) | FPGA-based sensor network SoC proto verification platform | |
| CN102854507B (en) | Imaging method of bistatic SAR (synthetic aperture radar) based on GPU (graphics processing unit) back projection | |
| CN104865560A (en) | UVM-based phased array radar digital beam former module verification method and verification platform thereof | |
| CN100535868C (en) | Real-time bit true simulation development system and method thereof | |
| Bailey et al. | A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance | |
| CN103728616A (en) | Field programmable gate array (FPGA) based inverse synthetic aperture radar (ISAP) imaging parallel envelope alignment method | |
| CN204178184U (en) | Based on the miniaturized high-speed disposable plates of the Doppler radar of DBF | |
| Wen et al. | Design and implementation of real-time SAR echo simulator for natural scene | |
| CN102608600B (en) | FPGA (field-programmable gate array)-based step frequency image splicing implementation method | |
| Wang et al. | Video SAR high-speed processing technology based on FPGA | |
| Burke et al. | Ramp blue: Implementation of a manycore 1008 processor fpga system | |
| CN106556831A (en) | GRADIENT PROJECTION METHODS based on FPGA | |
| Ashworth et al. | First steps in porting the lfric weather and climate model to the fpgas of the euroexa architecture | |
| CN109142868A (en) | Electric harmonic detector | |
| Zhang et al. | Shock wave signal distributed acquisition and data processing technology | |
| Jin et al. | Design of spaceborne SAR imaging processing and fast Verification Based on FPGA | |
| Liang et al. | Research on LFMCW radar velocity ranging optimization system based on FPGA | |
| CN103926567A (en) | High-speed real-time pulse compression algorithm | |
| Fruitwala et al. | Distributed processor for fpga-based superconducting qubit control | |
| CN110263470B (en) | STOLT interpolation realization method and device | |
| Almorin et al. | Model based design of FMCW radar processing systems on FPGA platforms | |
| Rasul et al. | FPGA accelerated computing platform for MATLAB and C/C++ | |
| Peng et al. | Design and implementation of fast SAR echo simulation based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |