CN109444886A - A kind of parallel computation processing method, system and the medium of Bistatic SAR real time imagery - Google Patents
A kind of parallel computation processing method, system and the medium of Bistatic SAR real time imagery Download PDFInfo
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- CN109444886A CN109444886A CN201811646350.XA CN201811646350A CN109444886A CN 109444886 A CN109444886 A CN 109444886A CN 201811646350 A CN201811646350 A CN 201811646350A CN 109444886 A CN109444886 A CN 109444886A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/904—SAR modes
- G01S13/9058—Bistatic or multistatic SAR
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9004—SAR image acquisition techniques
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Abstract
The present invention proposes parallel computation processing method, system and the medium of a kind of highly reliable Bistatic SAR real time imagery, and the method includes receiving the multidiameter delay digital signal from phased antenna；Pre-process the parallel digital signal；Pretreated data are divided into the identical preprocessed data in the road N and are distributed to the road N DSP calculating group, the road N DSP calculating group independently exports a sub-picture；Terminal receives the realtime graphic all exported, carries out images match identifying processing, issues corresponding control instruction according to the result of identification.The defect of reliability, communication efficiency, signal handling capacity etc. is solved under the premise of same computational in real time using the solution of the present invention.
Description
Technical field
The present invention relates to technical field of data processing, and in particular to a kind of highly reliable Bistatic SAR real time imagery it is parallel
Computation processing method, system and medium.
Background technique
SAR (synthetic aperture radar) working principle is the relative motion using radar and target the lesser true day of size
The method of string holes diameter data processing synthesizes the radar in biggish equivalent aerial aperture.The characteristics of synthetic aperture radar is resolution ratio
Height, energy all weather operations can efficiently identify camouflage and penetrate cloak.Biradical synthetic aperture radar uses separation transmitter
And radar imagery is realized in receiver, flight in different platform, using the special flight path of flying platform, obtains Forward-looking SAR
Image.
Although domestic University of Electronic Science and Technology, the National University of Defense technology, Beijing Institute of Technology, Chinese Academy of Sciences electron institute etc.
Scientific research institutions have also carried out related exploratory development in terms of biradical Forward-looking SAR imaging algorithm.More than ten years are passed through by University of Electronic Science and Technology
Research of technique, systematically solve the problems such as system system, theoretical method and key technology of biradical Forward-looking SAR, in 2009
Year for the first time comprehensive system to biradical Forward-looking SAR imaging theory and there are the problem of be discussed, and to two-shipper Forward-looking SAR point
It distinguishes theoretical and optimal operating mode is studied；For the constant equal imaging patterns of change/shifting are moved, propose quadravalence RNLCS,
The series frequency domain imaging algorithm such as Keystone-NLCS, 2D- ω k, efficiently solves biradical Forward-looking SAR coarse migration, close coupling, two
The problems such as tieing up space-variant.However, domestic less in airborne, in terms of missile-borne Bistatic SAR imaging engineering chemistry database, majority is in
The theoretical research of algorithm simulating, the Real Time Imaging Technology of airborne Bistatic SAR when for high speed, ultrahigh speed environment, there are no one
Preferable engineering system schema.
Bistatic SAR digital signal processor is made of FPGA+DSP framework.It is general to use " assembly line " principle Deployment Algorithm
Module, but if it will cause system performance degradations in the presence of the calculation amount task sharply increased.In addition, modules it
Between there are data to rely on by force, as long as the damage of computing module, whole system cannot work.For airborne, missile-borne is biradical
For SAR, all kinds of technical requirements such as reliability, real-time are further increased.
Summary of the invention
In order to solve the above technical problems, the purpose of the present invention is to provide a kind of highly reliable Bistatic SAR real time imageries
Parallel computation processing method, system and medium.Under the premise of same computational in real time, reliability, communication efficiency, signal are solved
The defect of processing capacity etc..
An invention according to the present invention, the present invention provides a kind of parallel meters of highly reliable Bistatic SAR real time imagery
Processing method is calculated, the method includes as follows:
Receive the multidiameter delay digital signal from phased antenna；
Pre-process the parallel digital signal；
Pretreated data are divided into the identical data to be sent in the road N, and send data to corresponding DSP calculating group
In, the road the N DSP calculating group for receiving partial data independently exports a sub-picture；
Terminal receives the realtime graphic all exported, carries out images match identifying processing, issues phase according to the result of identification
The control instruction answered.
With the method for the invention it is preferred to, pretreated data are divided into the identical data to be sent in the road N, it is each
Corresponding identifier is arranged in road data to be sent, when the data distribution to be sent with respective identifier to the road N DSP calculating group
When, the corresponding relationship between record identifier DSP calculating group corresponding with the data of being sent；
After the road the N DSP calculating group is respectively received the pretreated data with identifier information, detection data is
It is no complete, if data are imperfect, identifier information is returned, request data is retransmitted, after receiving identifier information, selection
Data corresponding with identifier, the road the N DSP calculating group for receiving partial data independently export a sub-picture；
With the method for the invention it is preferred to, it is described that pretreated data are divided into the identical preprocessed data point in the road N
It is sent to after the DSP calculating group of the road N, further includes detecting whether to be successfully transmitted data to the road N DSP calculating group, if there is N-2 automatically
Circuit-switched data is not successfully transferred to DSP calculating group, then issues second level warning message, prompts current data sendaisle that open circuit occurs
Risk class is middle rank, needs to arouse attention, if there is N-1 circuit-switched data to be not successfully transferred to DSP calculating group, it is alert to issue level-one
Accuse information, prompt current data sendaisle occur breaking risk class be it is advanced, to handle in time.
With the method for the invention it is preferred to, any data communication and control are not present between N number of DSP calculating group,
It is mutually completely independent operation, each each self-starting calculation procedure of DSP calculating group starts N number of complete data handling procedure altogether；
Parallel computation, each DSP meter inside DSP calculating group are carried out between each DSP computing unit inside each DSP calculating group
The parallel computation for calculating unit includes: that coarse-grained parallelization, middle granularity parallel computation and fine grained parallel calculate；
Coarse-grained parallelization uses pipeline parallel computing technology, and polyalgorithm task is assigned to respectively by assembly line
DSP computing unit；
Middle granularity parallel computation uses parallel distributed computing technique, and the calculating task of super large calculation amount is shared DSP
Multiple DSP computing units in calculating group carry out parallel computation；
Fine grained parallel, which calculates, uses instruction set parallel computing, calculating task is split into instruction set marquis, by instruction
Collection is assigned to different DSP computing units parallel.
With the method for the invention it is preferred to, to following calculation task using coarse grain parallelism dispose: fixed point turn floating-point,
Doppler center is estimated, linear range is walked about correction, matrix transposition；
Granularity in the use of following calculation task is disposed parallel: doppler frequency rate estimation, Phase gradient autofocus, geometry
Correction.
TMS320C6678 is selected in fine grained parallel deployment, using Very Long Instruction Word (VLIW) frame
Structure and SIMD assembly instruction abundant.
According to still another embodiment of the invention, a kind of parallel computation processing system of highly reliable Bistatic SAR real time imagery,
The system comprises FPGA, N number of DSP calculating group and terminal, the FPGA includes FPGA receiving unit, preprocessing module, N number of
SIRO module, the terminal include terminal control module, wherein
FPGA receiving unit, for receiving the multidiameter delay digital signal from phased antenna；
Preprocessing module, for pre-processing the parallel digital signal, and when receiving data retransmission requests, selection with
The corresponding data of identifier, and send data in DSP calculating group corresponding with identifier；
The preprocessing module is also used to detect whether automatically to be successfully transmitted data to the road N DSP calculating group；
SIRO module is distributed to the road N DSP calculating for pretreated data to be divided into the identical data to be sent in the road N
Group；
It is secondary independently to calculate output one after being respectively received pretreated data for the road the N DSP calculating group
Image；
Terminal control module carries out images match identifying processing, according to identification for receiving the realtime graphic all exported
Result issue corresponding control instruction.
The system according to the present invention, it is preferred that the preprocessing module is also used to detect whether automatically successfully to send out data
It send to the road N DSP calculating group, if there is N-2 circuit-switched data to be not successfully transferred to DSP calculating group, issues second level warning message, prompt
It is middle rank that breaking risk class, which occurs, for current data sendaisle, needs to arouse attention, if there is N-1 circuit-switched data to be not successfully transferred
To DSP calculating group, then issue level-one warning message, prompt current data sendaisle occur breaking risk class be it is advanced,
Processing in time；
SIRO module, for pretreated data to be divided into the identical data to be sent in the road N, per data to be sent all the way
Corresponding identifier is set, when the data distribution to be sent with respective identifier to the road N DSP calculating group, record identifier
With the corresponding relationship of the current DSP calculating group for the data of being sent；
The road the N DSP calculating group, after being respectively received the pretreated data with identifier information, detection
Whether data are complete, if data are imperfect, return to identifier information, and request data is retransmitted, and the institute of partial data is received
It states the road N DSP calculating group and independently exports a sub-picture.
The system according to the present invention, it is preferred that the FPGA
It further include data cell, for pretreated multiple data frames to be assembled into data packet according to predetermined order.
The system according to the present invention, it is preferred that any data communication and control are not present between N number of DSP calculating group,
It is mutually completely independent operation, each each self-starting calculation procedure of DSP calculating group starts N number of complete data handling procedure altogether；
Parallel computation, each DSP meter inside DSP calculating group are carried out between each DSP computing unit inside each DSP calculating group
The parallel computation for calculating unit includes: that coarse-grained parallelization, middle granularity parallel computation and fine grained parallel calculate；
Coarse-grained parallelization uses pipeline parallel computing technology, and polyalgorithm task is assigned to respectively by assembly line
DSP computing unit；
Middle granularity parallel computation uses parallel distributed computing technique, and the calculating task of super large calculation amount is shared DSP
Multiple DSP computing units in calculating group carry out parallel computation；
Fine grained parallel, which calculates, uses instruction set parallel computing, calculating task is split into instruction set marquis, by instruction
Collection is assigned to different DSP computing units parallel.
According to still another embodiment of the invention, the present invention also provides a kind of computer readable storage medium, the calculating
Machine readable storage medium storing program for executing is stored with computer program, and the computer program realizes method as described above when being executed by processor
Step.
Using method of the invention, under the premise of same computational in real time, reliability, communication efficiency are solved, at signal
The defect of reason ability etc..
Detailed description of the invention
Fig. 1 is the parallel calculating method flow chart of the highly reliable Bistatic SAR real time imagery of one kind proposed by the present invention；
Fig. 2 is the concurrent computational system frame diagram of the highly reliable Bistatic SAR real time imagery of one kind proposed by the present invention；
Fig. 3 is that FPGA proposed by the present invention arranges multiple data cell schematic diagrames in calculating group；
Fig. 4 is parallel computation overall process schematic diagram proposed by the present invention；
Fig. 5 is Distributed Parallel Computing Model schematic diagram of the present invention；
Specific embodiment
A specific embodiment of the invention is explained in detail below in conjunction with attached drawing.
As illustrated in fig. 1 and 2, this gives a kind of parallel computation processing of highly reliable Bistatic SAR real time imagery
Method, the method includes as follows:
In the present invention, the system composition of this programme includes FPGA, multiple DSP calculating groups, high speed interconnection.Wherein,
FPGA selects Xilinx company Virtex-7 series；DSP selects TI company's T MS320C6678；High speed interconnection can be selected
SRIO link, HyperLink link, PCIE link etc..
FPGA unit
The signal output of phased array antenna is connect with FPGA；
The N number of SRIO module of FPGA exampleization, connects with N number of DSP calculating group respectively；
DSP calculating group
DSP calculating group is made of N piece TI company's T MS320C6678；
It is connected in DSP calculating group with hyperlink；
The output of each DSP calculating group is connect with terminal；
Terminal control
Specifically, FPGA receives the multidiameter delay digital signal from phased antenna；
The multidiameter delay digital signal received is pre-processed, and obtains pretreated data；
Pretreated data are divided into the identical data to be sent in the road N, corresponding mark is set per data to be sent all the way
Know symbol, when the data distribution to be sent with respective identifier to the road N DSP calculating group, record identifier and the number of being sent
According to current DSP calculating group corresponding relationship；
In the present invention, after obtaining pretreated data, need to transmit data to DSP calculating group, it is according to the present invention
Purpose, the scheme used are separately sent in the DSP calculating group of the road N, for these data are divided into N number of identical content in order to make
Data after must sending can also find the direction of its transmission, and present invention employs identifier, identical N number of number is arranged in data
According to, different identifiers is respectively set, for example, identifier A1 is arranged in first data, second data identifier is set as A2,
And so on, n-th data identifier is set as AN, and allowing for each data in this way has corresponding label, simultaneously as point
At the road N DSP calculating group, that is to say, that be divided into first via DSP calculating group, the second road DSP calculating group, and so on to the road N
DSP calculating group, so, when data occur, identifier is corresponding with road, for example corresponding second tunnel A1, A2 correspond to the first via, etc.
Deng.
After the road the N DSP calculating group is respectively received the pretreated data with identifier information, detection data is
It is no complete, if data are imperfect, identifier information is returned, request data is retransmitted, after receiving identifier information, selection
Data corresponding with identifier, and send data in DSP calculating group corresponding with identifier, receiving complete data
Afterwards, the road the N DSP calculating group independently exports a sub-picture.
Pretreated data are divided into after the identical preprocessed data in the road N is distributed to the road N DSP calculating group, further include,
Automatically it detects whether to send data to the road N DSP calculating group, if there is N-2 circuit-switched data to be not successfully transferred to DSP calculating group,
Second level warning message is issued, prompting current data sendaisle that breaking risk class occurs is middle rank, needs to arouse attention, if having
N-1 circuit-switched data is not successfully transferred to DSP calculating group, then issues level-one warning message, and current data sendaisle is prompted to occur
Breaking risk class be it is advanced, to handle in time.
Judging whether data are successfully transmitted, successful data reception can fed back using DSP calculating group, or to DSP number
It sends datagram according to after transmission to DSP calculating group to prompt the data transmission channel that can normally receive data, it can also
With use other modes, the present invention in no restrictions.
Terminal receives the realtime graphic all exported, carries out images match identifying processing, issues phase according to the result of identification
The control instruction answered.
FPGA pre-processes the multidiameter delay digital signal from phased array antenna.Pretreatment stage includes vertical course phase
Compensation, distance to FFT, apart from pulse pressure and coarse compensation etc..
FPGA starts N number of SRIO module, by preprocessed data it is parallel simultaneously be distributed to N number of DSP calculating group, SRIO mould
Block is also used to for pretreated data to be divided into the identical data to be sent in the road N, and corresponding mark is arranged per data to be sent all the way
Know symbol, when the data distribution to be sent with respective identifier to the road N DSP calculating group, record identifier and the number of being sent
According to current DSP calculating group corresponding relationship；.
By SRIO link, the DDR3 agreement of DSP calculating group (first DSP in selection calculating group) is stored data in
Region.Each DSP calculating group will receive identical original preprocessed data frame；
The road the N DSP calculating group, after being respectively received the pretreated data with identifier information, detection
Whether data are complete, if data are imperfect, return to identifier information, and request data is retransmitted, and complete data are being received
Afterwards, the road the N DSP calculating group independently exports a sub-picture.
Data cell is the minimum data set of DSP calculating group signal processing.By FPGA by multiple initial data frames according to
Centainly sequentially assemble.As shown in Figure 3.
Data cell [m*n] in figure, m indicate the line number of initial data frame in a data cell, and n indicates an original number
It counts according to the data of frame.
It is described pretreated data are divided into the identical preprocessed data in the road N to be distributed to the road N DSP calculating group, further include,
It is distributed to the road N DSP calculating group after pretreated multiple data frames are assembled according to predetermined order, and has been sent by data
Afterwards, it detects whether to be successfully transmitted data to the road N DSP calculating group automatically, be counted if there is N-2 circuit-switched data to be not successfully transferred to DSP
Calculation group then issues second level warning message, and prompting current data sendaisle that breaking risk class occurs is middle rank, needs to cause to infuse
Meaning issues level-one warning message if there is N-1 circuit-switched data to be not successfully transferred to DSP calculating group, prompts current data to send logical
Road occur breaking risk class be it is advanced, to handle in time.
Since the scheme that the present invention uses is separately sent to data in the DSP calculating group of the road N, then just needing to obtain in time
The information for taking these accesses, when there is data not send successfully, will not influence other accesses send data, but in order to
Guarantee that data will be transmitted to terminal in time, is provided with corresponding risk class in the present invention, is managed in time.Institute as above
It states, if there is N-2 circuit-switched data to be not successfully transferred to DSP calculating group, issues second level warning message, prompt current data to send logical
It is middle rank that breaking risk class, which occurs, for road, needs to arouse attention, if there is N-1 circuit-switched data to be not successfully transferred to DSP calculating group,
Issue level-one warning message, prompt current data sendaisle occur breaking risk class be it is advanced, to handle in time
After N number of DSP calculating group receives pretreated data, each self-starting calculation procedure starts N number of complete altogether
Signal processing.
After each DSP calculating group receives the notice of FPGA, each self-starting calculation procedure will start N number of complete letter altogether
Number treatment process.As shown in Figure 4.
There is N number of DSP calculating group in the program, any data communication and control is not present between each DSP calculating group, mutually
It is completely independent operation.Therefore, even if some DSP calculating group is gone on strike by the factors such as malicious attack or hardware self-damage, but
Since calculating group uses distributed nature, each DSP calculating group has the independence of height, and remaining M (M < N) is a at this time
DSP calculating group will continue to provide real-time image data, the sound assurance availability of product, in complicated, severe ring
Reliability under border.
What a from the point of view of system entirety angle, as long as optimizing the calculated performance of DSP calculating group, it is easy to expand to N
A DSP calculating group, this not only lowers the complexity of system integration joint-trial, can efficiently ensure equipment development, technical support
Equal scientific research missions, more to the scalability important in inhibiting of system.For example, when airborne Bistatic SAR real time imagery, each DSP
Calculating group independently calculates piece image, if system needs to reach 500 milliseconds of real time imagery, need to only be directed to a DSP
Calculating group Continuous optimization is calculated time-consuming and is maintained at 1 second time-consuming below.
Secondly, any data communication and control is not present in N number of DSP calculating group, comparison multi-DSP is by assembly line connection
Traditional approach (there are mass data communication and controls), actually increases the overall operation efficiency of system.
Each self-starting calculation procedure, starts N number of complete data handling procedure altogether, further includes, each DSP calculating group
The internal thought for also using parallel computation realizes efficient parallel letter by reasonably organizing the multi-DSP in DSP calculating group
Number calculating process.
There is no any data communication and control between N number of DSP calculating group, it is mutually completely independent operation.
Specifically, according to an embodiment of the invention,
N number of DSP calculating group is performed in parallel signal processing algorithm.Also using parallel computation inside each DSP calculating group
Thought realizes efficient parallel signal calculating process by reasonably organizing the multi-DSP in DSP calculating group.
Bistatic SAR is generally divided into orientation processing and distance to processing, and common signal processing algorithm process includes: fixed point
Turn floating-point, Doppler center estimation, linear range walk about correction, matrix transposition, FFT, IFFT, secondary range pulse pressure correction, hang down
The compensation of equivalent single course quadratic phase, higher order polynomial-fitting, doppler frequency rate estimation, orientation phase compensation, orientation high order
Phase filtering, Phase gradient autofocus, geometric correction etc..
In signal processing, the parallel computation in DSP calculating group can divide three levels to go to define: coarse grain parallelism,
Middle granularity is parallel, fine grained parallel.
(1) coarse grain parallelism
Coarse grain parallelism removes design-calculated concurrency, available coarse grain parallelism technology --- assembly line in top layer
Concurrent technique.Assembly line (pipeline) parallel computing, refers to polyalgorithm task assigning to each DSP computing unit,
Using time-consuming most DSP computing unit as actual Performance Prediction value.
Be evenly distributed for time-consuming in algoritic module, signal data attribute it is consistent, as fixed point turn floating-point, Doppler center
Estimation, linear range are walked about correction, matrix transposition etc., can be deployed on the DSP0 and DSP1 in figure inside DSP calculating group.
(2) granularity is parallel in
Middle granularity is parallel, goes design-calculated concurrency in middle layer, is effectively supplemented coarse grain parallelism.It can be selected
Middle granularity concurrent technique --- Distributed Parallel Computing technology.Distributed (distribution) parallel computing, refer to by
The calculating task of super large calculation amount shares multiple DSP computing units and carries out parallel computation.
Elapsed time in algoritic module is sharply increased, signal data is there is no relevance, such as doppler frequency rate
Estimation, Phase gradient autofocus, geometric correction etc. can be deployed on DSP1~N in figure inside DSP calculating group.
For example, doppler frequency rate estimation module needs estimate each distance unit from signal data (radar return)
Frequency modulation rate, typical algorithm is image offsetting.For by 2048 4096 distance unit data accumulations, signal is calculated
Amount needs 900ms on monolithic DSP, if being distributed to 3 DSP, then the time is approximately original 1/3.
The parallel computation design philosophy for merging " assembly line+distribution ", can be easier to excavate out signal processor most
Best performance.Certainly, the software complexity of this parallel computation is very high, needs good software architecture and carrys out support applications program.
(3) fine grained parallel
It is parallel to refer generally to instruction set for fine grained parallel.The TI company's T MS320C6678 of selection, using Very Long
Instruction Word (VLIW) framework and SIMD assembly instruction abundant, therefore have very powerful instruction set simultaneously
Row function.
N number of DSP calculating group will export N width SAR image after the completion of signal processing altogether.N is sent by SRIO link
Width image is to terminal module.
Terminal receives whole realtime graphics, carries out images match identifying processing, then issues phase according to the result of identification
The control instruction answered.
According to one embodiment of present invention, the present invention provides a kind of computer readable storage medium, the computers
Readable storage medium storing program for executing is stored with computer program, and the computer program is realized when being executed by processor described in above-mentioned any one
The step of method.
The purpose of the present invention is to provide a kind of parallel computation processing method of highly reliable Bistatic SAR real time imagery, it is
System and computer media solve the side such as reliability, communication efficiency, signal handling capacity under the premise of same computational in real time
The defect in face.
It is obvious to a person skilled in the art that the embodiment of the present invention is not limited to the details of above-mentioned exemplary embodiment,
And without departing substantially from the spirit or essential attributes of the embodiment of the present invention, this hair can be realized in other specific forms
Bright embodiment.Therefore, in all respects, the present embodiments are to be considered as illustrative and not restrictive, this
The range of inventive embodiments is indicated by the appended claims rather than the foregoing description, it is intended that being equal for claim will be fallen in
All changes in the meaning and scope of important document are included in the embodiment of the present invention.It should not be by any attached drawing mark in claim
Note is construed as limiting the claims involved.Furthermore, it is to be understood that one word of " comprising " does not exclude other units or steps, odd number is not excluded for
Plural number.Multiple units, module or the device stated in system, device or terminal claim can also be by the same units, mould
Block or device are implemented through software or hardware.The first, the second equal words are used to indicate names, and are not offered as any specific
Sequence.
Finally it should be noted that embodiment of above is only to illustrate the technical solution of the embodiment of the present invention rather than limits,
Although the embodiment of the present invention is described in detail referring to the above better embodiment, those skilled in the art should
Understand, can modify to the technical solution of the embodiment of the present invention or equivalent replacement should not all be detached from the skill of the embodiment of the present invention
The spirit and scope of art scheme.
Claims (10)
1. a kind of parallel computation processing method of Bistatic SAR real time imagery, which is characterized in that the method includes as follows:
Receive the multidiameter delay digital signal from phased antenna；
Pre-process the parallel digital signal；
Pretreated data are divided into the identical data to be sent in the road N, and are sent data in corresponding DSP calculating group,
The road the N DSP calculating group for receiving partial data independently exports a sub-picture；
Terminal receives the realtime graphic all exported, carries out images match identifying processing, is issued according to the result of identification corresponding
Control instruction.
2. parallel computation processing method according to claim 1, which is characterized in that pretreated data are divided into the road N
Corresponding identifier is arranged per data to be sent all the way, when the number to be sent with respective identifier in identical data to be sent
Corresponding relationship when according to being distributed to the road N DSP calculating group, between record identifier DSP calculating group corresponding with the data of being sent；
After the road the N DSP calculating group is respectively received the pretreated data with identifier information, whether detection data is complete
It is whole, if data are imperfect, identifier information is returned, request data is retransmitted, after receiving identifier information, selection and mark
Know and accord with corresponding data, the road the N DSP calculating group for receiving partial data independently exports a sub-picture.
3. parallel computation processing method according to claim 2, which is characterized in that described to be divided into pretreated data
The identical preprocessed data in the road N is distributed to after the DSP calculating group of the road N, further include detect whether for data to be successfully transmitted automatically to
The road N DSP calculating group issues second level warning message if there is N-2 circuit-switched data to be not successfully transferred to DSP calculating group, prompts current
It is middle rank that breaking risk class, which occurs, for data transmitting channel, needs to arouse attention, if having N-1 circuit-switched data be not successfully transferred to
DSP calculating group, then issue level-one warning message, prompt current data sendaisle occur breaking risk class be it is advanced, and
When handle.
4. parallel computation processing method according to claim 3, which is characterized in that
There is no any data communications and control between N number of DSP calculating group, are mutually completely independent operation, and each DSP is calculated
Each self-starting calculation procedure of group, starts N number of complete data handling procedure altogether；
Parallel computation is carried out between each DSP computing unit inside each DSP calculating group, each DSP is calculated single inside DSP calculating group
The parallel computation of member includes: that coarse-grained parallelization, middle granularity parallel computation and fine grained parallel calculate；
Coarse-grained parallelization uses pipeline parallel computing technology, polyalgorithm task is assigned to each DSP by assembly line based on
Calculate unit；
Middle granularity parallel computation uses parallel distributed computing technique, and the calculating task of super large calculation amount is shared DSP and is calculated
Multiple DSP computing units in group carry out parallel computation；
Fine grained parallel, which calculates, uses instruction set parallel computing, calculating task is split into instruction set marquis, simultaneously by instruction set
Row is assigned to different DSP computing units.
5. parallel computation processing method according to claim 4, which is characterized in that
Disposed to following calculation task using coarse grain parallelism: fixed point turns floating-point, Doppler center estimation, linear range are walked about school
Just, matrix transposition；
Granularity in the use of following calculation task is disposed parallel: doppler frequency rate estimation, Phase gradient autofocus, geometry school
Just.
TMS320C6678 is selected in fine grained parallel deployment, using Very Long Instruction Word (VLIW) framework, with
And SIMD assembly instruction abundant.
6. a kind of parallel computation processing system of Bistatic SAR real time imagery, which is characterized in that the system comprises FPGA, N number of
DSP calculating group and terminal, the FPGA include FPGA receiving unit, preprocessing module, N number of SIRO module, the terminal packet
Include terminal control module, wherein
FPGA receiving unit, for receiving the multidiameter delay digital signal from phased antenna；
Preprocessing module, for pre-processing the parallel digital signal, and when receiving data retransmission requests, selection and mark
Corresponding data are accorded with, and are sent data in DSP calculating group corresponding with identifier；
The preprocessing module is also used to detect whether automatically to be successfully transmitted data to the road N DSP calculating group；
SIRO module is distributed to the road N DSP calculating group for pretreated data to be divided into the identical data to be sent in the road N；
The road the N DSP calculating group independently calculates one sub-picture of output after being respectively received pretreated data；
Terminal control module carries out images match identifying processing, according to the knot of identification for receiving the realtime graphic all exported
Fruit issues corresponding control instruction.
7. parallel computation processing system according to claim 6, which is characterized in that the preprocessing module is also used to certainly
It is dynamic to detect whether to be successfully transmitted data to the road N DSP calculating group, if there is N-2 circuit-switched data to be not successfully transferred to DSP calculating group,
Second level warning message is then issued, prompting current data sendaisle that breaking risk class occurs is middle rank, it needs to arouse attention, if
There is N-1 circuit-switched data to be not successfully transferred to DSP calculating group, then issue level-one warning message, prompts current data sendaisle hair
Raw open circuit risk class be it is advanced, to handle in time；
SIRO module, for pretreated data to be divided into the identical data to be sent in the road N, per data setting to be sent all the way
Corresponding identifier, when the data distribution to be sent with respective identifier to the road N DSP calculating group, record identifier and institute
Send the corresponding relationship of the current DSP calculating group of data；
The road the N DSP calculating group, after being respectively received the pretreated data with identifier information, detection data
It is whether complete, if data are imperfect, identifier information is returned to, request data is retransmitted, and the road N of partial data is received
DSP calculating group independently exports a sub-picture.
8. parallel computation processing system according to claim 6, which is characterized in that the FPGA further includes data cell,
For pretreated multiple data frames to be assembled into data packet according to predetermined order.
9. parallel computation processing system according to claim 6, which is characterized in that do not deposited between N number of DSP calculating group
In any data communication and control, it is mutually completely independent operation, each each self-starting calculation procedure of DSP calculating group starts N number of altogether
Complete data handling procedure；
Parallel computation is carried out between each DSP computing unit inside each DSP calculating group, each DSP is calculated single inside DSP calculating group
The parallel computation of member includes: that coarse-grained parallelization, middle granularity parallel computation and fine grained parallel calculate；
Coarse-grained parallelization uses pipeline parallel computing technology, polyalgorithm task is assigned to each DSP by assembly line based on
Calculate unit；
Middle granularity parallel computation uses parallel distributed computing technique, and the calculating task of super large calculation amount is shared DSP and is calculated
Multiple DSP computing units in group carry out parallel computation；
Fine grained parallel, which calculates, uses instruction set parallel computing, calculating task is split into instruction set marquis, simultaneously by instruction set
Row is assigned to different DSP computing units.
10. a kind of computer readable storage medium, the computer-readable recording medium storage has computer program, and feature exists
In realization is such as the step of claim 1 to 5 any one the method when the computer program is executed by processor.
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