CN110263470B - STOLT interpolation realization method and device - Google Patents
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Abstract
A STOLT interpolation implementation method is applied to the technical field of electronics and comprises the following steps: s1, adopting VIVADO HLS to design a STOLT interpolation algorithm to obtain a STOLT interpolation algorithm; s2, inputting the input data into a STOLT interpolation algorithm to obtain an output result; s3, building a test platform, and verifying the STOLT interpolation algorithm in the test platform to obtain a verification result; s4, judging whether the verification result is consistent with the output result; if not, executing S1-S4 again according to the verification result; if the two are consistent, executing S5 and checking the time sequence of the STOLT interpolation algorithm to obtain a time sequence result; s6, judging whether the time sequence result is correct; if not, executing S1-S6 again according to the timing result; and if the result is correct, executing S7, generating a corresponding IP core according to the STOLT interpolation algorithm, and adding the IP core into an IP library of the corresponding FPGA chip in the VIVADO. The invention also discloses a STOLT interpolation implementation device, which can reduce the implementation and debugging difficulty, reduce the optimization difficulty and improve the transportability.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a STOLT interpolation realization method and device.
Background
Synthetic Aperture Radars (SAR) have the characteristics of high resolution, no influence of natural factors such as time and weather, penetration of shelters and the like, and are widely applied to civil and military fields such as disaster detection and mineral exploration.
At present, a plurality of mature SAR imaging algorithms exist, and an omega K algorithm is one of the algorithms which are widely applied. The main flow of the omega K algorithm comprises radar data, two-dimensional Fast Fourier Transform (FFT), reference function multiplication, STOLT interpolation, two-dimensional FFT and image output. Where the reference function multiplication completes the fine focus at the reference distance, but there is a residual phase for targets at other distances. And the STOLT interpolation accurately eliminates residual phases at other positions through mapping from a frequency axis, and completes accurate focusing on all scenes. So STOLT interpolation is the core of the ω K algorithm. In addition, in consideration of implementation precision, the STOLT interpolation module is generally implemented on a Field-Programmable Gate Array (FPGA) by using a double-precision floating point. However, the existing technology implemented in the FPGA has the following problems:
(1) the algorithm is complex, and the traditional Register-Transfer Level (RTL) -based language is difficult to realize. One obvious difference between FPGAs and CPUs is that: the CPU needs software support, and the FPGA is a software and hardware integration. This means that developers can implement algorithm functions in the CPU in a high-level language that is more efficient to implement and does not need to consider hardware implementation structures. And FPGA is closer to IO, and the algorithm is realized by adopting a hardware descriptive language and is directly converted into the combination of the transistor circuit without the translation of an instruction system. Therefore, when implementing complex algorithms using FPGAs, more hardware circuit combinations need to be considered. The complex algorithm is difficult to realize logic control, and the calculation module has large realization workload, which can lead to long algorithm realization period and the condition that the algorithm cannot be realized.
(2) The debugging period is long. The FPGA is a structure integrating software and hardware, so that the algorithm debugging cannot adopt a single-step debugging method. The state of internal signals is monitored and captured by adopting VIO and ILA cores generally. This makes the debugging efficiency of FPGA lower and debugging cycle overlength.
(3) The optimization is difficult. Traditional FPGA implementation based on hardware description language can not realize design optimization through simple optimization instructions, but in design, specific implementation needs to be considered for a certain specific optimization form. If the optimization mode is to be changed, the implementation code needs to be changed. This makes the module optimization space very narrow.
(4) The portability is poor. The circuit design of different types of FPGA chips is different, the realization circuits of the same algorithm on different FPGA chips are different, and the realized codes are also different. Therefore, the portability is poor.
Disclosure of Invention
The present invention is directed to a STOLT interpolation implementation method and apparatus, which can solve at least one of the above technical problems.
In order to achieve the above object, a first aspect of the embodiments of the present invention provides a STOLT interpolation implementation method, including:
s1, adopting VIVADO HLS to design a STOLT interpolation algorithm to obtain a STOLT interpolation algorithm;
s2, inputting the input data into the STOLT interpolation algorithm to obtain an output result;
s3, building a test platform, and verifying the STOLT interpolation algorithm in the test platform to obtain a verification result;
s4, judging whether the verification result is consistent with the output result;
if the verification result is not consistent with the output result, performing steps S1 to S4 again according to the verification result; if the verification result is consistent with the output result, executing step S5, and checking the time sequence of the STOLT interpolation algorithm to obtain a time sequence result;
s6, judging whether the time sequence result is correct or not;
if the timing result is incorrect, performing steps S1-S6 again according to the timing result; and if the time sequence result is correct, executing step S7, generating a corresponding IP core according to the STOLT interpolation algorithm, and adding the IP core into an IP library of the corresponding FPGA chip in the VIVADO.
Further, the inputting the input data into the STOLT interpolation algorithm to obtain an output result includes:
acquiring system parameters of a radar;
calculating a distance direction frequency axis according to the system parameters;
mapping the distance to a frequency axis back to a known frequency axis according to the stolt mapping relation, and calculating a frequency coordinate to be interpolated;
if the frequency coordinate to be interpolated is between [0, NR ], carrying out sinc interpolation on the frequency coordinate to be interpolated, wherein NR is a distance direction sampling point;
if the frequency coordinate to be interpolated is less than 0, outputting the first data of the input data;
and if the frequency coordinate to be interpolated is greater than NR, outputting the last data of the input data.
Further, the performing sinc interpolation on the frequency coordinate to be interpolated includes:
acquiring frequency coordinates of N sampling points in the distance direction around the frequency coordinate to be interpolated;
generating N corresponding sinc function values according to the frequency coordinates of the N sampling points;
multiplying and adding the frequency coordinates of the N sampling points and the N sinc function values in a one-to-one correspondence manner to obtain result data;
and outputting the result data.
Further, the imaginary part of the input data adopts [ -127,128] sawtooth wave cycle data, and the real part is 0.
Further, in the process of implementing the STOLT interpolation algorithm, the implementation process is set to a data stream mode, and the initialization time interval is 1.
A second aspect of the embodiments of the present invention provides a STOLT interpolation implementation apparatus, including:
the design module is used for designing a STOLT interpolation algorithm by adopting VIVADO HLS to obtain the STOLT interpolation algorithm;
the input module is used for inputting input data into the STOLT interpolation algorithm to obtain an output result;
the test module is used for building a test platform and verifying the STOLT interpolation algorithm in the test platform to obtain a verification result;
the first judgment module is used for judging whether the verification result is consistent with the output result or not;
the first adjusting module is used for returning to the design module according to the verification result if the verification result is inconsistent with the output result;
the verification module is used for verifying the time sequence of the STOLT interpolation algorithm to obtain a time sequence result if the verification result is consistent with the output result;
the second judging module is used for judging whether the time sequence result is correct or not;
the second adjusting module is used for returning to the design module according to the time sequence result if the time sequence result is incorrect;
and the generation adding module is used for generating a corresponding IP core according to the STOLT interpolation algorithm if the time sequence result is correct, and adding the IP core into an IP library of the corresponding FPGA chip in the VIVADO.
Further, the input module includes:
the first acquisition submodule is used for acquiring system parameters of the radar;
the first calculation submodule is used for calculating a distance direction frequency axis according to the system parameters;
the mapping submodule is used for mapping the distance to the frequency axis back to the known frequency axis according to the store mapping relation and calculating the frequency coordinate to be interpolated;
the interpolation submodule is used for carrying out sinc interpolation on the frequency coordinate to be interpolated if the frequency coordinate to be interpolated is between [0 and NR ], wherein NR is a distance direction sampling point;
the first output submodule is used for outputting first data of the input data if the frequency coordinate to be interpolated is less than 0;
and the second output submodule is used for outputting the last data of the input data if the frequency coordinate to be interpolated is greater than NR.
Further, the interpolation sub-module includes:
the second acquisition submodule is used for acquiring the frequency coordinates of N sampling points in the distance direction around the frequency coordinate to be interpolated;
the function value generating sub-module is used for generating N corresponding sinc function values according to the frequency coordinates of the N sampling points;
the second calculation submodule is used for multiplying the frequency coordinates of the N sampling points and the N sinc function values in a one-to-one correspondence manner and then adding the frequency coordinates and the N sinc function values to obtain result data;
and the third output submodule is used for outputting the result data.
Further, the imaginary part of the input data adopts [ -127,128] sawtooth wave cycle data, and the real part is 0.
Further, the input module is set to a data stream mode, and the initialization time interval is 1.
This application adopts above-mentioned technical scheme, has following beneficial effect:
(1) according to the invention, a PIPELINE instruction is adopted in the VIVADO HLS, so that the STOLT module PIPELINE processing is realized, output data can be generated in each subsequent clock cycle after a certain clock cycle is delayed, and the data processing efficiency is greatly improved.
(2) The invention adopts VIVADO HLS to realize the module design of STOLT interpolation, realizes the software debugging of the module, improves the module simulation speed and greatly shortens the debugging time of the module.
(3) The invention adopts VIVADO HLS to realize STOLT interpolation module design, unifies time sequence and interface design, avoids a large amount of time sequence alignment work in the RTL language realization process, simplifies the design flow and improves the design efficiency.
(4) The invention adopts VIVADO HLS to realize the STOLT interpolation module design, the design is carried out through C + + language, HLS is adopted to realize the conversion from high-level language C + + to RTL language, the coupling relation between algorithm realization and bottom hardware circuit is removed to a certain extent, and the portability of the module is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a STOLT interpolation implementation method according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of step S2 in the STOLT interpolation implementation method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a STOLT interpolation implementation apparatus according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an input module of the STOLT interpolation device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an interpolation submodule in the STOLT interpolation implementation apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart of a STOLT interpolation implementation method according to an embodiment of the present invention, the method mainly includes the following steps:
s1, adopting VIVADO HLS to design a STOLT interpolation algorithm to obtain a STOLT interpolation algorithm;
vivadd HLS refers to an integrated design simulation software. Furthermore, before interpolation design is carried out by using VIVADO HLS, MATLAB is adopted to carry out STOLT interpolation algorithm design in advance and verify the correctness of the STOLT interpolation algorithm. This embodiment is performed with the premise that the algorithm is guaranteed to be correct.
Correspondingly, in the FPGA hardware design, the STOLT interpolation algorithm is a STOLT interpolation module.
S2, inputting the input data into a STOLT interpolation algorithm to obtain an output result;
the input data can be generated in matlab with imaginary part using [ -127,128] sawtooth cycle data and real part 0. Meanwhile, the input data is saved as a dat file.
In the embodiment of the invention, the STOLT interpolation algorithm can be divided into four steps of frequency mapping, position calculation, data reading and sine interpolation.
S3, building a test platform, and verifying the STOLT interpolation algorithm in the test platform to obtain a verification result;
the test platform is a software test program which can test a test _ bench file corresponding to the STOLT interpolation algorithm.
S4, judging whether the verification result is consistent with the output result;
if the verification result is inconsistent with the output result, performing steps S1 to S4 again according to the verification result; if the verification result is consistent with the output result, executing step S5, and checking the time sequence of the STOLT interpolation algorithm to obtain a time sequence result;
s6, judging whether the time sequence result is correct;
the timing result is correct, for example: when the HLS generates the RTL module, automatically generating corresponding handshake signals: ap _ start, ap _ done, ap _ idle, and ap _ ready, i.e., the timing result is correct.
And the ap _ start control module executes the program, and starts to operate when the logic is 1. It should hold a logical 1 until the corresponding output handshake ap _ ready is set. When ap _ ready goes high, it is decided whether to continue to keep ap _ start set and perform other things or set ap _ start to logic 0, allowing the design to pause at the end of the current transaction. If ap _ start is set low before ap _ ready is a logic 1, the design may not have all input ports read out and may stall the next input read operation.
ap _ ready indicates that the design is ready to accept new data. When a new input is ready to be accepted, the ap _ ready signal is set to logic 1. Indicating that all input reads for this transaction have been completed. If the design is not pipelined, a new read is not started until the next transaction. This signal is used to determine when to use the new value on the port, and whether to use an ap start input to start a new transaction. If the ap start signal is not set high, this signal goes low when all operations in the current transaction completion are designed.
ap _ done indicates that the design completes all operations in the current transaction. The output logic 1 indicates that the design has completed all operations for this transaction. Since at the end of the transaction, this signal is a logic 1 also indicating that the data on the ap _ return port is valid.
ap _ idle indicates that the design is operating or idle (no operation). The output port is indicated by a logic 1 as being idle. Once the design begins to operate, the signal is low. When the signal is high, the design is done and no further operation is performed.
If the timing result is incorrect, executing steps S1-S6 again according to the timing result; if the time sequence result is correct, step S7 is executed, a corresponding IP core is generated according to the STOLT interpolation algorithm, and the IP core is added to the IP library of the corresponding FPGA chip in the vivadd.
More, before step S7, the design of STOLT interpolation algorithm may be optimized to accelerate the throughput rate of data, optimize the resource utilization rate, and accelerate the processing speed, where the specific optimization process is as follows:
the STOLT interpolation algorithm is set to be in a data flow mode, synchronous operation is adopted as much as possible, the characteristic of FPGA parallelization is fully utilized, namely, a program is set to be in a PIPELINE mode, and the initialization time interval is 1. If the data stream processing is not set, a data blocking phenomenon exists in the module execution process, and the data processing speed is reduced.
When HLS is adopted for hardware design, the interface performance is of great importance to the system. According to the requirements of the STOLT interpolation module, an input port of radar data is set to be of an ap _ memory type, and the adopted storage resource type is of a RAM _ S2P _ BRAM type.
In another embodiment, referring to fig. 2, step S2 includes:
s21, acquiring system parameters of the radar;
radar system parameters, e.g. f0Radar center frequency, Kr chirp rate, Vst aircraft flight speed, etc.
S22, calculating a distance direction frequency axis according to the system parameters;
according to the principle of the ω K algorithm, it is assumed that after multiplication by a reference function, the compensated phase in the two-dimensional frequency domain is:
in the formula (f)rIs the range frequency, faIs azimuth frequency, y is target azimuth position, v is platform flight velocity, f0The central frequency of the radar, y the azimuth position of the target, R the vertical distance from the target to the flight path at a certain point in the radar irradiation area, and RrefIs the sag from the reference distance or swath center to the flight path, and c is the speed of light.
For different faBy subjecting the data to STOLT interpolation, the phase can be changed to f'rIs a linear function of (a). Namely:
fris' frThe new distance after mapping is towards the frequency axis. Wherein f isrAnd f'rThe relationship of (a) is as follows:
s23, mapping the distance to the frequency axis back to the known frequency axis according to the store mapping relation, and calculating the frequency coordinate to be interpolated;
after mapping the old frequency axis to the new frequency axis, the original data is in the old frequency axis space. Therefore, the new frequency axis needs to be remapped back to the old frequency axis. And then calculating the frequency coordinate to be interpolated.
If the frequency coordinate to be interpolated is between [0, NR ], executing step S24, and performing sinc interpolation on the frequency coordinate to be interpolated, wherein NR is a distance direction sampling point;
if the frequency coordinate to be interpolated is less than 0, executing step S25, and outputting the first data of the input data;
if the frequency coordinate to be interpolated is greater than NR, step S26 is executed to output the last data of the input data.
Wherein, step S24 includes:
acquiring frequency coordinates of N sampling points in the distance direction around the frequency coordinate to be interpolated;
in the embodiment of the present invention, N is 16 as an example. Assuming that the calculated frequency coordinate to be interpolated is add _ a, the surrounding 16 points are set to [ add _ a-8, add _ a +7 ].
Generating N corresponding sinc function values according to the frequency coordinates of the N sampling points;
and (4) correspondingly multiplying and adding the frequency coordinates of the N sampling points and the N sinc function values one by one to obtain result data.
Referring to fig. 3, the apparatus mainly includes:
the design module 101 is configured to design a STOLT interpolation algorithm by using a vivadd HLS to obtain a STOLT interpolation algorithm;
an input module 102, configured to input data to the STOLT interpolation algorithm to obtain an output result;
the test module 103 is used for building a test platform, and verifying the STOLT interpolation algorithm in the test platform to obtain a verification result;
a first judging module 104, configured to judge whether the verification result is consistent with the output result;
a first adjusting module 105, configured to, if the verification result is inconsistent with the output result, return to the design module according to the verification result;
the checking module 106 is configured to check a time sequence of the STOLT interpolation algorithm to obtain a time sequence result if the verification result is consistent with the output result;
a second judging module 107, configured to judge whether the timing result is correct;
a second adjusting module 108, configured to, if the timing result is incorrect, return to the design module according to the timing result;
and the generation adding module 109 is used for generating a corresponding IP core according to the STOLT interpolation algorithm if the time sequence result is correct, and adding the IP core into an IP library of the corresponding FPGA chip in the VIVADO.
Further, referring to fig. 4, the input module 102 includes:
a first obtaining submodule 1021, configured to obtain system parameters of a radar;
a first calculating submodule 1022, configured to calculate a distance direction frequency axis according to the system parameter;
the mapping submodule 1023 is used for mapping the distance to the frequency axis back to the known frequency axis according to the store mapping relation and calculating a frequency coordinate to be interpolated;
the interpolation submodule 1024 is configured to perform sinc interpolation on the frequency coordinate to be interpolated if the frequency coordinate to be interpolated is between [0 and NR ], where NR is a distance direction sampling point; (obtaining position data of 16 points around if the position data)
A first output sub-module 1025, configured to output a first data of the input data if the frequency coordinate to be interpolated is less than 0;
a second output submodule 1026, configured to output the last data of the input data if the frequency coordinate to be interpolated is greater than NR.
Further, referring to fig. 5, the interpolation submodule 1024 includes:
the second obtaining submodule 10241 is configured to obtain frequency coordinates of N sampling points in a distance direction around the frequency coordinate to be interpolated;
the function value generating sub-module 10242 is configured to generate N corresponding sinc function values according to the frequency coordinates of the N sampling points;
the second calculation submodule 10243 is configured to multiply the frequency coordinates of the N sampling points by the N sinc function values in a one-to-one correspondence manner, and then add the multiplied values to obtain result data;
a third output sub-module 10244 for outputting the result data.
Further, the imaginary part of the input data adopts [ -127,128] sawtooth wave cycle data, and the real part is 0.
Further, the input module is set to a data stream mode, and the initialization time interval is 1.
This application adopts above-mentioned technical scheme, has following beneficial effect:
(1) according to the invention, a PIPELINE instruction is adopted in the VIVADO HLS, so that the STOLT module PIPELINE processing is realized, output data can be generated in each subsequent clock cycle after a certain clock cycle is delayed, and the data processing efficiency is greatly improved.
(2) The invention adopts VIVADO HLS to realize the module design of STOLT interpolation, realizes the software debugging of the module, improves the module simulation speed and greatly shortens the debugging time of the module.
(3) The invention adopts VIVADO HLS to realize STOLT interpolation module design, unifies time sequence and interface design, avoids a large amount of time sequence alignment work in the RTL language realization process, simplifies the design flow and improves the design efficiency.
(4) The invention adopts VIVADO HLS to realize the STOLT interpolation module design, the design is carried out through C + + language, HLS is adopted to realize the conversion from high-level language C + + to RTL language, the coupling relation between algorithm realization and bottom hardware circuit is removed to a certain extent, and the portability of the module is improved.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In view of the above, for the STOLT interpolation implementation method and apparatus provided by the present invention, for a person skilled in the art, there may be changes in the specific implementation and application scope according to the ideas of the embodiments of the present invention, and in summary, the content of the present description should not be construed as limiting the present invention.
Claims (9)
1. A STOLT interpolation implementation method is characterized by comprising the following steps:
s1, adopting VIVADO HLS to design a STOLT interpolation algorithm to obtain a STOLT interpolation algorithm;
s2, inputting the input data into the STOLT interpolation algorithm to obtain an output result;
the inputting of the input data into the STOLT interpolation algorithm to obtain the output result comprises:
acquiring system parameters of a radar;
calculating a distance direction frequency axis according to the system parameters;
mapping the distance to a frequency axis back to a known frequency axis according to the stolt mapping relation, and calculating a frequency coordinate to be interpolated;
if the frequency coordinate to be interpolated is between [0, NR ], carrying out sinc interpolation on the frequency coordinate to be interpolated, wherein NR is a distance direction sampling point;
the performing sinc interpolation on the frequency coordinate to be interpolated comprises:
acquiring frequency coordinates of N sampling points in the distance direction around the frequency coordinate to be interpolated;
generating N corresponding sinc function values according to the frequency coordinates of the N sampling points;
multiplying and adding the frequency coordinates of the N sampling points and the N sinc function values in a one-to-one correspondence manner to obtain result data;
outputting the result data;
s3, building a test platform, and verifying the STOLT interpolation algorithm in the test platform to obtain a verification result;
s4, judging whether the verification result is consistent with the output result;
if the verification result is not consistent with the output result, performing steps S1 to S4 again according to the verification result; if the verification result is consistent with the output result, executing step S5;
s5, checking the time sequence of the STOLT interpolation algorithm to obtain a time sequence result;
s6, judging whether the time sequence result is correct or not;
if the timing result is incorrect, performing steps S1-S6 again according to the timing result; if the timing result is correct, go to step S7;
and S7, generating a corresponding IP core according to the STOLT interpolation algorithm, and adding the IP core into an IP library of the corresponding FPGA chip in the VIVADO.
2. The STOLT interpolation implementation method of claim 1, wherein inputting the input data to a STOLT interpolation algorithm and obtaining the output result comprises:
if the frequency coordinate to be interpolated is less than 0, outputting the first data of the input data;
and if the frequency coordinate to be interpolated is greater than NR, outputting the last data of the input data.
3. A STOLT interpolation realization method according to any of the claims 1-2 characterized in that the imaginary part of the input data is [ -127,128] sawtooth cycle data and the real part is 0.
4. A STOLT interpolation implementation method according to any of claims 1-2, characterized in that in the implementation of the STOLT interpolation algorithm, the implementation is set to data stream mode with an initialization time interval of 1.
5. A STOLT interpolation implementation device is characterized by comprising:
the design module is used for designing a STOLT interpolation algorithm by adopting VIVADO HLS to obtain the STOLT interpolation algorithm;
the input module is used for inputting input data into the STOLT interpolation algorithm to obtain an output result;
the inputting of the input data into the STOLT interpolation algorithm to obtain the output result comprises:
acquiring system parameters of a radar;
calculating a distance direction frequency axis according to the system parameters;
mapping the distance to a frequency axis back to a known frequency axis according to the stolt mapping relation, and calculating a frequency coordinate to be interpolated;
if the frequency coordinate to be interpolated is between [0, NR ], carrying out sinc interpolation on the frequency coordinate to be interpolated, wherein NR is a distance direction sampling point;
the performing sinc interpolation on the frequency coordinate to be interpolated comprises:
acquiring frequency coordinates of N sampling points in the distance direction around the frequency coordinate to be interpolated;
generating N corresponding sinc function values according to the frequency coordinates of the N sampling points;
multiplying and adding the frequency coordinates of the N sampling points and the N sinc function values in a one-to-one correspondence manner to obtain result data;
outputting the result data;
the test module is used for building a test platform and verifying the STOLT interpolation algorithm in the test platform to obtain a verification result;
the first judgment module is used for judging whether the verification result is consistent with the output result or not;
the first adjusting module is used for returning to the design module according to the verification result if the verification result is inconsistent with the output result;
the verification module is used for verifying the time sequence of the STOLT interpolation algorithm to obtain a time sequence result if the verification result is consistent with the output result;
the second judging module is used for judging whether the time sequence result is correct or not;
the second adjusting module is used for returning to the design module according to the time sequence result if the time sequence result is incorrect;
and the generation adding module is used for generating a corresponding IP core according to the STOLT interpolation algorithm if the time sequence result is correct, and adding the IP core into an IP library of the corresponding FPGA chip in the VIVADO.
6. A STOLT interpolation implementation apparatus according to claim 5, wherein the input module comprises:
the first acquisition submodule is used for acquiring system parameters of the radar;
the first calculation submodule is used for calculating a distance direction frequency axis according to the system parameters;
the mapping submodule is used for mapping the distance to the frequency axis back to the known frequency axis according to the store mapping relation and calculating the frequency coordinate to be interpolated;
the interpolation submodule is used for carrying out sinc interpolation on the frequency coordinate to be interpolated if the frequency coordinate to be interpolated is between [0 and NR ], wherein NR is a distance direction sampling point;
the first output submodule is used for outputting first data of the input data if the frequency coordinate to be interpolated is less than 0;
and the second output submodule is used for outputting the last data of the input data if the frequency coordinate to be interpolated is greater than NR.
7. A STOLT interpolation implementation apparatus according to claim 6, wherein the interpolation sub-module comprises:
the second acquisition submodule is used for acquiring the frequency coordinates of N sampling points in the distance direction around the frequency coordinate to be interpolated;
the function value generating sub-module is used for generating N corresponding sinc function values according to the frequency coordinates of the N sampling points;
the second calculation submodule is used for multiplying the frequency coordinates of the N sampling points and the N sinc function values in a one-to-one correspondence manner and then adding the frequency coordinates and the N sinc function values to obtain result data;
and the third output submodule is used for outputting the result data.
8. A STOLT interpolation realization device according to any of the claims 5 to 7, characterized in that the imaginary part of the input data is [ 127,128] sawtooth cycle data, and the real part is 0.
9. A STOLT interpolation realization device according to any of the claims 5-7 characterized in that the input module is set to data flow mode with an initialization time interval of 1.
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