CN109445366B

CN109445366B - FPGA programmable logic resource screening and testing method

Info

Publication number: CN109445366B
Application number: CN201811616300.7A
Authority: CN
Inventors: 孙嘉斌; 贾一平; 周丽萍; 陈倩; 胡凯; 孙晓哲
Original assignee: Nanjing Fanlin Technology Co Ltd
Current assignee: Jinan Guokexin Microelectronics Technology Co.,Ltd.
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2020-10-13
Anticipated expiration: 2038-12-27
Also published as: CN109445366A

Abstract

The invention relates to a method for screening and testing FPGA programmable logic resources, which comprises the following steps: (1) designing the function of programmable logic resources; (2) the lookup table tests the input vector design; (3) RTL level code emulation; (4) analyzing the circuit design by using the test result; (5) and copying the module and outputting the logic design. The screening test method for the FPGA programmable logic resource adopts a test method based on BIST, and overcomes the defects of high test cost and great test technical difficulty of ATE. Only two sets of codes are needed to cover all LUT modules and DFF modules, and the testing efficiency is improved. The method makes full use of the programmable characteristic of the FPGA chip, and rich channel resources and embedded Memory units (BRAMs) in the chip. The method has simple implementation steps, strong transportability and certain engineering application value.

Description

FPGA programmable logic resource screening and testing method

Technical Field

The invention relates to a screening test method of FPGA programmable logic resources, belonging to the technical field of integrated circuits.

Background

The Programmable logic resource is one of the most important and basic hardcores in a Field Programmable Gate Array (FPGA), and the main function is to provide the most basic logic operation and data storage functions for a digital system. Generally, hundreds or even thousands of programmable logic modules are integrated in the FPGA, the number of programmable logic resources is huge, and FPGA manufacturers generally cannot perform comprehensive functional test on common commercial FPGA chips due to the limitation of test time and test cost. In the high-reliability application field, a user needs to perform supplementary screening test on purchased commercial chips so as to meet the requirement of the complete machine on the use reliability of components.

Researchers have designed a variety of structures: based on pass tubes, NAND gates, multi-way switches (MUX), Look-Up tables (LUT), and multi-input gate arrays, etc. Considering the factors of function, layout area, speed and power consumption, the logic module based on LUT structure is commonly used in FPGA at present.

A look-up table (LUT) can be considered to be a memory array having 1-bit outputs, with the address lines of the memory being the input signal lines of the LUT, and a LUT having n inputs corresponding to a memory having 2n memory cells. In an FPGA, an LUT is usually implemented by an SRAM memory cell, and a user writes a truth table of logic functions into the LUT in a programming manner, so as to implement a combinational logic function with any n inputs.

At present, a programmable logic module mainly performs a function Test through an ATE (Automatic Test Equipment) tester, and an ATE device diagnoses an internal fault of an FPGA by inputting a Test vector to an FPGA chip and analyzing a Test output result. Two major problems exist in the ATE test method:

(1) it requires expensive purchase or lease of ATE equipment, development of specific ATE test programs and dedicated test boards, and the use of sockets for chip testing (sockets), which increases the cost burden on users to some extent.

(2) With the increasing integration level of the FPGA, the chip scale is larger and larger, the number of the packaged I/O ports is limited, and the difficulty of performing coverage test on all programmable logic resources by using ATE equipment is larger and larger.

Disclosure of Invention

The invention aims to solve the technical problems that: the defects of the technology are overcome, and the FPGA programmable logic resource screening Test method based on Built-in Self Test (BIST) is provided.

In order to solve the technical problems, the technical scheme provided by the invention is as follows: a method for screening and testing FPGA programmable logic resources comprises the following steps:

(1) designing the function of programmable logic resources; the following two sets of functional circuits are configured: 1) configuring all lookup tables of a tested chip into an n-input exclusive-OR logic gate structure; 2) configuring all lookup tables of a tested chip into an n-input exclusive-OR logic gate structure;

(2) the lookup table tests the input vector design; the design of the lookup table test input vector is generated by a clock and a reset signal through a counter;

(3) RTL level code emulation; obtaining an expected correct output result through a ModelSim behavior level, and further generating an initialization ROM file required by the FPGA embedded memory module; completing storage of a correct result by instantiating a corresponding BRAM IP core module;

(4) analyzing the circuit design by using the test result; when the test is started, generating a corresponding address signal through a clock and a reset signal, and further reading the storage data of a corresponding address in the BRAM module; judging whether the function is correct or not by comparing the calculation result with the calculation result of the programmable logic resource;

(5) module copying and output logic design; and repeating the instantiated Verilog function codes, and simultaneously carrying out exclusive OR operation on the output result of each programmable logic module, so that once a certain tested module has an error, the output signal changes from low to high, and a status indicator lamp is lightened to remind a user.

The scheme is further improved in that: in the step (1), all the outputs of the LUTs in each programmable logic module are registered by the programmable flip-flops, the registered outputs are cascaded to the LUT _ a port of the next-level LUT through the internal channel, and the output of the last programmable flip-flop is connected to the outside of the module.

The screening test method for the FPGA programmable logic resource adopts a test method based on BIST, and overcomes the defects of high test cost and great test technical difficulty of ATE. Only two sets of codes are needed to cover all LUT modules and DFF modules, and the testing efficiency is improved. The method makes full use of the programmable characteristic of the FPGA chip, and rich channel resources and embedded Memory units (BRAMs) in the chip. The method has simple implementation steps, strong transportability and certain engineering application value.

Drawings

The invention will be further explained with reference to the drawings.

FIG. 1 is a flow chart of a screening test implementation according to a preferred embodiment of the present invention.

Figure 2 is a schematic diagram of BLE.

FIG. 3 is a functional block diagram of a test circuit.

FIG. 4 is a functional design block diagram of a programmable logic resource.

Detailed Description

Examples

The method for testing the performance of the FPGA embedded block memory of the embodiment, as shown in FIG. 1, comprises the following steps:

(1) designing the function of programmable logic resources;

(2) the lookup table tests the input vector design;

(3) RTL level code emulation;

(4) analyzing the circuit design by using the test result;

(5) and copying the module and outputting the logic design.

The ergodic test is a test method which inputs all possible test stimuli to a tested circuit and observes the output result of the tested circuit. If the circuit under test is a combinational logic circuit, assuming that there are n data input pins in total, there are 2n test vectors. Assuming that the unit time for completing each test and observation is t, the total time required for completing the test is 2n · t. For sequential circuits, the total test time is still longer. Thus, the traversal test is generally applicable to circuits with fewer inputs. For programmable logic resources, the testing method consumes a large amount of testing time and is high in testing cost.

In view of the reconfigurable characteristic of the FPGA chip, a Built-in Self Test (BIST) method can be adopted to detect and diagnose the fault of the FPGA. Through programming, a part of logic resources of the FPGA are used as a Test Pattern Generation (TPG), the TPG can provide excitation input for a module Under Test (BUT), another part of logic resources are used as an Output Response Analyzer (ORA), and the ORA can analyze and compare Output results of the BUT to further judge whether the BUT has a fault. The present invention therefore introduces a BIST-based testing concept.

Basic Logic Element (BLE) is the smallest programmable unit in FPGA, and each programmable Logic module includes a plurality of BLE. The basic structural diagram of BLE is shown in figure 2.

Each BLE contains an n-input look-up table, a programmable flip-flop controlled by a clock, a carry chain, etc. Taking the four-input lookup table as an example, it can implement any combination of 4 input signals (lut _ a, lut _ b, lut _ c, lut _ d) or sequential logic circuit functions. The look-up table logic function truth table is stored in 16 SRAM units, and can realize any four-input combinational logic function. For register logic, the output of the lookup table is registered and output through the programmable flip-flop, and for combinational logic function, the output of the lookup table bypasses the programmable flip-flop and is directly output to the output end of the BLE.

The programmable Flip-Flop in BLE is a D-type Flip-Flop (DFF) having a data input terminal (in), a clock terminal (clk), an asynchronous clear terminal (nclr), and an output terminal (out). The clock signal and the asynchronous clear signal can be from a global clock network and interconnection resources; the data input signal is derived from the interconnect resource. The output of the programmable flip-flop can also be directly fed back to the input of the look-up table of BLE where it is located.

Since an n-input LUT corresponds to a memory having 2n memory cells, in order to cover all LUT blocks and DFF blocks, the following two sets of functional circuits need to be configured:

(1) all the lookup tables of the tested chip are configured into an n-input exclusive-or logic gate structure, and taking a four-input lookup table as an example, the initialization value of 24 memory cells is 16'b0110_1001_1001_0110, and 16 is denoted as 16' h6996 in a binary system.

(2) All the lookup tables of the chip to be tested are configured into an n-input exclusive-nor structure, and taking a four-input lookup table as an example, the initialization value of 24 memory cells is 16'b1001_0110_0110_1001, and 16 is denoted as 16' h9669 in a carry-over manner.

As shown in fig. 3, the look-up table test input vector design is generated by clock, reset signals through counters, which significantly reduces the number of pins required for testing.

Programmable logic resource functional design block diagram as shown in fig. 4, in each programmable logic module, the outputs of the LUTs are all registered by programmable flip-flops, the registered outputs are cascaded to LUT _ a ports of the next-level LUT through internal channels, and the output of the last programmable flip-flop is connected to the outside of the module.

After the working mode of the programmable logic resource and the test input vector are determined, an expected correct output result can be obtained through ModelSim behavior level simulation, and then an initialization ROM file required by the FPGA embedded memory module is generated. The storage of the correct result can be accomplished by instantiating the corresponding BRAM IP core module.

When the test is started, the corresponding address signal is generated through the clock and the reset signal, and then the storage data of the corresponding address in the BRAM module is read. By comparing with the calculation result of the programmable logic resource, whether the function is correct or not can be judged, and then the state (correct/wrong) is output. The state flag signal changes from low to high in case of error in the calculation result of the programmable logic resource in a certain period.

By repeatedly instantiating the Verilog function codes, the resource utilization rate of the programmable logic modules can reach or approach 100%, and the output result of each programmable logic module is subjected to exclusive OR operation, so that once a certain test module has an error, an output signal changes from low to high, and a state indicator lamp is turned on to remind a user.

The present invention is not limited to the above-described embodiments. All technical solutions formed by equivalent substitutions fall within the protection scope of the claims of the present invention.

Claims

1. A method for screening and testing FPGA programmable logic resources is characterized by comprising the following steps:

(1) designing the function of programmable logic resources; the following functional circuits are configured: configuring all lookup tables of a tested chip into an n-input exclusive-OR logic gate structure;

(4) analyzing the circuit design by using the test result; when the test is started, generating a corresponding address signal through a clock and a reset signal, and further reading the storage data of a corresponding address in the BRAM module; judging whether the function is correct or not by comparing the calculation result with the calculation result of the programmable logic module;

(5) module copying and output logic design; and repeating the instantiated Verilog function codes, and simultaneously carrying out exclusive OR operation on the output result of each programmable logic module, so that once a certain programmable logic module has an error, the output signal changes from low to high, and a status indicator lamp is lightened to remind a user.

2. The method for screening and testing FPGA programmable logic resources of claim 1, characterized in that: in the step (1), all the outputs of the LUTs in each programmable logic module are registered by the programmable flip-flops, the registered outputs are cascaded to the LUT _ a input port of the next-stage LUT through the internal channel, and the output of the last programmable flip-flop is connected to the outside of the module.

3. The method for screening and testing FPGA programmable logic resources of claim 1, characterized in that: in the step (1), all the lookup tables of the tested chip are configured into an n-input exclusive-nor logic gate structure.