CN103474421A - 高产量半导体装置 - Google Patents
高产量半导体装置 Download PDFInfo
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- CN103474421A CN103474421A CN2013103867080A CN201310386708A CN103474421A CN 103474421 A CN103474421 A CN 103474421A CN 2013103867080 A CN2013103867080 A CN 2013103867080A CN 201310386708 A CN201310386708 A CN 201310386708A CN 103474421 A CN103474421 A CN 103474421A
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Abstract
本发明公开了一种半导体装置,包括安装到衬底的两个或更多个裸芯堆叠。第一裸芯堆叠被安装,至少部分地包封,然后测试。如果所述第一裸芯堆叠在预定参数内工作,则在第一裸芯堆叠上安装第二裸芯堆叠,然后,该装置可以经历第二包封工艺。在安装第二裸芯堆叠之前测试第一裸芯堆叠,通过在半导体装置内安装所有裸芯之前识别故障半导体裸芯,来改善产量。
Description
背景技术
便携式消费电子产品的需求的强劲增长驱动了高容量存储器件的需求。诸如闪存存储卡的非易失性半导体存储器件被广泛用以满足对数字信息存储和交换的日益增长的需求。其便携性、多用性和耐震设计以及其高可靠性和大容量已经使得这样的存储器件理想地用于各种电子设备中,包括例如数码相机、数码音乐播放器、视频游戏控制台、PDA和蜂窝电话中。
虽然已知了许多各式各样的封装构造,但是将闪存存储卡通常制造为***级封装(SiP)或多芯片模块(MCM),其中,在小的足印(footprint)衬底上安装和互连多个裸芯(die)。该衬底通常可以包括具有在一侧或两侧上蚀刻有导电层的刚性的电介质基底。在裸芯和导电层之间形成电连接,且导电层提供电引导结构而将裸芯连接到主机装置。一旦裸芯和衬底之间形成了电连接,然后该组件典型地包封在提供保护性封装的模塑复合物(moldingcompound)中。
在图1和2中示出传统半导体封装体20的剖面侧视图和俯视图(图2中没有模塑复合物)。典型的封装体包括多个粘附到衬底26的半导体裸芯、诸如闪存裸芯22和控制器裸芯24。在裸芯制造工艺期间,多个裸芯接合衬垫28可形成在半导体裸芯22、24上。类似地,多个接触衬垫30可形成在衬底26上。裸芯22可以粘附到衬底26,然后可以在裸芯22上安装裸芯24。然后,通过在各个裸芯接合衬垫28和接触衬垫30对之间粘附引线接合件32,可以将所有裸芯电耦合于衬底。一旦所有电连接形成,裸芯和引线接合件可包封在模塑复合物34中,以密封该封装体和保护裸芯和引线接合件。
为了最高效地使用封装体足印,已知在彼此顶上堆叠半导体裸芯,半导体裸芯彼此完全重叠且在相邻裸芯之间具有间隔体层,或如图1和2所示具有偏移。在偏移构造中,一裸芯堆叠在另一裸芯顶上使得下面的裸芯的接合衬垫被暴露。偏移构造有利于方便地接近堆叠中的每个半导体裸芯上的接合衬垫。
随着半导体裸芯变得越来越薄,且为了增加半导体封装体中的存储器容量,半导体封装体的裸芯堆叠中的裸芯数量继续增加。这里存在的一个问题是当在裸芯堆叠的测试期间单个裸芯失效时,通常整个裸芯堆叠就被丢弃。提高产量以使大裸芯堆叠是值得的变得重要。
发明内容
在一个例子中,本技术涉及一种半导体装置,包括:衬底;粘附到衬底的第一裸芯堆叠;第一组引线接合件,将第一裸芯堆叠引线接合到衬底;第一模塑复合物,至少包封第一组引线接合件;第二裸芯堆叠,安装在第一裸芯堆叠上方;第二组引线接合件,将第二裸芯堆叠引线接合到衬底;第二模塑复合物,至少包封第二组裸芯堆叠、第二组引线接合件和第一模塑复合物。
在另一例子中,本技术涉及一种半导体装置,包括:衬底;粘附到衬底的第一裸芯堆叠;第一组引线接合件,将第一裸芯堆叠引线接合到衬底;第一模塑复合物,至少包封第一组引线接合件;第二裸芯堆叠,安装在第一模塑复合物和第一裸芯堆叠上方;第二组引线接合件,将第二裸芯堆叠引线接合到衬底;第二模塑复合物,包封第二裸芯堆叠、第二组引线接合件、第一模塑复合物和未被第一模塑复合物包封的第一裸芯堆叠的任何部分。
在另一例子中,本技术涉及一种用于形成半导体装置的方法,包括:(a)在衬底上安装第一裸芯堆叠;(b)将第一裸芯堆叠电连接到衬底;(c)包封第一裸芯堆叠的至少一部分;(d)测试第一裸芯堆叠的功能性;(e)如果在步骤(d)中第一裸芯堆叠在预定参数内工作,则将第二裸芯堆叠安装在第一裸芯堆叠上;(f)将第二裸芯堆叠电连接到衬底;以及(g)在第二包封步骤中包封第二裸芯堆叠。
附图说明
图1是传统半导体封装体的剖面侧视图。
图2是传统衬底和接合半导体裸芯的引线的俯视图。
图3是根据本发明的实施例的半导体装置的整体制造工艺的流程图。
图4是在根据本技术的实施例的制造工艺中的第一步的半导体装置的侧视图。
图5是在根据本技术的实施例的制造工艺中的第二步的半导体装置的俯视图。
图6是在根据本技术的实施例的制造工艺中的第三步的半导体装置的侧视图。
图7是在根据本技术的实施例的制造工艺中的第四步的半导体装置的侧视图。
图8是在根据本技术的实施例的制造工艺中的第五步的半导体装置的侧视图。
图9是在根据本技术的实施例的制造工艺中的第五步的半导体装置的简化透视图。
图10是在根据本技术的实施例的制造工艺中的第六步的半导体装置的侧视图。
图11是在根据本技术的实施例的制造工艺中的第七步的半导体装置的侧视图。
图12是在根据本技术的实施例的制造工艺中的第八步的半导体装置的侧视图。
图13是在根据本技术的实施例的制造工艺中的第九步的半导体装置的侧视图。
图14-16是根据本技术的半导体装置的可替换实施例的侧视图。
图17-18是根据本技术的半导体装置的另一可替换实施例的侧视图。
具体实施方式
现在,将参考图3至图18来描述本技术,本技术在实施例中涉及包括中间裸芯堆叠的半导体装置,中间裸芯堆叠可在安装另外的裸芯堆叠之前被测试和包封。应理解本发明可以不同形式实施,而应不被解释为限于在此阐述的实施例。更确切地,提供这些实施例以使本公开更加透彻和完整,且将完全地将本发明传达给本领域技术人员。事实上,本发明旨在覆盖这些实施例的替换、修改和等效方式,这些都被包括在由所附权利要求限定的本发明的范围和精神内。另外,在本发明的以下详细描述中,阐述多个具体的细节以便提供对本发明的透彻理解。但是,本领域普通技术人员应清楚本发明可以在没有这些具体细节的情况下实施。
本文使用的术语“顶,”“底,”“上,”“下,”“垂直”和“水平”仅为了示例和阐释目的,而不旨在限制本发明的描述,因为所引用的项目可以在位置和方向上交换。而且,如本文采用的,术语“实质上”、“近似地”和/或“约”是指具体尺度或参数可对于给定应用而在可接受的制造公差内变化。在一个实施例中,可接受制造公差是±0.25%。
现在参考图3的流程图和图4到12的俯视图和侧视图来描述本发明的实施例。虽然图4至图18的每个示出单个装置100或其一部分,但是理解装置100可以与衬底面板上的多个其他封装100一起被批处理以实现规模经济。在衬底上的封装体100的行数和列数可以改变。
该衬底面板以多个衬底102开始(再次,在图4至图18中示出一个这样的衬底)。衬底102可以是各种不同芯片载体媒介、诸如印刷电路板(PCB)、引线框、或卷带自动接合(TAB)卷带。在衬底102是PCB的情况下,该衬底可以由如图4所示的具有顶导电层105和底导电层107的核心103组成。核心103可由各种电介质材料(诸如例如聚酰亚胺叠层、包括FR4和FR5的环氧树脂、双马来酰亚胺三嗪树脂(bismaleimidetriazine,BT)等)组成。尽管核心的厚度对本发明并非关键,但是核心可具有40微米(μm)到200μm之间的厚度,然而在可替换实施例中核心的厚度可能在该范围之外改变。在可替换实施例中,核心103可以是陶瓷的或有机的。
围绕核心的导电层105、107可以由铜或铜合金、电镀铜或电镀铜合金、合金42(42Fe/58Ni)、镀铜钢(copper plated steel)或已知在衬底面板上使用的其他金属和材料组成。导电层可以具有大约10μm到25μm的厚度,然而在可替换实施例中这些层的厚度可在该范围之外变化。
图3是根据本发明的实施例的形成半导体装置的制造工艺的流程图。在步骤200中,衬底102可以被钻孔以在衬底102中限定通孔通路104。这些通路104(图中仅对其中的一些进行了标号)是示例性的,而衬底102可以包括比图中所示的更多的通路104,且它们可以处于不同于图中所示的位置。接下来,在步骤202中,导电图案形成在顶导电层和底导电层之一或两者上。导电图案可以包括例如图5和6中所示的电迹线106和接触衬垫108。迹线106和接触衬垫108(图中仅对其中的一些进行了标号)是示例性的,而衬底102可以包括比图中所示的更多的迹线和/或接触衬垫,且它们可以处于不同于图中所示的位置。
在实施例中,完成的半导体装置100组件可以被用作BGA(球栅阵列)封装体。衬底102的下表面可包括用于接收焊料球的接触衬垫108,如下面要阐释的。在另外的实施例中,完成的半导体装置100可以是包括接触指的LGA(栅格阵列)封装体,接触指用于在主机装置内可移除地耦合完成的装置100。在这样的实施例中,下表面可以包括接触指而非接收焊料球的接触衬垫。在衬底102的顶表面和/或底表面上的导电图案可以通过各种已知的工艺来形成,包括例如各种光刻工艺。
再次参考图3,然后,在步骤204中可在自动光学检查(AOI)中检查衬底102。一旦被检查,可在步骤206中向衬底施加焊料掩模110。在施加了焊料掩模之后,在步骤208中,可以在已知的电镀或薄膜沉积工艺中用Ni/Au、合金42等镀覆接触衬垫、接触指和导电图案上的任何其他的焊料区域。然后,可以在自动检查工艺(步骤210)以及最终视觉检查(步骤212)中检查和测试衬底102以检验电运转,以及发现污染物、刮痕和污点。
假设衬底102通过了检测,接下来可以在步骤214中将无源构件112粘附到衬底。一个或多个无源构件可以包括例如一个或多个电容器、电阻器和/或电感器,然而也可设想其他构件。示出的无源构件112(图中仅对一个无源构件进行了标号)是示例性的,而在其他实施例中可以改变数量、类型和位置。
根据本技术,接下来以允许安装、包封和测试第一组裸芯、然后安装第二组裸芯、包封整个封装、然后测试的方式可将裸芯堆叠粘附到衬底上。这允许包括大量半导体裸芯的封装体的高产量,然而在一些实施例中,本技术的原则可以应用于具有少量半导体裸芯的封装体。通过在所有裸芯安装到半导体装置内之前识别故障半导体裸芯,在安装第二裸芯堆叠之前测试第一裸芯堆叠来改善产量。
在步骤218中,可以在衬底102上形成包括多个半导体裸芯124的第一裸芯堆叠120。在此的形成指的是将裸芯粘附到堆叠中的衬底上,如图7所示,然后,如图8所示采用引线接合件130使半导体裸芯彼此引线接合以及与衬底引线接合。如图7和8所示可以以偏移(阶梯式)构造堆叠裸芯。裸芯可以使用裸芯粘合膜粘附到衬底和/或彼此粘附。作为一个例子,裸芯粘合剂可以是来自Henkel AG&Co.KGaA的8988UV环氧物,固化到B阶段以初步地在堆叠120中粘附裸芯124,接着固化到最终C阶段以永久性地在堆叠120中粘附裸芯124。
半导体裸芯124例如可以是诸如NAND闪存裸芯的存储器裸芯,但是也可以使用其他类型的裸芯124。图7示出其中在堆叠120中安装八个裸芯124的实施例。但是,在其他实施例中,在堆叠120中可以存在多于八个或小于八个的裸芯124。作为其他例子,裸芯堆叠120可以包括四个或六个存储器裸芯。
现在参考图8的侧视图,一旦形成裸芯堆叠120,则堆叠120中的各个裸芯124可以使用引线接合件130彼此电连接以及电连接到衬底120。图9是示出衬底102和裸芯堆叠120中的仅仅底部的两个裸芯124的简化的立体图。如所示,每个半导体堆叠124可包括沿着裸芯124的边缘的一行裸芯接合衬垫134。应理解每个裸芯124可以包括比图9所示的更多的裸芯接合衬垫134。一半导体裸芯的行中的每个裸芯接合衬垫134可以使用引线接合件130电连接到下一个相邻半导体裸芯的行中的对应裸芯接合衬垫134。底部的半导体裸芯124的每个裸芯接合衬垫134可以使用引线接合件130电连接到衬底102上的接触衬垫的行中的对应接触衬垫108。
虽然可以通过各种技术形成引线接合件130,但是在一个实施例中,可以将引线接合件130形成为倒转的球接合件。这些可以通过首先使用已知结构(未示出)的引线接合毛细管在诸如底部裸芯124的裸芯的裸芯接合衬垫上沉积球接合件134来形成。经由引线接合毛细管的中间腔体供给一定长度的引线(典型的金或银合金)可以形成球136(其中之一在图9中被标号)。引线经由毛细管的尖端突出,其中,从与毛细管尖端相关联的换能器(transducer)对引线施加高电压电荷。电荷在尖端融化引线,且由于熔化的金属的表面张力引线形成球136。然后,球136可在负载下被粘附到裸芯接合衬垫134,同时换能器施加超声波能量。
然后,引线接合毛细管可以吐出小长度的引线,且引线可在导电球处被切断,以将球接合件136留在裸芯接合衬垫134上。然后,从毛细管的端部悬吊的引线的小尾部可以用于形成用于行中的下一个后面的裸芯接合衬垫134的球接合件136。可以通过包括例如晶片级的柱形凸起或金凸起的各种其他方法或各种其他方法在半导体裸芯124的接合衬垫处形成球接合件136。
然后,如上所述,在下一个较低层级上(例如,在衬底102上)形成另一球接合件。但是,替代切断引线,引线被吐出并与位于下一个较高层级上的对应球接合件136接触(尽管在其他实施例中可以略过一个或多个级)。引线在负载下被施加到球接合件136,同时换能器施加超声波能量。组合的热量、压力和超声波能量在引线和球接合件136之间产生接合。然后,引线接合毛细管可以吐出小长度的引线,且引线可被切断以在不同层级上的对应接合衬垫之间形成引线接合件130。
可以水平横过裸芯和衬底上的衬垫重复该工艺,以及在裸芯和衬底上的衬垫之间垂直地重复此工艺,直到形成所有引线接合件130。(水平地或垂直地)形成引线接合件130的顺序在不同实施例中可以改变。另外,虽然引线接合件130通常示出为呈现从裸芯堆叠120和衬底的一层到下一层的直垂直列,但是一个或多个引线接合件也可以从一层到下一层对角地延伸。另外,引线接合件跳过裸芯堆叠120中的一个或多个层也是可能的。
在将第一裸芯堆叠120粘附和引线接合到衬底之后,如图10所示,在步骤220中可以将裸芯堆叠120的一部分包封在模塑复合物128中。在实施例中,仅是堆叠120的包括引线接合件130的部分在步骤220中被包封。但是,如以下描述的,在其他实施例中,可以在步骤220中包封任何量的裸芯堆叠120,包括全部的裸芯堆叠120。
模塑复合物128可以包括例如固态环氧树脂、酚树脂(phenol resin)、熔融石英、结晶二氧化硅、碳黑和/或金属羟化物。这种模塑复合物可从例如Sumitomo公司和Nitto-Denko公司得到,其两者在日本都有总部。来自其他制造商的其他模塑复合物是可预期的。根据各种已知工艺,包括通过采用仅覆盖此阶段要包封的半导体装置100的部分的模塑空腔的传递模塑,可施加模塑复合物128。在其他实施例中,可以通过注模或其他技术来执行包封工艺。模塑复合物128可以被施加为A阶段或B阶段环氧物,然后固化至固态C阶段。可替换地,当第二裸芯堆叠被粘附(如以下所述)时模塑复合物128可以被保留为B阶段粘合剂,且随后被固化到C阶段。
在步骤220中的包封之后,可以在步骤222中测试包括裸芯堆叠120的半导体装置100。步骤222可以包括测试裸芯堆叠120中的各个裸芯124的功能性以及装置100的整体功能性的一个或多个操作。在步骤224中,如果装置100没有通过测试,即不是以预定参数工作,则可以丢弃图10所示的装置100。可替换地,取决于测试的结果,可以通过如下所述禁用一个或多个不合格的裸芯而回收装置100。在包封制造中的此阶段探测不合格的封装体,通过防止好的裸芯被添加到故障封装体,节省了装置制造成本,且改善了整体产量。
另一方面,如果图10所示的半导体装置100通过了步骤224中的测试,则可以在步骤228中添加一个或多个附加的裸芯堆叠。具体地,在实施例中,半导体装置100可以包括如以下描述的图11所示的两个裸芯堆叠120、132。然而,可设想通过对于每个附加的裸芯堆叠重复步骤218、220、222、224和226而在半导体装置100内形成的多于两个的裸芯堆叠。但是,注意,对于添加的最后的裸芯堆叠,可以跳过步骤220和222。也就是,不需要在步骤220中包封或测试最上面的裸芯堆叠,因为可以在下述步骤232、240中形成裸芯堆叠之后包封和测试整个封装体。因此,例如,在存在两个裸芯堆叠的情况下,底部的裸芯堆叠可以在步骤220中被部分包封以及在步骤222中被测试,但上部的裸芯堆叠的部分包封和测试可以被跳过,有利于步骤232和240中发生的装置100的整体包封和测试。在例如存在三个裸芯堆叠的情况下,前面的两个可以在步骤220、222中被部分包封和测试,但对于第三和最后的裸芯堆叠可以跳过这些步骤。
假设要在步骤228中添加附加的裸芯堆叠,则流程可以返回到步骤218以形成下一个存储器裸芯堆叠,诸如例如图11所示的裸芯堆叠132。步骤218可以被重复以在裸芯堆叠120的顶上添加裸芯堆叠132。在图11所示的实施例中,裸芯堆叠132可形成为具有类似数量的裸芯但在相反的方向上成阶梯状。引线接合件130可如上所述地形成,引线接合件离开堆叠132中的底部裸芯1241向下延伸到衬底102上的接触衬垫108。这将堆叠132中的半导体裸芯124彼此电连接以及与衬底102电连接。
虽然未示出,但是可以在裸芯堆叠120和132之间提供***体层,以简化引线接合。在其他实施例中省略可以***体。
在实施例中,堆叠132中的底部裸芯1241可以在水平方向上延伸超过底部裸芯堆叠120中的最上面的裸芯,以具有不支撑在其下方的半导体裸芯上的包括裸芯接合衬垫的边缘,如图11所示。为了防止裸芯1241在引线接合工艺期间断裂,底部裸芯1241可以比裸芯堆叠132中的其余裸芯更厚。在一个实施例中,堆叠120和132中的裸芯(除了1241以外)可以具有约25μm的厚度,而裸芯1241可以是约102μm。这些厚度仅是示例性的且可以在其他实施例中改变。在一些实施例中,裸芯1241可以与堆叠132中的其他裸芯一样厚。
在实施例中,裸芯1241可以具有使得其与模塑复合物128的上表面共平面的厚度。因此,裸芯1241直接上方的裸芯可安装在裸芯1241上,具有可能位于模塑复合物128的上表面的顶上的边缘(如图11所示),而不在裸芯内产生压力(stress)。在其他实施例中,裸芯1241的厚度可以使得裸芯1241直接上方的裸芯124可被安装在模塑复合物128的表面上方。
在将裸芯堆叠120、132等安装到衬底102上之后,在步骤230中,可将控制器裸芯(未示出)安装和引线接合到衬底。在实施例中,控制器裸芯可被安装到最上面的裸芯堆叠的最上面的裸芯上。在另外的实施例中,要安装的控制器裸芯位于堆叠120中的最下面的裸芯下方。例如,控制器裸芯可以被安装在衬底102的顶上。国际申请日为2013年1月9日,标题为“Semiconductor Device Including an Independent Film Layer For Embeddingand/or Spacing Semiconductor Die”的专利合作条约专利申请第PCT/CN2013/070264号中公开了这样的实施例的一个例子。作为另一例子,控制器裸芯可安装在衬底102内。在国际申请日为2013年1月28日,标题为“Semiconductor Device Including an Embedded Controller Die and Method ofMaking Same”的专利合作条约专利申请第PCT/CN2013/071051号中公开了这样的实施例的一个例子。这些国际专利申请两者其整体通过引用结合此。
在安装和电连接裸芯堆叠120、132和控制器裸芯之后,可以在步骤232中且如图12所示将裸芯堆叠、控制器、引线接合件以及衬底的至少一部分包封在模塑复合物140中。模塑复合物140可以包括例如固态环氧树脂、酚树脂、熔融石英、结晶二氧化硅、碳黑和/或金属羟化物。这样的模塑复合物可从例如Sumitomo公司和Nitto-Denko公司得到,其两者在日本都有总部。来自其他制造商的其他模塑复合物是可预期的。根据各种已知工艺,包括通过传递模塑和注射模塑技术,可施加模塑复合物。在其他实施例中,包封工艺可以通过FFT(无压流薄,Flow Free Thin)压缩模塑来执行。
可固化的B阶段粘合剂和树脂、诸如例如裸芯之间的裸芯粘合膜和可能的模塑复合物128、140在包封步骤期间可固化到最终的交联的C阶段。在其他实施例中,粘合剂和/或树脂可以在分离的加热步骤中被固化到C阶段。
如图12所示,在步骤232中包封面板上的裸芯之后,对于其中装置100是BGA封装体的实施例,在步骤234中,焊料球142可以被焊接到各个封装体的底表面上的接触衬垫108。在封装体是LGA封装体的情况下,可以跳过步骤226。
在步骤236中被单片化的各个封装体形成如图12或13所示的完成的半导体装置100。每个半导体装置100可以通过多种切割方法中的任一种而被单片化,多种切割方法包括锯、水喷射切割、激光切割、水引导激光切割、干燥介质切割和金刚石涂覆引线切割。虽然直线切割将通常限定矩形或正方形的半导体装置100,但是应理解半导体装置100可以在本发明的其他实施例中具有不同于矩形和正方形的形状。
如上所述,随着每个裸芯堆叠被添加到装置100,可以测试裸芯堆叠和装置100的运转。在将完成的半导体装置100单片化之后,装置可以在步骤240中经受最终测试以确定完成的装置100是否正确运作。如现有技术已知的,这样的测试可以包括电测试、老化(burn in)和其他测试。可选地,在步骤244中,例如在半导体装置是LGA封装体的情况下,完成的半导体装置可被包封在盖(未示出)内。
在一个或多个裸芯没有通过测试步骤222和/或240的情况下,这样的裸芯可以被禁用(即,在裸芯堆叠内电性断开和隔离)。这可以通过切断用于该裸芯的芯片使能(CE)迹线来实现。然后,包括一个或多个被禁用的裸芯的装置可以通过在此描述的制造步骤继续直到得到完整的装置100并且包括一个或多个被禁用的裸芯的装置可以是以较小容量(相比于具有全功能的裸芯的可比封装体)可操作的。
完成的半导体装置100可以例如是诸如MMC卡、SD卡、多用途卡、微SD卡、存储棒、紧凑SD卡、ID卡、PCMCIA卡、SSD卡、芯片卡、智能卡、USB卡、MCP型嵌入式卡存储等的存储卡。
图14-16示出了根据本技术的半导体装置100的另一实施例。图14-16的装置100类似于先前图中的装置,且通过相同的步骤来制造。但是,例如图11所示的裸芯堆叠132与裸芯堆叠120相反地成阶梯状,而图14中的裸芯堆叠132在与裸芯堆叠120相同的方向上成阶梯状。
在此实施例中,模塑复合物128的上表面可以高于裸芯堆叠120中的上部裸芯的表面(至少高出堆叠120中的上部裸芯的引线接合件的高度)。为了对图14-16的实施例中的上部裸芯堆叠132提供层级接合表面(level bondingsurface),间隔体层150可安装在堆叠120的顶部裸芯上,至模塑复合物128的侧面。间隔体层150可以由诸如聚酰亚胺的电介质材料形成,且可以具有使得间隔体层的上表面基本与模塑复合物128的上表面共平面的厚度。在实施例中,可以在粘附第二裸芯堆叠132之前粘附间隔体层。在图14-16的实施例中,底裸芯1241可以与裸芯堆叠132中的其他裸芯一样厚,或其可以如上所述相对较厚。
如先前描述的,在实施例中,中间包封步骤220包封下部裸芯堆叠的围绕引线接合件130的一部分。但是,中间包封步骤220可以包封下部裸芯堆叠的任意量,包括如图17-18所示的所有下部裸芯堆叠。在图17中,示出了两个裸芯堆叠,且第二个裸芯堆叠相对于第一个裸芯堆叠相反地成阶梯状。第一裸芯堆叠可完全包封在模塑复合物128内,然后第二裸芯堆叠可安装在模塑复合物128的上表面上。第二裸芯堆叠的最底部的裸芯可以或可以不比第二裸芯堆叠中的其他裸芯更厚。在图18中,示出了两个裸芯堆叠,第二个裸芯堆叠在与第一个相同的方向上成阶梯状。第一裸芯堆叠可完全包封在模塑复合物128内,然后第二裸芯堆叠可安装在模塑复合物128的上表面上。可以省略在先前实施例中描述的间隔体层150。
为了例示和描述的目的,已经给出了本发明的前述详细描述。这些描述不旨在是穷举的或将本发明限制到所公开的精确形式。在上述教导下,许多修改和变型是可能的。所描述的实施例被选择用以便最佳地说明本发明的原理和其实际应用,从而使得本领域其他技术人员能够在各种实施例中最佳地利用本发明以及采用各种修改使之适合于所构思的具体用途。本发明的范围旨在由随附于此的权利要求所限定。
Claims (24)
1.一种半导体装置,包括:
衬底;
第一裸芯堆叠,粘附到所述衬底;
第一组引线接合件,将所述第一裸芯堆叠引线接合到所述衬底;
第一模塑复合物,至少包封所述第一组引线接合件;
第二裸芯堆叠,安装在所述第一裸芯堆叠上方;
第二组引线接合件,将所述第二裸芯堆叠引线接合到所述衬底;
第二模塑复合物,至少包封所述第二组裸芯堆叠、所述第二组引线接合件和所述第一模塑复合物。
2.根据权利要求1的半导体装置,其中,所述第一裸芯堆叠在第一方向上成阶梯状,而所述第二裸芯堆叠在相反的第二方向上成阶梯状。
3.根据权利要求2的半导体装置,其中,所述第二裸芯堆叠的最底部的裸芯比第二裸芯堆叠中的其他裸芯更厚。
4.根据权利要求1的半导体装置,其中,所述第一裸芯堆叠在第一方向上成阶梯状,且所述第二裸芯堆叠在相同的方向上成阶梯状。
5.根据权利要求4的半导体装置,还包括在所述第一裸芯堆叠和所述第二裸芯堆叠之间的电介质间隔体层。
6.根据权利要求1的半导体装置,其中,所述第一模塑复合物未完全包封整个所述第一裸芯堆叠。
7.根据权利要求1的半导体装置,其中,所述第一模塑复合物包封整个所述第一裸芯堆叠。
8.根据权利要求1的半导体装置,其中,所述第一裸芯堆叠和所述第二裸芯堆叠的每个包括八个存储器裸芯。
9.根据权利要求1的半导体装置,其中,所述第一裸芯堆叠和所述第二裸芯堆叠的每个包括六个存储器裸芯。
10.根据权利要求1的半导体装置,其中,所述第一裸芯堆叠和所述第二裸芯堆叠的每个包括四个存储器裸芯。
11.根据权利要求1的半导体装置,还包括控制器裸芯。
12.根据权利要求1的半导体装置,其中,所述半导体装置是栅格阵列半导体封装体。
13.根据权利要求1的半导体装置,其中,所述半导体封装体是球栅阵列半导体封装体,且还包括安装到所述衬底的表面上的接触衬垫的多个焊料球,所述接触衬垫所在表面与所述衬底的包括所述第一裸芯堆叠和所述第二裸芯堆叠的表面相反。
14.一种半导体装置,包括:
衬底;
第一裸芯堆叠,粘附到所述衬底;
第一组引线接合件,将所述第一裸芯堆叠引线接合到所述衬底;
第一模塑复合物,至少包封所述第一组引线接合件;
第二裸芯堆叠,安装在所述第一模塑复合物和第一裸芯堆叠上方;
第二组引线接合件,将所述第二裸芯堆叠引线接合到所述衬底;
第二模塑复合物,包封所述第二裸芯堆叠、所述第二组引线接合件、所述第一模塑复合物和未被所述第一模塑复合物包封的第一裸芯堆叠的任何部分。
15.根据权利要求14的半导体装置,其中,所述第一模塑复合物的表面与所述第二裸芯堆叠中的最底部的裸芯的表面共平面。
16.根据权利要求14的半导体装置,还包括在所述第一裸芯堆叠和所述第二裸芯堆叠之间的电介质间隔体层。
17.根据权利要求16的半导体装置,其中,所述第一模塑复合物的表面与所述间隔体层的表面共平面。
18.根据权利要求14的半导体装置,其中,所述第一模塑复合物未完全包封整个所述第一裸芯堆叠。
19.根据权利要求14的半导体装置,其中,所述第一模塑复合物包封整个所述第一裸芯堆叠。
20.一种形成半导体装置的方法,包括如下步骤:
(a)在衬底上安装第一裸芯堆叠;
(b)将所述第一裸芯堆叠电连接到所述衬底;
(c)包封所述第一裸芯堆叠的至少一部分;
(d)测试所述第一裸芯堆叠的功能性;
(e)如果在所述步骤(d)中所述第一裸芯堆叠在预定参数内工作,则将第二裸芯堆叠安装在所述第一裸芯堆叠上;
(f)将所述第二裸芯堆叠电连接到所述衬底;以及
(g)在第二包封步骤中包封所述第二裸芯堆叠。
21.根据权利要求20的方法,其中,所述步骤(b)包括将所述第一裸芯堆叠中的半导体裸芯的裸芯接合衬垫引线接合到所述衬底上的接触衬垫。
22.根据权利要求20的方法,其中,所述步骤(c)包括包封所述第一裸芯堆叠的一部分。
23.根据权利要求20的方法,其中,所述步骤(c)包括包封全部的所述第一裸芯堆叠。
24.根据权利要求20的方法,还包括禁用不在预定参数内工作的一个或多个裸芯的步骤。
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TWI574332B (zh) | 2017-03-11 |
US20150061157A1 (en) | 2015-03-05 |
US9240393B2 (en) | 2016-01-19 |
CN103474421B (zh) | 2016-10-12 |
TW201523757A (zh) | 2015-06-16 |
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