CN103456679B - Interconnection structure and manufacture method thereof - Google Patents
Interconnection structure and manufacture method thereof Download PDFInfo
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- CN103456679B CN103456679B CN201210183504.2A CN201210183504A CN103456679B CN 103456679 B CN103456679 B CN 103456679B CN 201210183504 A CN201210183504 A CN 201210183504A CN 103456679 B CN103456679 B CN 103456679B
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Abstract
The invention provides a kind of interconnection structure and manufacture method thereof, carbon nanometer interconnection technique is embedded in traditional CMOS Local Copper interconnection technique, use the through hole of carbon nano-tube as local interlinkage or the interconnection material of contact hole, use graphene nanobelt as the metal wire interconnection material of local interlinkage, significantly reduce the parasitic capacitance between dead resistance and line that copper interconnection technology brings because local interlinkage size is less; Use closed cavity as the connected medium of local interlinkage simultaneously, significantly reduce interlayer sneak electric capacity; Interconnection structure of the present invention and manufacture method thereof, can be compatible with existing CMOS copper interconnection technology, significantly reduces interconnect RC delay, improve chip performance, control chip cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of interconnection structure and manufacture method thereof.
Background technology
Present social information amount sharply increases, and proposes more and more higher requirement to the process of information, transmission and storage.As the pillar of information industry, semiconductor industry especially CMOS technology, under the promotion of this demand, always by Moore's Law high speed development, becomes the industry that development in nearly 50 years is the swiftest and the most violent.
Along with the high speed development of CMOS technology, on chip, the integrated level of device improves constantly, and chip speed is also more and more faster.In order to meet the demand of device integration and speed, Cu interconnection replaces traditional Al interconnection gradually becomes main flow, and the live width simultaneously interconnected also constantly reduces, and wiring density is also more and more higher.But along with the further reduction of Cu interconnect line width, the electron scattering caused by crystal boundary and surface will cause the significantly rising of copper resistance rate, exacerbate the interconnect delay caused by resistance and electric capacity (RC), cause the decline of chip overall performance.
The delay of device and the delay of interconnection decide the maximum operating frequency of circuit jointly.Along with constantly reducing of device size, interconnect delay has surmounted device level delay, becomes the principal element affecting circuit work frequency; Particularly the scattering making the electron transport of Cu line be subject to surface and grain boundary of reducing of live width strengthens, and below 100nm Cu linear resistivity sharply rises, and this will greatly affect the performance of circuit.The use of low-k (low-k) medium can reduce the parasitic capacitance of interconnection introducing, but its application also brings a lot of other problem, and as integration problem, integrity problem etc., low-k material dielectric constant also will reach capacity about 1.5 simultaneously.Estimate that electrochemical process or the technology of CVD deposit Cu and the application of low-k material can proceed to the year two thousand twenty, but the research and development in rear road Cu interconnection technique (comprising the technology such as light network, carbon nanomaterial interconnection) are very urgent.
Graphene (graphene) is a kind of material of novelty, and it is the graphite of monoatomic layer in fact, refers to by the former molecular hexangle type honeycomb lattice planar monolayer film of monolayer carbon, the two-dimensional material be made up of a carbon atomic layer thickness.Graphene nanobelt is then banded Graphene, or can be understood as the Single Walled Carbon Nanotube of expansion, or graphical after graphene-structured.Grapheme material has very excellent performance, comprises high carrier mobility, high current density, high mechanical properties, high thermal conductivity energy etc.
Graphene nanobelt is provided with excellent properties and the unique property of himself of grapheme material, comprising:
1, high conductance property: report that its mean free path can have hundreds of nanometer, the nearly several micron of high electron mobility; The parallel connection of Multi-layer graphite nanobelt significantly can reduce resistance, improving SNR, and small size property is far superior to copper-connection;
2, deelectric transferred performance is superior: its adjacent carbon atom relies on SP
2valence link forms bonding, the very superior 10E9A/cm of mechanical strength and electromigration resistance properties
2the 10E6A/cm of contrast and Cu
2, larger current density can be carried;
3, thermal conductivity is more superior: the thermal conductance of single-layer graphene is reported as 5300W/mK, when being applied in interconnection technique, can have more excellent heat dissipation characteristics, thus improves the reliability performance of interconnection;
4, resistivity is with different GNR(zigzag) rim condition can turn to conductor by semiconductor variable, makes it possible to for different boundary structure to design its different range of application.
Carbon nano-tube (CarbonNanotube) is then a kind of carbon molecule of tubulose, and on pipe, each carbon atom takes SP
2hydridization, each other with carbon-to-carbon σ bond altogether, forms the alveolate texture that is made up of the hexagon skeleton as carbon nano-tube.The a pair p electronics each carbon atom having neither part nor lot in hydridization forms the conjugated pi electron cloud crossing over whole carbon nano-tube each other.Different according to the number of plies of pipe, be divided into Single Walled Carbon Nanotube and multi-walled carbon nano-tubes.The radial direction of pipe is very thin, only have nanoscale, and the length of nanotube can reach hundreds of micron.Carbon nano-tube has very excellent machinery and electrology characteristic, and be also a kind of nano material being applied to the great potential of interconnection technique, especially it is along the guidance quality growth characteristics of catalyst.
In existing advanced CMOS technology, general definition is interconnected as the level of 3 types, local interlinkage, intermediate interconnection and globally interconnected respectively, wherein local interlinkage is the level that size is less, be in the bottom of interconnection structure, comprise the levels such as contact, metal1, via1, metal2, via2, because its size smaller wiring density is higher, be more easily subject to the Performance And Reliability impact that dead resistance and parasitic capacitance and heat leakage in small size Cu interconnection cause; And intermediate interconnection and globally interconnected size larger, wiring density is lower, so the impact being subject to small-size effect is relatively little.
Summary of the invention
The object of the present invention is to provide a kind of interconnection structure and manufacture method thereof, effectively to reduce interconnect RC delay, improve chip performance, control chip cost.
In order to solve the problem, the invention provides a kind of manufacture method of interconnection structure, comprising the following steps:
Semiconductor substrate is provided, is formed with nesting level on the semiconductor substrate, described nesting level comprise be positioned at center the first catalyst layer, around described first catalyst layer first medium layer and run through multiple copper support columns of the first catalyst layer;
Described nesting level forms graphene nanobelt;
Remove described first catalyst layer, described graphene nanobelt, copper support, first medium layer and Semiconductor substrate form closed cavity;
Described graphene nanobelt forms second dielectric layer, and etches described second dielectric layer and graphene nanobelt, form the through hole exposing described copper support column top;
Form the second catalyst layer in described through-hole surfaces, and on the second catalyst layer carbon nano-tube to fill up described through hole.
Further, the material of described first catalyst layer is Co, Ni, Pt or Ru.
Further, the material of described first medium layer is low-K dielectric.
Further, laser direct writing method is adopted to form graphene nanobelt on described nesting level.
Further, wet etching mode is adopted to remove described first catalyst layer.
Further, spin coating or depositional mode is adopted to form second dielectric layer on described graphene nanobelt.
Further, the material of described second dielectric layer is low-K dielectric.
Further, described second catalyst layer adopts PVD, CVD, PLD or ALD mode to deposit formation.
Further, the material of described second catalyst layer is Co, Ni, Pt or Ru.
Accordingly, the present invention also provides a kind of interconnection structure, comprise the first medium layer, graphene nanobelt and the second dielectric layer that are formed in Semiconductor substrate from bottom to top, described interconnection structure also comprises closed cavity and carbon nano-tube, described closed cavity top is graphene nanobelt, sidewall is first medium layer, and bottom is Semiconductor substrate, is provided with the multiple copper support columns be positioned in Semiconductor substrate in chamber; Described carbon nano-tube filled in running through second dielectric layer and graphene nano brings in the through hole at described copper support column top.
Further, the length of described graphene nanobelt than described first medium layer and second dielectric layer short, described first medium layer directly contacts with described second dielectric layer bottom margin.
Compared with prior art, interconnection structure provided by the invention and manufacture method thereof, carbon nanometer interconnection technique is embedded in traditional CMOS Local Copper interconnection technique, use the through hole of carbon nano-tube as local interlinkage or the interconnection material of contact hole, use graphene nanobelt as the metal wire interconnection material of local interlinkage, significantly reduce the parasitic capacitance between dead resistance and line that copper interconnection technology brings because local interlinkage size is less; Use closed cavity as the connected medium of local interlinkage simultaneously, significantly reduce interlayer sneak electric capacity; Interconnection structure of the present invention and manufacture method thereof can be compatible with existing CMOS copper interconnection technology, significantly reduce interconnect RC delay, improve chip performance, control chip cost.
Accompanying drawing explanation
Fig. 1 is the manufacture method flow chart of interconnection structure of the present invention;
Fig. 2 A ~ 2D is the device architecture cutaway view in the interconnection structure manufacture process of the specific embodiment of the invention.
Embodiment
The interconnection structure proposed the present invention below in conjunction with the drawings and specific embodiments and manufacture method thereof are described in further detail.
As shown in Figure 1, the invention provides a kind of interconnection structure manufacture method, comprise the following steps:
S1, provides Semiconductor substrate, is formed with nesting level on the semiconductor substrate, described nesting level comprise be positioned at center the first catalyst layer, around described first catalyst layer first medium layer and run through multiple copper support columns of the first catalyst layer;
S2, described nesting level forms graphene nanobelt;
S3, removes described first catalyst layer, described graphene nanobelt, copper supports, first medium layer and Semiconductor substrate form closed cavity;
S4, described graphene nanobelt forms second dielectric layer, and etches described second dielectric layer and graphene nanobelt, forms the through hole exposing described copper support column top;
S5, forms the second catalyst layer in described through-hole surfaces, and on the second catalyst layer carbon nano-tube to fill up described through hole.
Please refer to Fig. 2 A, in step sl, the Semiconductor substrate 200 provided can be Si, Ge, SiGe or GaAs semi-conducting material; Be formed with nesting level on semiconductor substrate 200, described nesting level comprise be positioned at center the first catalyst layer 201, around described first catalyst layer 201 first medium layer 202 and run through multiple copper support columns 203 of the first catalyst layer 201.First catalyst layer 201 is preferably Co, Ni, Pt or Ru.
The mode forming this nesting level has multiple, and wherein a kind of method forming nesting level comprises:
First, deposit first medium layer 202 on semiconductor substrate 200, described first medium layer 202 can be low K dielectric layer, and thickness is 300 ~ 2000 dusts;
Then, etching first medium layer 202, until exposing semiconductor substrate 200, forms groove (trench);
Then, deposit the first catalyst layer 201 in the trench, the material of described first catalyst layer 201 is Co, Ni, Pt or Ru;
Then, etch the first catalyst layer 201 and form multiple through hole,
Then, fill copper in through-holes, form copper support column 203.
The another kind of method forming nesting level comprises:
First, the first catalyst layer 201 is deposited on semiconductor substrate 200;
Then, etch the first catalyst layer 201, until exposing semiconductor substrate 200, then remove the first catalyst layer 201 edge one fixed width, and form multiple through hole wherein;
Then, fill copper in through-holes, form copper support column 203;
Then, Semiconductor substrate 200 and the first catalyst layer 201 deposit first medium layer 202, and described in chemical-mechanical planarization, first medium layer 202 to the first catalyst layer 201, can form nesting level.
Please refer to Fig. 2 B, in step s 2, laser direct writing method can be adopted, under the catalytic action of the first catalyst layer 201, growing graphene nanobelt 204 on described nesting level, this graphene nanobelt 204 is as the follow-up interconnection line interconnected for through-hole interconnection (Via) or contact hole (Contact) structure partial, and can be individual layer, also can be multilayer.Graphene nanobelt 204 significantly can reduce dead resistance, simultaneously due to time graphene nanobelt 204 very thin, the parasitic capacitance between its line is also significantly reduced.
Please continue to refer to Fig. 2 B, in step s3, wet etching mode is adopted to remove described first catalyst layer 201, make graphene nanobelt 204, copper supports 203, first medium layer 202 and Semiconductor substrate 200 form closed cavity, use closed cavity as the connected medium of local interlinkage, significantly reduce interlayer sneak electric capacity.Due to the similar graphite surface of Graphene, can the various atom of adsorption and desorption and molecule, therefore wet etching liquid can the first catalyst layer 201 fast erosion through graphene nanobelt 204 to below, and to graphene nanobelt 204, copper supports 203, the corrosion of first medium layer 202 is relatively slow, therefore choosing of wet etching liquid needs to make the first catalyst layer 201 Graphene relatively, copper, first medium layer 202 has very high selectivity, preferably, the corrosive liquid of wet etching is 96% sulfuric acid of 50 volume ratios, the mixed liquor of 30% hydrogen peroxide of 1 volume ratio, corrosion temperature is at about 120 degree.
Please refer to Fig. 2 C, in step s 4 which, first, the mode of spin coating or deposition can be adopted, described graphene nanobelt 204 and first medium layer 202 form second dielectric layer 205, and second dielectric layer 205 is low-K dielectric or ultralow K dielectric material (as porous material); Then etch described second dielectric layer 205 and graphene nanobelt 204, form the through hole 206 exposing described copper support column 203 top;
Please refer to Fig. 2 D, in step s 5, first, adopt the sputtering of the metals such as Co, Ni, Pt or Ru, evaporation, plating or deposition process on described through hole 206 surface by formation second catalyst layer 207, the deposition process of described second catalyst layer 207 comprises PVD, CVD, PLD or ALD; Then, can by the method such as chemical vapour deposition technique (or be called hydrocarbon gas pyrolysismethod), laser ablation method of temperature lower than 500 degrees Celsius, carbon nano-tube (CNT) 208 is grown into, to complete the filling of through hole 206 under the catalytic action of the second catalyst layer 207.
Accordingly, please refer to Fig. 2 D, the present invention also provides a kind of interconnection structure, comprise the first medium layer 202 be formed in Semiconductor substrate 200, graphene nanobelt 204 and second dielectric layer 205 from bottom to top, described interconnection structure also comprises closed cavity and carbon nano-tube 208, and described closed cavity top is graphene nanobelt 204, and sidewall is first medium layer 202, bottom is Semiconductor substrate 200, is provided with the multiple copper support columns 203 be positioned in Semiconductor substrate 200 in chamber; Described carbon nano-tube 208 is filled in and runs through second dielectric layer 202 and graphene nanobelt 204 in the through hole at described copper support column 203 top.
In the present embodiment, described graphene nanobelt 204 than described first medium layer 202 and second dielectric layer 205 short, described first medium layer 202 is directly contacted, for local interlinkage with described second dielectric layer 205 bottom margin.
In sum, interconnection structure provided by the invention and manufacture method thereof, carbon nanometer interconnection technique is embedded in traditional CMOS Local Copper interconnection technique, use the through hole of carbon nano-tube as local interlinkage or the interconnection material of contact hole, use graphene nanobelt as the metal wire interconnection material of local interlinkage, significantly reduce the parasitic capacitance between dead resistance and line that copper interconnection technology brings because local interlinkage size is less; Use closed cavity as the connected medium of local interlinkage simultaneously, significantly reduce interlayer sneak electric capacity; In the intermediate interconnection level that interconnection structure of the present invention and manufacture method thereof can be applied to road copper interconnection technology after existing CMOS and globally interconnected level, to realize the compatibility with existing CMOS copper interconnection technology, significantly reduce interconnect RC delay, improve chip performance, control chip cost.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. a manufacture method for interconnection structure, is characterized in that, comprising:
Semiconductor substrate is provided, is formed with nesting level on the semiconductor substrate, described nesting level comprise be positioned at center the first catalyst layer, around described first catalyst layer first medium layer and run through multiple copper support columns of the first catalyst layer;
Described nesting level forms graphene nanobelt;
Remove described first catalyst layer, described graphene nanobelt, copper support column, first medium layer and Semiconductor substrate form closed cavity;
Described graphene nanobelt forms second dielectric layer, and etches described second dielectric layer and graphene nanobelt, form the through hole exposing described copper support column top;
Form the second catalyst layer in described through-hole surfaces, and on the second catalyst layer carbon nano-tube to fill up described through hole.
2. the manufacture method of interconnection structure as claimed in claim 1, it is characterized in that, the material of described first catalyst layer is Co, Ni, Pt or Ru.
3. the manufacture method of interconnection structure as claimed in claim 1, it is characterized in that, the material of described first medium layer is low-K dielectric.
4. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, adopts laser direct writing method to form graphene nanobelt on described nesting level.
5. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, adopts wet etching mode to remove described first catalyst layer.
6. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, adopts spin coating or depositional mode to form second dielectric layer on described graphene nanobelt.
7. the manufacture method of the interconnection structure as described in claim 1 or 6, is characterized in that, the material of described second dielectric layer is low-K dielectric.
8. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, described second catalyst layer adopts PVD, CVD, PLD or ALD mode to deposit formation.
9. the manufacture method of the interconnection structure as described in claim 1 or 8, is characterized in that, the material of described second catalyst layer is Co, Ni, Pt or Ru.
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| CN1937172A (en) * | 2005-08-31 | 2007-03-28 | 韩国科学技术院 | Method of forming on predetermined area of substrate with grown carbon nanotube, and method of forming semiconductor metal wire and inductor by using the same |
| CN101573797A (en) * | 2006-09-04 | 2009-11-04 | 皇家飞利浦电子股份有限公司 | Control of carbon nanostructure growth in an interconnect structure |
| CN102403304A (en) * | 2011-12-06 | 2012-04-04 | 上海集成电路研发中心有限公司 | Interconnection structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1937172A (en) * | 2005-08-31 | 2007-03-28 | 韩国科学技术院 | Method of forming on predetermined area of substrate with grown carbon nanotube, and method of forming semiconductor metal wire and inductor by using the same |
| CN101573797A (en) * | 2006-09-04 | 2009-11-04 | 皇家飞利浦电子股份有限公司 | Control of carbon nanostructure growth in an interconnect structure |
| CN102403304A (en) * | 2011-12-06 | 2012-04-04 | 上海集成电路研发中心有限公司 | Interconnection structure and manufacturing method thereof |
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