CN103390602B - 半导体封装件及其封装基板 - Google Patents

半导体封装件及其封装基板 Download PDF

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CN103390602B
CN103390602B CN201210167790.3A CN201210167790A CN103390602B CN 103390602 B CN103390602 B CN 103390602B CN 201210167790 A CN201210167790 A CN 201210167790A CN 103390602 B CN103390602 B CN 103390602B
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layer
patterned metal
packaging
base plate
metal layer
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林长甫
蔡和易
姚进财
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其封装基板，该半导体封装件包括：具有图案化金属层的封装基板、接合于该封装基板上的半导体芯片、以及形成于该封装基板与该半导体芯片之间的底充材料，通过于该图案化金属层上形成开口，以减少该图案化金属层的面积，所以可减少该底充材料与金属材的接触面积，以避免该底充材料脱层。

Description

半导体封装件及其封装基板
技术领域
本发明涉及一种半导体封装件，尤指一种具有特殊图案化金属层的半导体封装件及其封装基板。
背景技术
在现行覆晶封装技术中，如图1所示的半导体封装件1，通过将一具有防焊层（solder mask）102的封装基板10借由多个导电凸块111结合一半导体芯片11，再形成底充材料12(Underfill)于该半导体芯片11与该封装基板10之间，以包覆该些导电凸块111，且该底充材料12与该防焊层102间的结合力佳，可避免该底充材料12与该封装基板10分离。
随着电子产业的蓬勃发展，电子产品逐渐迈向多功能、高性能的趋势，且电子产品在型态上的设计也趋于轻薄短小，例如：一般具有细间距（fine pitch）线路的封装基板10同时整合有细线路（线宽约等于12um）与大尺寸的接地部（径宽大于200um）及粗线路（线宽大于20um）。
然而，该封装基板10上的防焊层102虽可防止介电层100（其材质为预浸材Prepreg,PP）表面上的线路层101氧化，却也增加该封装基板10的厚度，致使整体结构难以薄化。
因此，遂发展出另一种覆晶用的封装基板，其上不需形成防焊层，借以达到薄化需求。如图2A所示，现有半导体封装件2中，通过将一不具有防焊层的封装基板20的电性连接垫201a借由多个导电凸块211结合一半导体芯片21，再形成底充材料22于该半导体芯片21与该封装基板20之间，以包覆该些导电凸块211，且该底充材料22直接覆盖线路层201，以防止该线路层201氧化。
此外者，为了提升散热功效，该封装基板20的表面上布设有大面积的图案化金属层202，且该图案化金属层202也可供该半导体芯片21作接地。
然而，因该底充材料22与该介电层200间的结合力佳，而该底充材料22与金属材的结合力差，所以当该底充材料22与该金属材（线路层201与图案化金属层202）间的接触面积过多时，容易造成脱层(delamination)，即该底充材料22与该封装基板20分离。
因此，第7808113号美国专利提供了解决上述问题的方式，如图2B所示的半导体封装件2’中，是于一封装基板20’的线路层201’与金属层202’上形成一助粘层（adhesionpromoter layer）203，且该底充材料22与该助粘层203间的结合力佳，使该底充材料22仅与少部分的金属材相结合，所以可避免脱层。
然而，制作该助粘层203的其中一种方式，是将所有金属材（除了电性连接垫201a处）的表面粗糙化以形成有机金属表面（organometallic surface）供作为助粘层203，导致成本高、工艺复杂度高及工艺时间长，而不利于产品量产化。
此外，制作该助粘层203的另一方式是于该金属材表面上沉积硅烷偶合剂(silanecoupling agent)以作为助粘层203，但该线路层201’与金属层202’的表面相当凹凸（例如：导电通孔201b），导致沉积硅烷偶合剂时不易控制该助粘层203的厚度，且仍有成本高、工艺复杂度高及工艺时间长等问题，所以不利于产品大量生产。
因此，如何克服上述现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明的主要目的在于提高一种半导体封装件及其封装基板，可减少该底充材料与金属材的接触面积，以避免该底充材料脱层。
本发明所提供的半导体封装件，包括：一封装基板，其具有介电层、形成于该介电层的同一面上的至少一图案化金属层及线路层，该图案化金属层具有至少一开口；半导体芯片，是以覆晶方式结合于该封装基板上，且电性连接该线路层；以及底充材料，如含环氧树脂的底胶，其形成于该封装基板与该半导体芯片之间，以结合该介电层、该半导体芯片、该线路层及至少一该图案化金属层。
本发明还提供一种半导体封装件，其包括：一封装基板，其具有介电层、形成于该介电层的同一面上的至少一图案化金属层及线路层，该图案化金属层具有至少一开口；半导体芯片，其以覆晶方式结合于该封装基板上，且电性连接该些线路层，又该半导体芯片未覆盖该图案化金属层；以及底充材料，如含环氧树脂的底胶，其形成于该封装基板与该半导体芯片之间，以结合该介电层、该线路层及该半导体芯片，又该底充材料未结合该图案化金属层。
本发明还提供一种封装基板，其包括：一基板本体，其具有介电层；线路层，其设于该介电层的表面上；以及至少一图案化金属层，其设于该线路层所在的介电层同一面上，且该图案化金属层具有至少一开口。
前述的半导体封装件及其封装基板中，该开口于该图案化金属层上的所占面积比例为35%至60%。
前述的半导体封装件及其封装基板中，该开口外露该介电层表面。
前述的半导体封装件及其封装基板中，该开口开设于该图案化金属层的侧部。或者，该开口开设于该图案化金属层边缘内。
前述的半导体封装件及其封装基板中，至少一该图案化金属层作为接地或散热之用。
另外，前述的半导体封装件及其封装基板中，该封装基板内具有导电通孔，以电性连接该线路层，且该线路层具有多个电性连接垫，以供电性连接该半导体芯片。其中，该半导体芯片借由多个导电凸块结合于该些电性连接垫上，且该底充材料包覆该些导电凸块。
由上可知，本发明的半导体封装件及其封装基板中，其借由在该封装基板上的图案化金属层形成外露该介电层表面的开口，以减少该图案化金属层的面积，而增加该底充材料与该介电层的接触面积，所以相比于现有技术，本发明的结构中，可减少底充材料与该图案化金属层间的接触面积，因而有效避免脱层的问题。
此外，该开口工艺具有简易性、步骤少、成本低、工艺时间短等优点，因而利于产品大量生产。
附图说明
图1为现有半导体封装件的剖视示意图；
图2A及图2B为现有半导体封装件的不同实施例的剖视示意图；
图3为本发明半导体封装件的剖视示意图；
图4A至图4D为本发明半导体封装件的不同实施例的上视示意图；以及
图5A、图5B及图5C为本发明封装基板的图案化金属层的不同实施例的局部上视示意图。
主要组件符号说明
1,2,2’,3 半导体封装件
10,20,20’,30 封装基板
100,200,300 介电层
101,201,201’,301 线路层
102 防焊层
11,21,31 半导体芯片
111,211,311 导电凸块
12,22,32 底充材料
201a,301a 电性连接垫
201b 导电通孔
202,202’ 金属层
203 助粘层
30a 基板本体
302,302’ 图案化金属层
302a,302a’ 开口
310 电极垫
33 表面处理层。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图3，其为本发明的半导体封装件3的剖面示意图。如图3所示，该半导体封装件3包括：一封装基板30、覆晶接合该封装基板30的一半导体芯片31、以及形成于该封装基板30与该半导体芯片31之间的底充材料32。
所述的封装基板30具有一基板本体30a、设于该基板本体30a上的至少一介电层300、设于该介电层300同一表面上的线路层301及至少一图案化金属层302，且该图案化金属层302具有至少一开口302a，又该图案化金属层302与该线路层301不相电性连接。
于本实施例中，该基板本体30a内具有导电通孔（图未示）以电性连接该线路层301，且该线路层301具有多个电性连接垫301a，而该图案化金属层302的材料包含铜或铝，又该些开口302a外露该介电层300表面。
此外，可于该些电性连接垫301a上形成表面处理层33，且形成该表面处理层33的材料选自由电镀镍/金、化学镀镍/金、化镍浸金（ENIG）、化镍钯浸金（ENEPIG）、化学镀锡（Immersion Tin）及有机保焊剂(OSP)所组成的群组中的其中一者。
此外，一并参阅图4A至图4C，其为该图案化金属层302的布设区域的上视示意图，该图案化金属层302作为提升散热效率与电性改进（如接地）之用，所以该图案化金属层302可视不同封装应用需求而布设于置晶区的不同区域上；但该图案化金属层302的布设形状并不限于图中所示，且图4A至图4C中该置晶区定义为底充材料32所分布的区域内。
另外，该基板本体30a为压合板材，其包含Bismaleimide和Triazine聚合而成的BT板材或含Ajinomoto build up film的ABF板材。
所述的半导体芯片31具有多个电极垫310，该些电极垫310借由多个导电凸块311结合且电性连接于该些电性连接垫301a上，使该半导体芯片31覆晶接合该封装基板30。
于本实施例中，该半导体芯片31与该图案化金属层302为接地连接。
所述的底充材料32包覆该些导电凸块311，且结合该线路层301、图案化金属层302、介电层300表面及该开口302a中的介电层300表面。
于本实施例中，该底充材料32为包含环氧树脂的底胶。
本发明的半导体封装件3借由在该图案化金属层302上形成开口302a，以减少该图案化金属层302的面积，因而可降低该底充材料32与该金属材的接触面积，且增加该底充材料32与该介电层300的接触面积，所以有效克服现有技术中的脱层问题。
此外，该开口302a于该图案化金属层302上所占的面积比例（即开口面积率）为35%至60%时，较利于防止脱层。其中，所述的开口面积率的定义如下：
开口面积率=开口面积／金属总面积
此外，本发明仅需于该图案化金属层302上进行开口工艺，即可克服脱层问题，且因有关开口工艺的方法繁多，并且开口技术已相当成熟与普及，所以相比于现有技术，本发明利用开口工艺将使该半导体封装件3的成本低、工艺简易及工艺时间短，且不受该图案化金属层302的表面凹凸结构影响，因而有利于产品大量生产。
另外，于另一实施例中，如图4D所示，该图案化金属层302’完全位于该置晶区外，使该半导体芯片31未覆盖该图案化金属层302’，且该底充材料32未结合该图案化金属层302’，所以仍可降低该底充材料32与金属材的接触面积。
请一并参阅图5A及图5B，该开口302a开设于该图案化金属层302的同一侧部，如图5A所示；或者，该开口302a开设于该图案化金属层302的不同侧部，如图5B所示。
此外，如图5C所示，该开口302a’也可开设于该图案化金属层302边缘内。
此外，于本实施例中，是以L形的图案化金属层302作说明，而于其它实施例中，该图案化金属层302的形状可任意设计，并无特别限制，也就是只要于该图案化金属层302上形成开口302a即可。
另外，该开口302a,302a’的端面轮廓形状可为圆形、矩形、三角形、方形、长方形、十字形、星形、椭圆形、多边形或任意形状，并无特别限制。
综上所述，本发明半导体封装件及其封装基板，主要借由该封装基板上的图案化金属层具有外露该介电层表面的开口，以减少该图案化金属层的面积，而增加该底充材料与该介电层的接触面积，因而避免该底充材料与该金属层间的脱层问题。
此外，开口工艺因具有简易性、步骤少、成本低、工艺时间短等优点，所以有利于产品大量生产。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种半导体封装件，其包括：
一封装基板，其具有介电层、形成于该介电层的同一面上的至少一图案化金属层及线路层，该图案化金属层边缘内具有至少一开口，该开口于该图案化金属层上的所占面积比例为35％至60％；
半导体芯片，其以覆晶方式结合于该封装基板上，且电性连接该线路层；以及
底充材料，其形成于该封装基板与该半导体芯片之间，以结合该介电层、该半导体芯片、该线路层及至少一该图案化金属层。
2.一种半导体封装件，其包括：
一封装基板，其具有介电层、形成于该介电层的同一面上的至少一图案化金属层及线路层，该图案化金属层边缘内具有至少一开口，该开口于该图案化金属层上的所占面积比例为35％至60％；
半导体芯片，其以覆晶方式结合于该封装基板上，且电性连接该些线路层，又该半导体芯片未覆盖该图案化金属层；以及
底充材料，其形成于该封装基板与该半导体芯片之间，以结合该介电层、该线路层及该半导体芯片，又该底充材料未结合该图案化金属层。
3.根据权利要求1或2所述的半导体封装件，其特征在于，该开口外露该介电层表面。
4.根据权利要求1或2所述的半导体封装件，其特征在于，至少一该图案化金属层作为接地或散热之用。
5.根据权利要求1或2所述的半导体封装件，其特征在于，该封装基板内具有导电通孔，以电性连接该线路层，且该线路层具有多个电性连接垫，以电性连接该半导体芯片。
6.根据权利要求5所述的半导体封装件，其特征在于，该半导体芯片借由多个导电凸块结合于该些电性连接垫上，且该底充材料包覆该些导电凸块。
7.根据权利要求1或2所述的半导体封装件，其特征在于，该底充材料的材质包含环氧树脂。
8.一种封装基板，其包括：
一基板本体，其具有介电层；
线路层，其设于该介电层的表面上；以及
至少一图案化金属层，其设于该线路层所在的介电层同一面上，且该图案化金属层边缘内具有至少一开口，该开口于该图案化金属层上的所占面积比例为35％至60％。
9.根据权利要求8所述的封装基板，其特征在于，该开口外露该介电层表面。
10.根据权利要求8所述的封装基板，其特征在于，至少一该图案化金属层是作为接地或散热之用。
11.根据权利要求8所述的封装基板，其特征在于，该封装基板内具有导电通孔，以电性连接该线路层，且该线路层具有多个电性连接垫，以供电性连接半导体芯片。
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