CN105023910B - 导电盲孔结构及其制法 - Google Patents

导电盲孔结构及其制法 Download PDF

Info

Publication number
CN105023910B
CN105023910B CN201410198024.2A CN201410198024A CN105023910B CN 105023910 B CN105023910 B CN 105023910B CN 201410198024 A CN201410198024 A CN 201410198024A CN 105023910 B CN105023910 B CN 105023910B
Authority
CN
China
Prior art keywords
blind hole
conductive blind
dielectric layer
perforation
preparation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410198024.2A
Other languages
English (en)
Other versions
CN105023910A (zh
Inventor
陈彦亨
林畯棠
纪杰元
詹慕萱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN105023910A publication Critical patent/CN105023910A/zh
Application granted granted Critical
Publication of CN105023910B publication Critical patent/CN105023910B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)

Abstract

一种导电盲孔结构及其制法，该导电盲孔结构的制法，通过先形成穿孔于一封装胶体上，再形成介电层于该封装胶体上，且该介电层填满该些穿孔，之后形成盲孔于该介电层上，且该盲孔位于该些穿孔中，最后形成导电材于该盲孔中。藉由先将该介电层填满该些穿孔，再形成该盲孔于该些穿孔中的介电层中，以改善该些穿孔的壁面的粗糙度。

Description

导电盲孔结构及其制法
技术领域
本发明涉及一种贯穿胶体(Through molding via,TMV)的技术，尤指一种导电盲孔结构及其制法。
背景技术
贯穿胶体(Through molding via,TMV)的技术，目前已广泛运用于半导体领域，其主要技术为利用激光烧灼方式于封装胶体表面进行开孔制程，以显露出位于封装胶体下的电性接点(如线路或电性连接垫)。
例如，制作扇出型(Fan-Out,FO)封装堆栈(Package on Package,POP)结构时，便会使用该技术。图1A至图1D为现有FO-POP封装结构的导电盲孔结构的制法的剖面示意图。
如图1A所示，一具有多个线路层100的封装基板10设于一支撑件9上，且该封装基板10上设有一芯片11与一封装胶体12，并使该封装胶体12包覆该芯片11。
如图1B所示，形成一介电层13于该封装胶体12上。
如图1C所示，利用激光钻孔方式贯穿该介电层13与该封装胶体12，以形成多个盲孔130，令最上层的部分该线路层100(即电性连接垫)外露于该盲孔130。
如图1D所示，电镀形成如铜的导电材14于该介电层13上与该盲孔130中，使该介电层13上的导电材14作为扇出型线路重布层141，且于该盲孔130中的导电材14作为导电盲孔140，以令该导电盲孔140电性连接该线路层100与该线路重布层141。
于后续制程中，如图1E所示，形成一绝缘保护层15于该线路重布层141与该介电层13上，且该绝缘保护层15形成有多个开孔150，使该线路重布层141的电性接触垫142外露于该些开孔150。之后，形成一表面处理层16于该电性接触垫142上，以结合多个如焊球的导电组件(图略)于该表面处理层16上，俾制成半导体封装件1。最后，移除该支撑件9。
目前该盲孔130的最大孔径R为100至200微米(um)，如第1C图所示，随着该半导体封装件1的体积朝轻薄短小及功能性增强的趋势设计，该盲孔130的孔径将愈做愈小，且布孔密度也愈高，以符合装结构体积轻薄短小、及功能性增强的需求。
然而，前述现有导电盲孔140的制法中，使用激光钻孔方式形成该盲孔130，使该盲孔130的壁面130a呈现不平整表面，如图1C’所示，该盲孔130的壁面130a的粗糙度(Ra)为50微米(um)，也就是该盲孔130的壁面130a极为粗糙，所以该导电盲孔140将因粗糙的该壁面130a而形成锯齿状表面，如图1D所示，导致电荷容易集中于该导电盲孔140的表面突起处，以致于容易因电阻过高而产生焦耳热，进而造成线路断路的问题。
此外，于电镀铜时，会先溅镀一极薄的铜材晶种层(seed layer，图略)，但铜材与该封装胶体12的接口不亲，所以当该盲孔130的壁面130a极为粗糙时，该晶种层的铜材容易脱落(peeling)，致使后续电镀的导电材14无法有效附着于该盲孔130的壁面130a上而发生脱层现象，导致该半导体封装件1的可靠度不佳。
又，遂有另一方式，通过于该壁面130a上镀覆一钝化层(passvation layer)12’，以形成另一盲孔120，如图1C”所示，而藉以改善孔壁的粗糙度，之后再形成该导电材14于该盲孔120中。然而，该钝化层12’的厚度t仅1至2微米(um)，并无法有效填补该壁面130a的粗糙度，也就是该盲孔120的壁面120a仍然粗糙，即该盲孔120的壁面120a仍无法避免线路断路与铜材脱落的问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的目的为提供一种导电盲孔结构及其制法，能避免当电荷累积过多而产生焦耳热以造成线路断路的问题。
本发明的导电盲孔结构，包括：封装胶体，其具有连通至该封装胶体外部的多个穿孔；介电层，其形成于该封装胶体上并填充该些穿孔，且于该些穿孔中形成有盲孔；以及导电材，其填充于该盲孔中。
本发明还提供一种导电盲孔结构的制法，包括：于一封装胶体中形成连通至该封装胶体外部的多个穿孔；形成介电层于该封装胶体上，且该介电层填满该些穿孔；形成盲孔于该介电层上，且该盲孔位于该些穿孔中；以及形成导电材于该盲孔中。
前述的导电盲孔结构及其制法中，该些穿孔以激光钻孔方式形成者，使该些穿孔的壁面为非平整面，且该些穿孔的壁面的平均粗糙度为2至60微米。
前述的导电盲孔结构及其制法中，该穿孔的最大孔径为40至400微米。
前述的导电盲孔结构及其制法中，该介电层的材质为感旋光性材质。
前述的导电盲孔结构及其制法中，该介电层于该些穿孔中的厚度为30至50微米。
前述的导电盲孔结构及其制法中，该盲孔以曝光方式形成者，使该盲孔的壁面为平整面，且该盲孔的最大孔径为30至350微米。
前述的导电盲孔结构及其制法中，该导电材以电镀方式形成者，例如，该导电材填满该盲孔。
另外，前述的导电盲孔结构及其制法中，该导电材为铜材。
由上可知，本发明的导电盲孔结构及其制法，藉由先将该介电层填满该些穿孔，再形成该盲孔于该些穿孔中的介电层中，以改善该些穿孔的壁面的粗糙度，而使该盲孔的壁面呈平整面。因此，该导电材于该盲孔中不会产生电荷集中于孔壁突起处的现象，所以能避免当电荷累积过多而产生焦耳热以造成线路断路的问题。
此外，由于铜材与该介电层的接口极亲，所以铜材不会从该盲孔的壁面上脱落，因而能避免该导电材脱层的问题。
附图说明
图1A至图1D为现有导电盲孔结构的制法的剖面示意图；其中，图1C’为图1C的局部放大图，图1C”为图1C’的另一方式；
图1E为接续图1D的后续制程的剖面示意图。
图2A至图2D为本发明的导电盲孔结构的制法的剖面示意图；其中，图2C’为图2C的局部放大图2D’；以及
图2E为接续图2D的后续制程的剖面示意图。
符号说明
1,2 半导体封装件
10 封装基板
100,200 线路层
11 芯片
12,22 封装胶体
12’ 钝化层
120,130,230 盲孔
120a,130a,220a,230a 壁面
13,23 介电层
14,24 导电材
140,240,240’ 导电盲孔
141,241 线路重布层
142,242 电性接触垫
15,25 绝缘保护层
150,250 开孔
16,26 表面处理层
20 承载件
21 电子组件
220 穿孔
9 支撑件
D,R,R’ 孔径
T,t 厚度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2D为本发明的导电盲孔结构的制法的剖面示意图。
如图2A所示，一承载件20设于一支撑件9上，且该承载件20上设有一电子组件21与一封装胶体22，并使该封装胶体22包覆该电子组件21。之后，于该封装胶体22中形成连通至该封装胶体22外部的多个穿孔220。
于本实施例中，该承载件20为封装基板，其具有多个线路层200，以令最上层的部分该线路层200外露于该些穿孔220。于其它实施例中，该承载件20也可为中介板、半导体结构或导线架等，并不限于此。
此外，该穿孔220的最大孔径R’为40至400微米(um)，且以激光钻孔方式形成该些穿孔220，所以该些穿孔220的壁面220a为非平整面，如图2C’所示的不规则的凹凸面，且该些穿孔220的壁面220a的平均粗糙度(Ra)为2至60微米(um)。
又，该电子组件21为半导体组件，如主动组件或被动组件，并可使用多个半导体组件，且可选自主动组件、被动组件或其组合，该主动组件例如：芯片，而该被动组件例如：电阻、电容及电感。
另外，有关该承载件20、电子组件21与封装胶体22的组构结合的方式繁多，并无特别限制。
如图2B所示，形成一介电层23于该封装胶体22上，且该介电层23填满该些穿孔220。
于本实施例中，该介电层23的材质为感旋光性材质。
如图2C所示，形成多个盲孔230于该介电层23上，且该盲孔230的位置位于该些穿孔220中。
于本实施例中，最上层的该线路层200外露于该盲孔230。
此外，以曝光方式形成该盲孔230，所以该盲孔230的壁面230a为平整面，如图2C’所示的环形弧面。
又，该盲孔230为锥形孔，且该盲孔230的最大孔径D为30至350微米(um)。
另外，该介电层23于该些穿孔220中的厚度T为30至50微米(um)，如图2C’所示。
如图2D所示，形成导电材24于该介电层23上与该盲孔230中，使该介电层23上的导电材24作为一线路重布层241(Redistribution layer,RDL)，且于该盲孔230中的导电材24作为一导电盲孔240。
于本实施例中，利用电镀或沉积方式形成该导电材24，以填满该盲孔230。或者，于其它实施例中，如图2D’所示的导电盲孔240’，该导电材24未填满该盲孔230。
此外，该导电盲孔240,240’电性连接该最上层的该线路层200与该线路重布层241。
又，于后续制程中，如图2E所示，形成一绝缘保护层25于该线路重布层241与该介电层23上，且该绝缘保护层25形成有多个开孔250，使该线路重布层241的电性接触垫242外露于该些开孔250，以供结合多个如焊球的导电组件(图略)于该电性接触垫242上，以制成半导体封装件2，且该些导电组件用于接至其它如封装件、半导体组件或封装基板的电子装置(图略)上。最后，移除该支撑件9。
另外，也可先形成一表面处理层26于该电性接触垫242上，再结合该导电组件于该表面处理层26上。
本发明的制法中，藉由先将该介电层23填满该些穿孔220，再利用曝光方式形成该盲孔230，以改善该些穿孔220的壁面220a的粗糙度。
此外，由于利用曝光方式形成该盲孔230，使该介电层23于该些穿孔220中的厚度T够厚，而使该盲孔230的壁面230a得以呈平整面，因而电镀铜所制的导电盲孔240,240’不会产生电荷集中于孔壁突起处的现象，进而能避免当电荷累积过多而产生焦耳热以造成线路断路的问题，所以相较于现有技术，该导电盲孔240,240’的品质更佳，且使该半导体封装件2能正常运作。
又，由于铜材与该介电层23的接口极亲，所以于电镀或沉积该导电材24时，所溅镀的铜材晶种层(seed layer，图略)的铜材不会从该盲孔230的壁面230a上脱落，使该导电材24不会脱层，因而能提升该导电盲孔240,240’的品质，以利于该半导体封装件2的信赖性提升。
本发明提供一种导电盲孔结构，其包括：一封装胶体22、形成于该封装胶体22上的一介电层23、以及导电材24。
所述的封装胶体22具有连通至该封装胶体22外部的多个穿孔220，该些穿孔220的壁面220a为非平整面，且该些穿孔220的壁面220a的平均粗糙度为2至60微米，又该穿孔220的最大孔径R’为40至400微米。
所述的介电层23的材质为感旋光性材质，其复填充该些穿孔220并于该些穿孔220中形成有盲孔230，该盲孔230的壁面230a为平整面，且该盲孔230的最大孔径D为30至350微米。
所述的导电材24填充于该盲孔230中，以作为导电盲孔240,240’。
于一实施例中，该介电层23于该些穿孔220中的厚度T为30至50微米(um)。
于一实施例中，该导电材24填满该盲孔230。
于一实施例中，该导电材24为铜材。
综上所述，本发明的导电盲孔结构及其制法，主要藉由该介电层填平该些穿孔的粗糙壁面，以形成平整壁面的盲孔，所以不仅能避免线路断路与铜材脱落的问题，以提升该导电盲孔的品质，且不会增加材料成本。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种导电盲孔结构，包括：
封装胶体，其具有连通至该封装胶体外部的多个穿孔；
介电层，其形成于该封装胶体上并填充该些穿孔，且对填满该些穿孔中的介电层进行曝光方式以形成有盲孔，该盲孔的壁面为平整面；以及
导电材，其填充于该盲孔中。
2.如权利要求1所述的导电盲孔结构，其特征在于，该些穿孔的壁面为非平整面。
3.如权利要求1所述的导电盲孔结构，其特征在于，该些穿孔的壁面的平均粗糙度为2至60微米。
4.如权利要求1所述的导电盲孔结构，其特征在于，该穿孔的最大孔径为40至400微米。
5.如权利要求1所述的导电盲孔结构，其特征在于，该介电层的材质为感旋光性材质。
6.如权利要求1所述的导电盲孔结构，其特征在于，该介电层于该些穿孔中的厚度为30至50微米。
7.如权利要求1所述的导电盲孔结构，其特征在于，该盲孔的最大孔径为30至350微米。
8.如权利要求1所述的导电盲孔结构，其特征在于，该导电材为铜材。
9.如权利要求1所述的导电盲孔结构，其特征在于，该导电材填满该盲孔。
10.一种导电盲孔结构的制法，包括：
于一封装胶体中形成连通至该封装胶体外部的多个穿孔；
形成介电层于该封装胶体上，且该介电层填满该些穿孔；
对填满该些穿孔中的介电层进行曝光方式以形成有盲孔，该盲孔的壁面为平整面；以及
形成导电材于该盲孔中。
11.如权利要求10所述的导电盲孔结构的制法，其特征在于，该些穿孔以激光钻孔方式形成。
12.如权利要求10所述的导电盲孔结构的制法，其特征在于，该些穿孔的壁面的平均粗糙度为2至60微米。
13.如权利要求10所述的导电盲孔结构的制法，其特征在于，该穿孔的最大孔径为40至400微米。
14.如权利要求10所述的导电盲孔结构的制法，其特征在于，该介电层的材质为感旋光性材质。
15.如权利要求10所述的导电盲孔结构的制法，其特征在于，该介电层于该些穿孔中的厚度为30至50微米。
16.如权利要求10所述的导电盲孔结构的制法，其特征在于，该盲孔的最大孔径为30至350微米。
17.如权利要求10所述的导电盲孔结构的制法，其特征在于，该导电材为铜材。
18.如权利要求10所述的导电盲孔结构的制法，其特征在于，该导电材以电镀方式形成。
CN201410198024.2A 2014-04-15 2014-05-12 导电盲孔结构及其制法 Active CN105023910B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103113640 2014-04-15
TW103113640A TWI548030B (zh) 2014-04-15 2014-04-15 導電盲孔結構及其製法

Publications (2)

Publication Number Publication Date
CN105023910A CN105023910A (zh) 2015-11-04
CN105023910B true CN105023910B (zh) 2018-09-07

Family

ID=54265695

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410198024.2A Active CN105023910B (zh) 2014-04-15 2014-05-12 导电盲孔结构及其制法

Country Status (3)

Country Link
US (1) US9607941B2 (zh)
CN (1) CN105023910B (zh)
TW (1) TWI548030B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170002668A (ko) 2011-12-20 2017-01-06 인텔 코포레이션 등각 저온 밀봉 유전체 확산 장벽들
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR101982054B1 (ko) * 2017-08-10 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297142B1 (en) * 1998-03-18 2001-10-02 Hitachi Cable Ltd. Method for bonding a semiconductor chip to a lead-patterning substrate using a gold/tin alloy

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI295550B (en) * 2005-12-20 2008-04-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
US7767496B2 (en) * 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9147610B2 (en) * 2012-06-22 2015-09-29 Infineon Technologies Ag Monitor structures and methods of formation thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297142B1 (en) * 1998-03-18 2001-10-02 Hitachi Cable Ltd. Method for bonding a semiconductor chip to a lead-patterning substrate using a gold/tin alloy

Also Published As

Publication number Publication date
TW201539653A (zh) 2015-10-16
TWI548030B (zh) 2016-09-01
CN105023910A (zh) 2015-11-04
US9607941B2 (en) 2017-03-28
US20150294938A1 (en) 2015-10-15

Similar Documents

Publication Publication Date Title
CN101499445B (zh) 半导体器件及其制造方法
CN110098162A (zh) 包括导热层的半导体封装件
KR20180121893A (ko) 내장형 실리콘 기판의 팬 아웃 3d 패키지 구조
TW201705615A (zh) 用於低溫接合的結構和方法
CN104538318B (zh) 一种扇出型圆片级芯片封装方法
US9583418B2 (en) Chip embedded package method and structure
CN103119702A (zh) 具有聚合物填料沟槽的半导体芯片装置
TW201304080A (zh) 無核心層之封裝基板及其製法
CN104465542A (zh) 具有模塑通孔的叠层封装结构
CN102403275B (zh) 一种堆叠封装结构及其制作方法
CN103794569A (zh) 封装结构及其制法
CN105489565B (zh) 嵌埋元件的封装结构及其制法
JP2017034059A (ja) プリント配線板、半導体パッケージおよびプリント配線板の製造方法
CN102456636A (zh) 嵌入式芯片的封装件及其制造方法
CN102915995B (zh) 半导体封装件、基板及其制造方法
CN108962840A (zh) 电子封装件及其制法
CN105023910B (zh) 导电盲孔结构及其制法
JP2017195261A (ja) インターポーザ及びインターポーザの製造方法
CN110459521A (zh) 覆晶封装基板和电子封装件
TWI283055B (en) Superfine-circuit semiconductor package structure
TW202414634A (zh) 用於低溫接合的結構和方法
CN101360393B (zh) 嵌埋半导体芯片的电路板结构及其制法
TWI550744B (zh) 單層線路式封裝基板及其製法、單層線路式封裝結構及其製法
CN105489580B (zh) 半导体衬底及半导体封装结构
CN105304583B (zh) 封装结构的制法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant