CN103378148B - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN103378148B CN103378148B CN201210109964.0A CN201210109964A CN103378148B CN 103378148 B CN103378148 B CN 103378148B CN 201210109964 A CN201210109964 A CN 201210109964A CN 103378148 B CN103378148 B CN 103378148B
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Abstract
The invention provides a kind of semiconductor device and manufacture method, by forming groove first in a silicon substrate, after trenched side-wall forms barrier bed, continue to increase gash depth with expose portion silicon substrate, then in thermal oxidation process, make the silicon substrate of expose portion form silicon oxide layer, remove after silicon oxide layer afterwards, form pan in a silicon substrate, be positioned at not removed silicon material above pan and then form bridging structure above the pan that is located at.Semiconductor device of the present invention can form semiconductor nanowire transistor structure in the bridging structure of silicon material, replace the silicon on insulated substrate of prior art, and the size of bridging structure can be controlled well by the process conditions in controlled oxidization process, for the semiconductor nanowire transistor structure of follow-up formation provides accurate size Control.
Description
Technical field
The present invention relates to semiconductor device and manufacture method, particularly relate to a kind of semiconductor device and manufacture method thereof of semiconductor nanowire transistor structure.
Background technology
Recent decades, MOS field-effect transistor (metal-oxide-semiconductorfieldeffecttransistor, MOSFET) constantly to the trend development of minification, to gather way, to improve Components integration degree and the cost reducing integrated circuit.Along with the integrated level of semiconductor device is more and more higher, when grid width constantly shortens, mean that the influence degree that source electrode and drain electrode cause for the current potential of raceway groove (Channel) increases gradually, therefore, when grid width foreshortens to a certain degree, what " short-channel effect " caused the uncontrollable in fact raceway groove of voltage that grid applies opens or closes state.Traditionally with the mode solving short-channel effect comprise increase Semiconductor substrate body doping content, reduce thickness of grid oxide layer and engage with using shallow source/drain.But when grid width foreshortens to below 50nm, aforesaid way is difficult to suppress short-channel effect gradually, and thus planar MOSFET transistor reaches the lower limit of device size.Gradually the substitute is multiple-gate transistors tubular construction, multiple-gate transistors tubular construction can improve capacitive coupling effect between grid and raceway groove, increase grid to the control ability of channel potential, suppress short-channel effect, thus enable transistor size continue development to constantly reducing trend.
Wherein, multigrid transistor is common comprises FinFET (FinFET), grid wraps up transistor (Gate-All-Aroundtransistor entirely, GAAtransistor) and etc. structure, along with size constantly reduces, device architecture enters nano-grade size, semiconductor nanowire transistor structure is arisen at the historic moment, and efficiently solves short-channel effect (ShortChannelEffect, SCE).
In the prior art, a kind of method of semiconductor nanowire transistor structure is formed in silicon-on-insulator substrate (SOI substrate), silicon on insulated substrate comprises and buries oxide structure and be positioned at the silicon layer buried on oxide structure, after etching silicon layer, remove to be positioned at and bury oxide structure under silicon layer, thus make silicon layer form bridging structure, and form pan below bridging structure, in subsequent technique, in described bridging structure and around form semiconductor nanowire transistor structure.
Because the cost of SOI substrate is relatively high, how in common Si layer structure, pan and the bridging structure be located at above pan become industry problem demanding prompt solution.
Summary of the invention
The object of this invention is to provide a kind of semiconductor device controlled for the formation of semiconductor nanowire transistor structure, size and manufacture method thereof.
For solving the problems of the technologies described above, the invention provides a kind of semiconductor device, for the formation of semiconductor nanowire transistor structure, described semiconductor device comprises silicon substrate, described silicon substrate is formed with the bridging structure that pan arranges with the multiple flat shape be located on described pan.
Further, the interface of described bridging structure is circular.
Further, the diameter of the circular cross-section of described bridging structure is 5nm ~ 50nm.
Further, adjacent bridging structure distance is 5nm ~ 50nm.
The present invention also provides a kind of manufacture method of semiconductor device, and described semiconductor device is for forming semiconductor nanowire transistor structure, and described manufacture method comprises the following steps:
Silicon substrate is provided, described silicon substrate covers hard mask layer;
Hard mask layer and silicon substrate described in dry etching part for the first time, to form multiple grooves;
The sidewall of described groove forms barrier bed;
Silicon substrate described in second time dry etching, increases the degree of depth of described groove;
Carry out thermal oxidation technology, in the silicon substrate that the layer that is not blocked blocks, form silicon oxide layer in described groove;
Remove described barrier bed and silicon oxide layer, to form pan and be positioned at the multiple bridging structures on described pan on described silicon substrate.
Further, the material of described hard mask layer is silicon nitride or silicon oxynitride, and the thickness of described hard mask layer is 10nm ~ 500nm.
Further, after first time dry etching, the degree of depth of described groove in described silicon substrate is 5nm ~ 60nm.
Further, the forming step of described barrier bed comprises:
On described hard mask layer, the bottom surface of described groove and deposited on sidewalls block film;
Etching remove be positioned on described hard mask layer and the bottom surface of described groove block film, to form barrier bed on the sidewall of described groove.
Further, the thickness 2nm ~ 20nm of described barrier bed.
Further, after second time dry etching, the degree of depth of described groove in described silicon substrate is 10nm ~ 500nm.
Further, the temperature of described thermal oxidation technology is 600 DEG C ~ 1200 DEG C, the time is 5 seconds ~ 10 hours.
Further, the gas that passes into of described thermal oxidation technology is oxygen, and intake is 0.1SLM ~ 100SLM.1. further, described thermal oxidation technology pass into the mist that gas is oxygen and hydrogen, the intake of oxygen and hydrogen is respectively 0.1SLM ~ 50SLM.
Further, the cross section of described bridging structure is circular.
Further, the diameter of the circular cross-section of described bridging structure is 5nm ~ 50nm.
Further, the spacing of adjacent bridging structure is 5nm ~ 50nm.
In sum, semiconductor device of the present invention and manufacture method thereof, by forming groove first in a silicon substrate, and after trenched side-wall forms barrier bed, continue to increase gash depth with the silicon substrate exposed on the bottom surface and partial sidewall of described groove, then thermal oxidation technology is carried out, the partial silicon substrate exposed on the bottom surface and partial sidewall of described groove is made to form silicon oxide layer, and the partial silicon substrate that the layer that is blocked blocks is not oxidized, thus after silicon oxide layer is removed, form pan in a silicon substrate, be positioned at not removed silicon material above pan and then form bridging structure above the pan that is located at, described semiconductor device can replace prior art silicon on insulated substrate, the bridging structure of silicon substrate can form semiconductor nanowire transistor structure, and the size of bridging structure preferably can be controlled by the process conditions in controlled oxidization process, for the semiconductor nanowire transistor structure of follow-up formation provides accurate size Control.
Accompanying drawing explanation
Fig. 1 is the vertical view of semiconductor device described in one embodiment of the invention.
Fig. 2 is the profile along AA ' direction in Fig. 1.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.
Fig. 4 ~ Figure 10 is the structural representation in the manufacture process of semiconductor device in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 1 is the vertical view of semiconductor device described in one embodiment of the invention, Fig. 2 is the profile along AA ' direction in Fig. 1, composition graphs 1 and Fig. 2, the invention provides a kind of semiconductor device, at this semiconductor device for forming semiconductor nanowire transistor structure, described semiconductor device comprises silicon substrate 100, this silicon substrate 100 is formed with the bridging structure 110 that pan 108 arranges with the multiple flat shape be located on described pan 108.
In subsequent technique, bridging structure 110 on described pan 108 can form grid structure, grid structure is around the middle part of bridging structure 110, source electrode and drain electrode is formed in the bridging structure of grid structure both sides, carry out other known processing steps further, thus final formation semiconductor nanowire transistor structure, do not repeat them here.
Wherein, as shown in Figure 2, the cross section of described bridging structure 110 is circular, and described bridging structure 110 is overall cylindrical.The diameter of the circular cross-section of described bridging structure 110 is 5nm ~ 50nm, and the distance between adjacent bridging structure 110 is 5nm ~ 50nm.Distance between the diameter of the circular cross-section of described bridging structure 110 and bridging structure specifically can be determined according to the dimensional requirement of semiconductor nanowire transistor structure.
In conjunction with above-mentioned semiconductor device, the present invention also provides a kind of manufacture method of semiconductor device, comprises the following steps:
Step S01: provide silicon substrate, described silicon substrate covers hard mask layer;
Step S02: perform first time dry etch process, etched portions hard mask layer and silicon substrate, to form multiple groove;
Step S03: form barrier bed on the sidewall of described groove;
Step S04: perform second time dry etch process, etch described silicon substrate, increase the degree of depth of described groove;
Step S05: carry out thermal oxidation technology, forms silicon oxide layer in the silicon substrate that the layer that is not blocked blocks in described groove;
Step S06: remove described barrier bed and silicon oxide layer, to form pan and to be positioned at the multiple bridging structures on described pan on described silicon substrate.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention, Fig. 4 ~ Figure 10 is the structural representation in the manufacture process of semiconductor device in one embodiment of the invention, describes the manufacture method of semiconductor device of the present invention below in conjunction with Fig. 1 ~ Figure 10 in detail.
As shown in Figure 4, in step S01, provide silicon substrate 100, described silicon substrate 100 covers hard mask layer 102; The material of described hard mask layer 102 can be silicon nitride or silicon oxynitride; the thickness of described hard mask layer 102 can be 10nm ~ 500nm; be preferably wherein 100nm, adopt above-mentioned thickness in follow-up multiple etching process, to protect silicon substrate 100 not need the region etched.
As shown in Figure 5, in step S02, carry out first time dry etch process, hard mask layer 102 described in etched portions and silicon substrate 100, to form multiple grooves 200; Detailed process is: first on described hard mask layer 102, cover photoresist (not indicating in figure), utilize photoresist described in exposure, developing process patterning, expose the hard mask layer 102 for forming groove, then with described patterned photo glue for mask, etch described hard mask layer 102, until expose described silicon substrate 100, remove described patterned photo glue again, with described hard mask layer 102 for mask, silicon substrate 100 described in dry etching, thus form described groove 200.After first time dry etching, the depth H 1 of described groove 200 in described silicon substrate 100 is 5nm ~ 60nm, this depth bounds effectively can control the size of the bridging structure of follow-up formation, thus improves the mechanical strength of bridging structure while meeting the technological requirement of the size of bridging structure.
As shown in Figure 6 and Figure 7, in step S03, the sidewall of described groove 200 forms barrier bed 104; The forming step of described barrier bed 104 comprises: on described hard mask layer 102, the bottom surface of described groove 100 and deposited on sidewalls block film 104a; Then, etching remove be positioned on described hard mask layer 102 and the bottom surface of described groove 100 block film 104a, to form barrier bed 104 as shown in Figure 6 on the sidewall of described groove 200.Wherein, the thickness of described barrier bed 104 is 2nm ~ 20nm, the sidewall of groove 200 can form good interface, silicon substrate 100 region protecting it to block well.
As shown in Figure 8, in step S04, carry out second time dry etch process, etch described silicon substrate, increase the degree of depth of described groove 200; After described second time dry etching, the depth bounds H2 of described groove 200 in described silicon substrate 100 is 10nm ~ 500nm.
As shown in Figure 9, in step S05, carry out thermal oxidation technology, in the silicon substrate 100 that the layer 104 that is not blocked blocks, form silicon oxide layer 106 in described groove 200; The silicon substrate 100 exposed in groove 200 bottom surface and partial sidewall forms silicon oxide layer 106 in subsequent thermal oxidizing process, and partial silicon substrate 100 unreacted that the layer 104 that is blocked blocks, the silicon substrate 100 in this unreacted region follow-up by formation bridging structure.Wherein, carry out in thermal oxidation technology process, the temperature of described thermal oxidation technology is 600 DEG C ~ 1200 DEG C, time is 5 seconds ~ 10 hours, it is oxygen that thermal oxidation technology passes into gas, intake is 0.1SLM ~ 100SLM, or pass into the mist of oxygen and hydrogen, in mist, the intake of oxygen and hydrogen is respectively 0.1SLM ~ 50SLM (StandardLiterperMinute), by controlling intake, ambient temperature and time can the thickness that formed of controlled oxidization silicon layer 106, and then can control to be arranged in the silicon substrate 100 that oxidation reaction does not occur described barrier bed 104 sidewall.
Shown in composition graphs 9 and Figure 10, barrier bed 104 and silicon oxide layer 102 is removed in step S06, with the multiple bridging structures 110 forming pan 108 and be positioned on pan 108 on described silicon substrate 100, wherein the degree of depth of the final pan H3 formed is 10nm ~ 600nm, and the cross section of described bridging structure 110 is circular.
In subsequent technique, described bridging structure 110 on described pan 108 can form grid structure, grid structure is around the middle part of bridging structure 110, source electrode and drain electrode is formed in the bridging structure of grid structure both sides, carry out other processing steps further, thus final formation semiconductor nanowire transistor structure.Form the process technological means that be familiar with to by those of ordinary skill in the art of grid structure, source electrode, drain electrode, therefore repeat no more.
In sum, in sum, semiconductor device of the present invention and manufacture method thereof, by forming groove first in a silicon substrate, and after trenched side-wall forms barrier bed, continue to increase gash depth with the silicon substrate exposed on the bottom surface and partial sidewall of described groove, then thermal oxidation technology is carried out, the partial silicon substrate exposed on the bottom surface and partial sidewall of described groove is made to form silicon oxide layer, and the partial silicon substrate that the layer that is blocked blocks is not oxidized, thus after silicon oxide layer is removed, form pan in a silicon substrate, be positioned at not removed silicon material above pan and then form bridging structure above the pan that is located at, described semiconductor device can replace prior art silicon on insulated substrate, the bridging structure of silicon substrate can form semiconductor nanowire transistor structure, and the size of bridging structure preferably can be controlled by the process conditions in controlled oxidization process, for the semiconductor nanowire transistor structure of follow-up formation provides accurate size Control.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (9)
1. a manufacture method for semiconductor device, described semiconductor device, for forming semiconductor nanowire transistor structure, comprising:
Silicon substrate is provided, described silicon substrate covers hard mask layer;
Perform first time dry etch process, etched portions hard mask layer and silicon substrate, to form multiple groove, after performing first time dry etch process, the degree of depth of described groove in described silicon substrate is 5nm ~ 60nm;
The sidewall of described groove forms barrier bed;
Perform second time dry etch process, etch described silicon substrate, increase the degree of depth of described groove, after performing second time dry etch process, the degree of depth of described groove in described silicon substrate is 10nm ~ 500nm;
Carry out a thermal oxidation technology, in the silicon substrate that the layer that is not blocked blocks, form silicon oxide layer in described groove;
Remove described barrier bed and silicon oxide layer, to form pan and be positioned at the multiple bridging structures on described pan on described silicon substrate, the distance between adjacent bridging structure is 5nm ~ 50nm.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described hard mask layer is silicon nitride or silicon oxynitride, and the thickness of described hard mask layer is 10nm ~ 500nm.
3. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the forming step of described barrier bed comprises:
On described hard mask layer, the bottom surface of described groove and deposited on sidewalls block film;
Etching remove be positioned on described hard mask layer and the bottom surface of described groove block film, to form barrier bed on the sidewall of described groove.
4. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the thickness 2nm ~ 20nm of described barrier bed.
5. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the temperature of described thermal oxidation technology is 600 DEG C ~ 1200 DEG C, the time is 5 seconds ~ 10 hours.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the gas that passes into of described thermal oxidation technology is oxygen, and intake is 0.1SLM ~ 100SLM.
7. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described thermal oxidation technology pass into the mist that gas is oxygen and hydrogen, the intake of oxygen and hydrogen is respectively 0.1SLM ~ 50SLM.
8. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the cross section of described bridging structure is circular.
9. the manufacture method of semiconductor device as claimed in claim 8, it is characterized in that, the diameter in the cross section of described bridging structure is 5nm ~ 50nm.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295677A (en) * | 2007-04-27 | 2008-10-29 | 北京大学 | Production method of bulk silicon nano line transistor device |
| CN102110648A (en) * | 2009-12-24 | 2011-06-29 | 中国科学院微电子研究所 | Method for preparing bulk silicon gate-all-around metal oxide semiconductor field effect transistors |
| CN102315170A (en) * | 2011-05-26 | 2012-01-11 | 北京大学 | Method for manufacturing silicon nanowire FET (field effect transistor) based on wet etching |
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| FR2910456B1 (en) * | 2006-12-21 | 2018-02-09 | Commissariat A L'energie Atomique | METHOD FOR PRODUCING MICROFILS AND / OR NANOWIAS |
| US7884004B2 (en) * | 2009-02-04 | 2011-02-08 | International Business Machines Corporation | Maskless process for suspending and thinning nanowires |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295677A (en) * | 2007-04-27 | 2008-10-29 | 北京大学 | Production method of bulk silicon nano line transistor device |
| CN102110648A (en) * | 2009-12-24 | 2011-06-29 | 中国科学院微电子研究所 | Method for preparing bulk silicon gate-all-around metal oxide semiconductor field effect transistors |
| CN102315170A (en) * | 2011-05-26 | 2012-01-11 | 北京大学 | Method for manufacturing silicon nanowire FET (field effect transistor) based on wet etching |
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